b740942d2038cda538c6c5db819972ce4b10dda1
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / bios6_edma3_drv_sample_da830_cfg.c
1 /*******************************************************************************
2 **+--------------------------------------------------------------------------+**
3 **|                            ****                                          |**
4 **|                            ****                                          |**
5 **|                            ******o***                                    |**
6 **|                      ********_///_****                                   |**
7 **|                      ***** /_//_/ ****                                   |**
8 **|                       ** ** (__/ ****                                    |**
9 **|                           *********                                      |**
10 **|                            ****                                          |**
11 **|                            ***                                           |**
12 **|                                                                          |**
13 **|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
14 **|                        ALL RIGHTS RESERVED                               |**
15 **|                                                                          |**
16 **| Permission is hereby granted to licensees of Texas Instruments           |**
17 **| Incorporated (TI) products to use this computer program for the sole     |**
18 **| purpose of implementing a licensee product based on TI products.         |**
19 **| No other rights to reproduce, use, or disseminate this computer          |**
20 **| program, whether in part or in whole, are granted.                       |**
21 **|                                                                          |**
22 **| TI makes no representation or warranties with respect to the             |**
23 **| performance of this computer program, and specifically disclaims         |**
24 **| any responsibility for any damages, special or consequential,            |**
25 **| connected with the use of this program.                                  |**
26 **|                                                                          |**
27 **+--------------------------------------------------------------------------+**
28 *******************************************************************************/
30 /** \file   bios6_edma3_drv_sample_da830_cfg.c
32     \brief  SoC specific EDMA3 hardware related information like number of
33             transfer controllers, various interrupt ids etc. It is used while
34             interrupts enabling / disabling. It needs to be ported for different
35             SoCs.
37     (C) Copyright 2008, Texas Instruments, Inc
39     \version    1.0   Anuj Aggarwal         - Created
41  */
43 #include <ti/sdo/edma3/drv/edma3_drv.h>
46 /* DA830 Specific EDMA3 Information */
48 /** Number of PaRAM Sets available */
49 #define EDMA3_NUM_PARAMSET                              (128u)
51 /** Number of TCCS available */
52 #define EDMA3_NUM_TCC                                   (32u)
54 /** Number of Event Queues available */
55 #define EDMA3_NUM_EVTQUE                                (2u)
57 /** Number of Transfer Controllers available */
58 #define EDMA3_NUM_TC                                    (2u)
60 /** Interrupt no. for Transfer Completion */
61 #define EDMA3_CC_XFER_COMPLETION_INT                    (8u)
63 /** Interrupt no. for CC Error */
64 #define EDMA3_CC_ERROR_INT                              (56u)
66 /** Interrupt no. for TCs Error */
67 #define EDMA3_TC0_ERROR_INT                             (57u)
68 #define EDMA3_TC1_ERROR_INT                             (58u)
69 #define EDMA3_TC2_ERROR_INT                             (0u)
70 #define EDMA3_TC3_ERROR_INT                             (0u)
71 #define EDMA3_TC4_ERROR_INT                             (0u)
72 #define EDMA3_TC5_ERROR_INT                             (0u)
73 #define EDMA3_TC6_ERROR_INT                             (0u)
74 #define EDMA3_TC7_ERROR_INT                             (0u)
76 /**
77 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
78 * ECM events (SoC specific). These ECM events come
79 * under ECM block XXX (handling those specific ECM events). Normally, block
80 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
81 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
82 * is mapped to a specific HWI_INT YYY in the tcf file.
83 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
84 * to transfer completion interrupt.
85 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
86 * to CC error interrupts.
87 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
88 * to TC error interrupts.
89 */
90 #define EDMA3_HWI_INT_XFER_COMP                                                 (7u)
91 #define EDMA3_HWI_INT_CC_ERR                                                    (8u)
92 #define EDMA3_HWI_INT_TC_ERR                                                    (8u)
95 /**
96  * \brief Mapping of DMA channels 0-31 to Hardware Events from
97  * various peripherals, which use EDMA for data transfer.
98  * All channels need not be mapped, some can be free also.
99  * 1: Mapped
100  * 0: Not mapped
101  *
102  * This mapping will be used to allocate DMA channels when user passes
103  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
104  * copy). The same mapping is used to allocate the TCC when user passes
105  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
106  *
107  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
108  */
109                                                                                                           /* 31     0 */
110 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xCF3FFFFFu)
112 /**
113  * \brief Mapping of DMA channels 32-63 to Hardware Events from
114  * various peripherals, which use EDMA for data transfer.
115  * All channels need not be mapped, some can be free also.
116  * 1: Mapped
117  * 0: Not mapped
118  *
119  * This mapping will be used to allocate DMA channels when user passes
120  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
121  * copy). The same mapping is used to allocate the TCC when user passes
122  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
123  *
124  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
125  */
126 /* DMA channels 32-63 DOES NOT exist in DA830. */
127 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x0u)
130 /* Variable which will be used internally for referring number of Event Queues. */
131 unsigned int numEdma3EvtQue = EDMA3_NUM_EVTQUE;
133 /* Variable which will be used internally for referring number of TCs. */
134 unsigned int numEdma3Tc = EDMA3_NUM_TC;
136 /**
137  * Variable which will be used internally for referring transfer completion
138  * interrupt.
139  */
140 unsigned int ccXferCompInt = EDMA3_CC_XFER_COMPLETION_INT;
142 /**
143  * Variable which will be used internally for referring channel controller's
144  * error interrupt.
145  */
146 unsigned int ccErrorInt = EDMA3_CC_ERROR_INT;
148 /**
149  * Variable which will be used internally for referring transfer controllers'
150  * error interrupts.
151  */
152 unsigned int tcErrorInt[8] =    {
153                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
154                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
155                                 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
156                                 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT
157                                 };
159 /**
160  * Variables which will be used internally for referring the hardware interrupt
161  * for various EDMA3 interrupts.
162  */
163 unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
164 unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
165 unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
168 /* Driver Object Initialization Configuration */
169 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams =
170     {
171     /** Total number of DMA Channels supported by the EDMA3 Controller */
172     32u,
173     /** Total number of QDMA Channels supported by the EDMA3 Controller */
174     8u,
175     /** Total number of TCCs supported by the EDMA3 Controller */
176     32u,
177     /** Total number of PaRAM Sets supported by the EDMA3 Controller */
178     128u,
179     /** Total number of Event Queues in the EDMA3 Controller */
180     2u,
181     /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
182     2u,
183     /** Number of Regions on this EDMA3 controller */
184     4u,
186     /**
187      * \brief Channel mapping existence
188      * A value of 0 (No channel mapping) implies that there is fixed association
189      * for a channel number to a parameter entry number or, in other words,
190      * PaRAM entry n corresponds to channel n.
191      */
192     0u,
194     /** Existence of memory protection feature */
195     0u,
197     /** Global Register Region of CC Registers */
198     (void *)0x01C00000u,
199     /** Transfer Controller (TC) Registers */
200         {
201         (void *)0x01C08000u,
202         (void *)0x01C08400u,
203         (void *)NULL,
204         (void *)NULL,
205         (void *)NULL,
206         (void *)NULL,
207         (void *)NULL,
208         (void *)NULL
209         },
210     /** Interrupt no. for Transfer Completion */
211     EDMA3_CC_XFER_COMPLETION_INT,
212     /** Interrupt no. for CC Error */
213     EDMA3_CC_ERROR_INT,
214     /** Interrupt no. for TCs Error */
215         {
216         EDMA3_TC0_ERROR_INT,
217         EDMA3_TC1_ERROR_INT,
218         EDMA3_TC2_ERROR_INT,
219         EDMA3_TC3_ERROR_INT,
220         EDMA3_TC4_ERROR_INT,
221         EDMA3_TC5_ERROR_INT,
222         EDMA3_TC6_ERROR_INT,
223         EDMA3_TC7_ERROR_INT
224         },
226     /**
227      * \brief EDMA3 TC priority setting
228      *
229      * User can program the priority of the Event Queues
230      * at a system-wide level.  This means that the user can set the
231      * priority of an IO initiated by either of the TCs (Transfer Controllers)
232      * relative to IO initiated by the other bus masters on the
233      * device (ARM, DSP, USB, etc)
234      */
235         {
236         0u,
237         1u,
238         0u,
239         0u,
240         0u,
241         0u,
242         0u,
243         0u
244         },
245     /**
246      * \brief To Configure the Threshold level of number of events
247      * that can be queued up in the Event queues. EDMA3CC error register
248      * (CCERR) will indicate whether or not at any instant of time the
249      * number of events queued up in any of the event queues exceeds
250      * or equals the threshold/watermark value that is set
251      * in the queue watermark threshold register (QWMTHRA).
252      */
253         {
254         16u,
255         16u,
256         0u,
257         0u,
258         0u,
259         0u,
260         0u,
261         0u
262         },
264     /**
265      * \brief To Configure the Default Burst Size (DBS) of TCs.
266      * An optimally-sized command is defined by the transfer controller
267      * default burst size (DBS). Different TCs can have different
268      * DBS values. It is defined in Bytes.
269      */
270         {
271         16u,
272         16u,
273         0u,
274         0u,
275         0u,
276         0u,
277         0u,
278         0u
279         },
281     /**
282      * \brief Mapping from each DMA channel to a Parameter RAM set,
283      * if it exists, otherwise of no use.
284      */
285         {
286         0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
287         8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
288         16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
289         24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
290         /* DMA channels 32-63 DOES NOT exist in DA830. */
291         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
292         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
293         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
294         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
295         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
296         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
297         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
298         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
299         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
300         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
301         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
302         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
303         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
304         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
305         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
306         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
307         },
309      /**
310       * \brief Mapping from each DMA channel to a TCC. This specific
311       * TCC code will be returned when the transfer is completed
312       * on the mapped channel.
313       */
314         {
315         0u, 1u, 2u, 3u,
316         4u, 5u, 6u, 7u,
317         8u, 9u, 10u, 11u,
318         12u, 13u, 14u, 15u,
319         16u, 17u, 18u, 19u,
320         20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
321         24u, 25u, 26u, 27u,
322         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31,
323         /* DMA channels 32-63 DOES NOT exist in DA830. */
324         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
325         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
326         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
327         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
328         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
329         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
330         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
331         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
332         },
334     /**
335      * \brief Mapping of DMA channels to Hardware Events from
336      * various peripherals, which use EDMA for data transfer.
337      * All channels need not be mapped, some can be free also.
338      */
339         {
340         EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
341         EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
342         }
343     };
346 /* Driver Instance Initialization Configuration */
347 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig =
348     {
349         /* Resources owned by Region 1 */
350         /* ownPaRAMSets */
351         /* 31     0     63    32     95    64     127   96 */
352         {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
353         /* 159  128     191  160     223  192     255  224 */
354          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
355         /* 287  256     319  288     351  320     383  352 */
356          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
357         /* 415  384     447  416     479  448     511  480 */
358          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
360         /* ownDmaChannels */
361         /* 31     0     63    32 */
362         {0xFFFFFFFFu, 0x00000000u},
364         /* ownQdmaChannels */
365         /* 31     0 */
366         {0x000000FFu},
368         /* ownTccs */
369         /* 31     0     63    32 */
370         {0xFFFFFFFFu, 0x00000000u},
372         /* Resources reserved by Region 1 */
373         /* resvdPaRAMSets */
374         /* 31     0     63    32     95    64     127   96 */
375         {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
376         /* 159  128     191  160     223  192     255  224 */
377          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
378         /* 287  256     319  288     351  320     383  352 */
379          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
380         /* 415  384     447  416     479  448     511  480 */
381          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
383         /* resvdDmaChannels */
384         /* 31                                                       0 */
385         {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
386         /* 63                                                     32 */
387             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1},
389         /* resvdQdmaChannels */
390         /* 31     0 */
391         {0x00000000u},
393         /* resvdTccs */
394         /* 31                                                       0 */
395         {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
396         /* 63                                                     32 */
397             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}
398     };
401 /* End of File */