142cd13fa93360023af24bc787c2689c6eeac611
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_am335x_cfg.c
1 /*
2  * sample_am335x_cfg.c
3  *
4  * Platform specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES                     1u
45 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
47 uint16_t determineProcId(void)
48 {
49      return 0U;
50 }
52 int8_t*  getGlobalAddr(int8_t* addr)
53 {
54      return (addr); /* The address is already a global address */
55 }
57 uint16_t isGblConfigRequired(uint32_t dspNum)
58 {
59     (void) dspNum;
60         return 0U;
61 }
63 /* Semaphore handles */
64 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
66 /** Total number of DMA Channels supported by the EDMA3 Controller */
67 #define EDMA3_NUM_DMA_CHANNELS                        (64u)
68 /** Total number of QDMA Channels supported by the EDMA3 Controller */
69 #define EDMA3_NUM_QDMA_CHANNELS                       (8u)
70 /** Total number of TCCs supported by the EDMA3 Controller */
71 #define EDMA3_NUM_TCC                                 (64u)
72 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
73 #define EDMA3_NUM_PARAMSET                            (256u)
74 /** Total number of Event Queues in the EDMA3 Controller */
75 #define EDMA3_NUM_EVTQUE                              (3u)
76 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
77 #define EDMA3_NUM_TC                                  (3u)
78 /** Number of Regions on this EDMA3 controller */
79 #define EDMA3_NUM_REGION                              (8u)
83 /**
84  * \brief Channel mapping existence
85  * A value of 0 (No channel mapping) implies that there is fixed association
86  * for a channel number to a parameter entry number or, in other words,
87  * PaRAM entry n corresponds to channel n.
88  */
89 #define CHANNEL_MAPPING_EXISTENCE               (1u)
90 /** Existence of memory protection feature */
91 #define MEM_PROTECTION_EXISTENCE                (1u)
93 /** Global Register Region of CC Registers */
94 #define CC_BASE_ADDRESS                         (0x49000000u)
95 /** Transfer Controller 0 Registers */
96 #define TC0_BASE_ADDRESS                        (0x49800000u)
97 /** Transfer Controller 1 Registers */
98 #define TC1_BASE_ADDRESS                        (0x49900000u)
99 /** Transfer Controller 2 Registers */
100 #define TC2_BASE_ADDRESS                        (0x49A00000u)
101 /** Transfer Controller 3 Registers */
102 #define TC3_BASE_ADDRESS                        NULL
103 /** Transfer Controller 4 Registers */
104 #define TC4_BASE_ADDRESS                        NULL
105 /** Transfer Controller 5 Registers */
106 #define TC5_BASE_ADDRESS                        NULL
107 /** Transfer Controller 6 Registers */
108 #define TC6_BASE_ADDRESS                        NULL
109 /** Transfer Controller 7 Registers */
110 #define TC7_BASE_ADDRESS                        NULL
112 /** Interrupt no. for Transfer Completion */
113 #define EDMA3_CC_XFER_COMPLETION_INT                  (12u)
114 /** Interrupt no. for CC Error */
115 #define EDMA3_CC_ERROR_INT                            (14u)
116 /** Interrupt no. for TC 0 Error */
117 #define EDMA3_TC0_ERROR_INT                           (112u)
118 /** Interrupt no. for TC 1 Error */
119 #define EDMA3_TC1_ERROR_INT                           (113u)
120 /** Interrupt no. for TC 2 Error */
121 #define EDMA3_TC2_ERROR_INT                           (114u)
122 /** Interrupt no. for TC 3 Error */
123 #define EDMA3_TC3_ERROR_INT                           (0u)
124 /** Interrupt no. for TC 4 Error */
125 #define EDMA3_TC4_ERROR_INT                           (0u)
126 /** Interrupt no. for TC 5 Error */
127 #define EDMA3_TC5_ERROR_INT                           (0u)
128 /** Interrupt no. for TC 6 Error */
129 #define EDMA3_TC6_ERROR_INT                           (0u)
130 /** Interrupt no. for TC 7 Error */
131 #define EDMA3_TC7_ERROR_INT                           (0u)
133 /**
134  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
135  * ECM events (SoC specific). These ECM events come
136  * under ECM block XXX (handling those specific ECM events). Normally, block
137  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
138  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
139  * is mapped to a specific HWI_INT YYY in the tcf file.
140  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
141  * to transfer completion interrupt.
142  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
143  * to CC error interrupts.
144  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
145  * to TC error interrupts.
146  */
147 /* EDMA 0 */
149 #define EDMA3_HWI_INT_XFER_COMP                           (7U)
150 #define EDMA3_HWI_INT_CC_ERR                              (7U)
151 #define EDMA3_HWI_INT_TC0_ERR                             (10U)
152 #define EDMA3_HWI_INT_TC1_ERR                             (10U)
153 #define EDMA3_HWI_INT_TC2_ERR                             (10U)
155 /**
156  * \brief Mapping of DMA channels 0-31 to Hardware Events from
157  * various peripherals, which use EDMA for data transfer.
158  * All channels need not be mapped, some can be free also.
159  * 1: Mapped
160  * 0: Not mapped
161  *
162  * This mapping will be used to allocate DMA channels when user passes
163  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
164  * copy). The same mapping is used to allocate the TCC when user passes
165  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
166  *
167  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
168  */
169                                                                                                 /* 31     0 */
170 #define DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFCFCFFFu)
173 /**
174  * \brief Mapping of DMA channels 32-63 to Hardware Events from
175  * various peripherals, which use EDMA for data transfer.
176  * All channels need not be mapped, some can be free also.
177  * 1: Mapped
178  * 0: Not mapped
179  *
180  * This mapping will be used to allocate DMA channels when user passes
181  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
182  * copy). The same mapping is used to allocate the TCC when user passes
183  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
184  *
185  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
186  */
187 /* DMA channels 32-63 DOES NOT exist in DA830. */
188 #define DMA_CHANNEL_TO_EVENT_MAPPING_1          (0xFF3FFFC0u)
190 /* Variable which will be used internally for referring number of Event Queues*/
191 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {EDMA3_NUM_EVTQUE};
193 /* Variable which will be used internally for referring number of TCs.        */
194 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {EDMA3_NUM_TC};
196 /**
197  * Variable which will be used internally for referring transfer completion
198  * interrupt.
199  */
200 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
201                                                         {
202                                                         EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u, 0u,
203                                                         0u, 0u, 0u, 0u,
204                                                         },
205                         };
207 /**
208  * Variable which will be used internally for referring channel controller's
209  * error interrupt.
210  */
211 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
213 /**
214  * Variable which will be used internally for referring transfer controllers'
215  * error interrupts.
216  */
217 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =    {
218                                 {
219                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
220                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
221                                 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
222                                 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
223                                 }
224                             };
226 /**
227  * Variables which will be used internally for referring the hardware interrupt
228  * for various EDMA3 interrupts.
229  */
230 uint32_t hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
231 uint32_t hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
232 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
234     /* EDMA3 INSTANCE# 0 */
235     {
236         EDMA3_HWI_INT_TC0_ERR,
237         EDMA3_HWI_INT_TC1_ERR,
238         EDMA3_HWI_INT_TC2_ERR,
239         0,
240         0,
241         0,
242         0,
243         0
244     }
245 };
248 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
250     {
251     /** Total number of DMA Channels supported by the EDMA3 Controller */
252     EDMA3_NUM_DMA_CHANNELS,
253     /** Total number of QDMA Channels supported by the EDMA3 Controller */
254     EDMA3_NUM_QDMA_CHANNELS,
255     /** Total number of TCCs supported by the EDMA3 Controller */
256     EDMA3_NUM_TCC,
257     /** Total number of PaRAM Sets supported by the EDMA3 Controller */
258     EDMA3_NUM_PARAMSET,
259     /** Total number of Event Queues in the EDMA3 Controller */
260     EDMA3_NUM_EVTQUE,
261     /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
262     EDMA3_NUM_TC,
263     /** Number of Regions on this EDMA3 controller */
264     EDMA3_NUM_REGION,
266     /**
267      * \brief Channel mapping existence
268      * A value of 0 (No channel mapping) implies that there is fixed association
269      * for a channel number to a parameter entry number or, in other words,
270      * PaRAM entry n corresponds to channel n.
271      */
272     CHANNEL_MAPPING_EXISTENCE,
274     /** Existence of memory protection feature */
275     MEM_PROTECTION_EXISTENCE,
277     /** Global Register Region of CC Registers */
278     (void *)(CC_BASE_ADDRESS),
279     /** Transfer Controller (TC) Registers */
280         {
281         (void *)(TC0_BASE_ADDRESS),
282         (void *)(TC1_BASE_ADDRESS),
283         (void *)(TC2_BASE_ADDRESS),
284         (void *)(TC3_BASE_ADDRESS),
285         (void *)(TC4_BASE_ADDRESS),
286         (void *)(TC5_BASE_ADDRESS),
287         (void *)(TC6_BASE_ADDRESS),
288         (void *)(TC7_BASE_ADDRESS)
289         },
290     /** Interrupt no. for Transfer Completion */
291     EDMA3_CC_XFER_COMPLETION_INT,
292     /** Interrupt no. for CC Error */
293     EDMA3_CC_ERROR_INT,
294     /** Interrupt no. for TCs Error */
295         {
296         EDMA3_TC0_ERROR_INT,
297         EDMA3_TC1_ERROR_INT,
298         EDMA3_TC2_ERROR_INT,
299         EDMA3_TC3_ERROR_INT,
300         EDMA3_TC4_ERROR_INT,
301         EDMA3_TC5_ERROR_INT,
302         EDMA3_TC6_ERROR_INT,
303         EDMA3_TC7_ERROR_INT
304         },
306    /**
307      * \brief EDMA3 TC priority setting
308      *
309      * User can program the priority of the Event Queues
310      * at a system-wide level.  This means that the user can set the
311      * priority of an IO initiated by either of the TCs (Transfer Controllers)
312      * relative to IO initiated by the other bus masters on the
313      * device (ARM, DSP, USB, etc)
314      */
315         {
316         0u,
317         1u,
318         2u,
319         0u,
320         0u,
321         0u,
322         0u,
323         0u
324         },
325     /**
326      * \brief To Configure the Threshold level of number of events
327      * that can be queued up in the Event queues. EDMA3CC error register
328      * (CCERR) will indicate whether or not at any instant of time the
329      * number of events queued up in any of the event queues exceeds
330      * or equals the threshold/watermark value that is set
331      * in the queue watermark threshold register (QWMTHRA).
332      */
333         {
334         16u,
335         16u,
336         16u,
337         0u,
338         0u,
339         0u,
340         0u,
341         0u
342         },
344     /**
345      * \brief To Configure the Default Burst Size (DBS) of TCs.
346      * An optimally-sized command is defined by the transfer controller
347      * default burst size (DBS). Different TCs can have different
348      * DBS values. It is defined in Bytes.
349      */
350         {
351         16u,
352         16u,
353         16u,
354         0u,
355         0u,
356         0u,
357         0u,
358         0u
359         },
361     /**
362      * \brief Mapping from each DMA channel to a Parameter RAM set,
363      * if it exists, otherwise of no use.
364      */
365 #ifdef EDMA3_RES_USER_REQ
366         {
367             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
368             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
369             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
370             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
371             32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
372             40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
373             48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
374             56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
375         },
376 #else
377         {
378         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
379         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
380         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
381         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
382         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
383         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
384         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
385         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
386         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
387         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
388         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
389         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
390         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
391         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
392         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
393         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
394         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
395         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
396         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
397         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
398         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
399         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
400         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
401         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
402         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
403         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
404         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
405         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
406         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
407         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
408         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
409         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP
410         },
411 #endif
413      /**
414       * \brief Mapping from each DMA channel to a TCC. This specific
415       * TCC code will be returned when the transfer is completed
416       * on the mapped channel.
417       */
418         {
419         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
420         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
421                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
422                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
423                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
424                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
425                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
426                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
427         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
428                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
429                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
430                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
431                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
432                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
433                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
434                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP
435         },
437     /**
438      * \brief Mapping of DMA channels to Hardware Events from
439      * various peripherals, which use EDMA for data transfer.
440      * All channels need not be mapped, some can be free also.
441      */
442         {
443         DMA_CHANNEL_TO_EVENT_MAPPING_0,
444         DMA_CHANNEL_TO_EVENT_MAPPING_1
445         }
446     }
447 };
450 /* Default DRV Instance Initialization Configuration */
451 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM_REGION] =
453         {
455           {
456             /* Resources owned by Region 0 */
457             /* ownPaRAMSets */
458 #ifdef EDMA3_RES_USER_REQ
459             /* 31     0     63    32     95    64     127   96 */
460             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
461             /* 159  128     191  160     223  192     255  224 */
462             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
463             /* 287  256     319  288     351  320     383  352 */
464              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
465             /* 415  384     447  416     479  448     511  480 */
466              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
467 #else
468             /* 31     0     63    32     95    64     127   96 */
469             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
470             /* 159  128     191  160     223  192     255  224 */
471             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
472             /* 287  256     319  288     351  320     383  352 */
473              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
474             /* 415  384     447  416     479  448     511  480 */
475              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
476 #endif
478             /* ownDmaChannels */
479             /* 31     0     63    32 */
480             {0xFFFFFFFFu, 0xFFFFFFFFu},
482             /* ownQdmaChannels */
483             /* 31     0 */
484             {0x000000FFU},
486             /* ownTccs */
487             /* 31     0     63    32 */
488             {0xFFFFFFFFU, 0xFFFFFFFFU},
490             /* Resources reserved by Region 0 */
491             /* resvdPaRAMSets */
492             /* 31     0     63    32     95    64     127   96 */
493             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
494             /* 159  128     191  160     223  192     255  224 */
495              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
496             /* 287  256     319  288     351  320     383  352 */
497              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
498             /* 415  384     447  416     479  448     511  480 */
499              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
501             /* resvdDmaChannels */
502             /* 31                                         0  63                                                  32 */
503             {0x00000000u, 0x00000000u},
505             /* resvdQdmaChannels */
506             /* 31     0 */
507             {0x00000000u},
509             /* resvdTccs */
510             /* 31                                         0  63                                                  32 */
511             {0x00000000u, 0x00000000u},
512           },
514           {
515             /* Resources owned by Region 1 */
516              /* ownPaRAMSets */
517 #ifdef EDMA3_RES_USER_REQ
518             /* 31     0     63    32     95    64     127   96 */
519             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
520             /* 159  128     191  160     223  192     255  224 */
521             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
522             /* 287  256     319  288     351  320     383  352 */
523              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
524             /* 415  384     447  416     479  448     511  480 */
525              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
526 #else
527             /* 31     0     63    32     95    64     127   96 */
528             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
529             /* 159  128     191  160     223  192     255  224 */
530              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
531             /* 287  256     319  288     351  320     383  352 */
532              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
533             /* 415  384     447  416     479  448     511  480 */
534              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
535 #endif
537             /* ownDmaChannels */
538             /* 31     0     63    32 */
539             {0x00000000u, 0x00000000u},
541             /* ownQdmaChannels */
542             /* 31     0 */
543             {0x00000000u},
545             /* ownTccs */
546             /* 31     0     63    32 */
547             {0x00000000u, 0x00000000u},
549             /* Resources reserved by Region 1 */
550             /* resvdPaRAMSets */
551             /* 31     0     63    32     95    64     127   96 */
552             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
553             /* 159  128     191  160     223  192     255  224 */
554              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
555             /* 287  256     319  288     351  320     383  352 */
556              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
557             /* 415  384     447  416     479  448     511  480 */
558              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
560             /* resvdDmaChannels */
561             /* 31     0     63    32 */
562             {0x00000000u, 0x00000000u},
564             /* resvdQdmaChannels */
565             /* 31     0 */
566             {0x00000000u},
568             /* resvdTccs */
569             /* 31     0     63    32 */
570             {0x00000000u, 0x00000000u},
571           },
573           {
574             /* Resources owned by Region 2 */
575              /* ownPaRAMSets */
576 #ifdef EDMA3_RES_USER_REQ
577             /* 31     0     63    32     95    64     127   96 */
578             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
579             /* 159  128     191  160     223  192     255  224 */
580             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
581             /* 287  256     319  288     351  320     383  352 */
582              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
583             /* 415  384     447  416     479  448     511  480 */
584              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
585 #else
586             /* 31     0     63    32     95    64     127   96 */
587             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
588             /* 159  128     191  160     223  192     255  224 */
589              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
590             /* 287  256     319  288     351  320     383  352 */
591              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
592             /* 415  384     447  416     479  448     511  480 */
593              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
594 #endif
596             /* ownDmaChannels */
597             /* 31     0     63    32 */
598             {0x00000000u, 0x00000000u},
600             /* ownQdmaChannels */
601             /* 31     0 */
602             {0x00000000u},
604             /* ownTccs */
605             /* 31     0     63    32 */
606             {0x00000000u, 0x00000000u},
608             /* Resources reserved by Region 2 */
609             /* resvdPaRAMSets */
610             /* 31     0     63    32     95    64     127   96 */
611             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
612             /* 159  128     191  160     223  192     255  224 */
613              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
614             /* 287  256     319  288     351  320     383  352 */
615              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
616             /* 415  384     447  416     479  448     511  480 */
617              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
619             /* resvdDmaChannels */
620             /* 31     0     63    32 */
621             {0x00000000u, 0x00000000u},
623             /* resvdQdmaChannels */
624             /* 31     0 */
625             {0x00000000u},
627             /* resvdTccs */
628             /* 31     0     63    32 */
629             {0x00000000u, 0x00000000u},
630           },
632           {
633             /* Resources owned by Region 3 */
634              /* ownPaRAMSets */
635 #ifdef EDMA3_RES_USER_REQ
636             /* 31     0     63    32     95    64     127   96 */
637             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
638             /* 159  128     191  160     223  192     255  224 */
639             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
640             /* 287  256     319  288     351  320     383  352 */
641              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
642             /* 415  384     447  416     479  448     511  480 */
643              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
644 #else
645             /* 31     0     63    32     95    64     127   96 */
646             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
647             /* 159  128     191  160     223  192     255  224 */
648              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
649             /* 287  256     319  288     351  320     383  352 */
650              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
651             /* 415  384     447  416     479  448     511  480 */
652              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
653 #endif
655             /* ownDmaChannels */
656             /* 31     0     63    32 */
657             {0x00000000u, 0x00000000u},
659             /* ownQdmaChannels */
660             /* 31     0 */
661             {0x00000000u},
663             /* ownTccs */
664             /* 31     0     63    32 */
665             {0x00000000u, 0x00000000u},
667             /* Resources reserved by Region 3 */
668             /* resvdPaRAMSets */
669             /* 31     0     63    32     95    64     127   96 */
670             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
671             /* 159  128     191  160     223  192     255  224 */
672              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
673             /* 287  256     319  288     351  320     383  352 */
674              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
675             /* 415  384     447  416     479  448     511  480 */
676              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
678             /* resvdDmaChannels */
679             /* 31     0     63    32 */
680             {0x00000000u, 0x00000000u},
682             /* resvdQdmaChannels */
683             /* 31     0 */
684             {0x00000000u},
686             /* resvdTccs */
687             /* 31     0     63    32 */
688             {0x00000000u, 0x00000000u},
689           },
691           {
692             /* Resources owned by Region 4 */
693              /* ownPaRAMSets */
694 #ifdef EDMA3_RES_USER_REQ
695             /* 31     0     63    32     95    64     127   96 */
696             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
697             /* 159  128     191  160     223  192     255  224 */
698             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
699             /* 287  256     319  288     351  320     383  352 */
700              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
701             /* 415  384     447  416     479  448     511  480 */
702              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
703 #else
704             /* 31     0     63    32     95    64     127   96 */
705             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
706             /* 159  128     191  160     223  192     255  224 */
707              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
708             /* 287  256     319  288     351  320     383  352 */
709              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
710             /* 415  384     447  416     479  448     511  480 */
711              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
712 #endif
714             /* ownDmaChannels */
715             /* 31     0     63    32 */
716             {0x00000000u, 0x00000000u},
718             /* ownQdmaChannels */
719             /* 31     0 */
720             {0x00000000u},
722             /* ownTccs */
723             /* 31     0     63    32 */
724             {0x00000000u, 0x00000000u},
726             /* Resources reserved by Region 4 */
727             /* resvdPaRAMSets */
728             /* 31     0     63    32     95    64     127   96 */
729             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
730             /* 159  128     191  160     223  192     255  224 */
731              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
732             /* 287  256     319  288     351  320     383  352 */
733              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
734             /* 415  384     447  416     479  448     511  480 */
735              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
737             /* resvdDmaChannels */
738             /* 31     0     63    32 */
739             {0x00000000u, 0x00000000u},
741             /* resvdQdmaChannels */
742             /* 31     0 */
743             {0x00000000u},
745             /* resvdTccs */
746             /* 31     0     63    32 */
747             {0x00000000u, 0x00000000u},
748           },
750           {
751             /* Resources owned by Region 5 */
752              /* ownPaRAMSets */
753 #ifdef EDMA3_RES_USER_REQ
754             /* 31     0     63    32     95    64     127   96 */
755             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
756             /* 159  128     191  160     223  192     255  224 */
757             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
758             /* 287  256     319  288     351  320     383  352 */
759              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
760             /* 415  384     447  416     479  448     511  480 */
761              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
762 #else
763             /* 31     0     63    32     95    64     127   96 */
764             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
765             /* 159  128     191  160     223  192     255  224 */
766              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
767             /* 287  256     319  288     351  320     383  352 */
768              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
769             /* 415  384     447  416     479  448     511  480 */
770              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
771 #endif
773             /* ownDmaChannels */
774             /* 31     0     63    32 */
775             {0x00000000u, 0x00000000u},
777             /* ownQdmaChannels */
778             /* 31     0 */
779             {0x00000000u},
781             /* ownTccs */
782             /* 31     0     63    32 */
783             {0x00000000u, 0x00000000u},
785             /* Resources reserved by Region 5 */
786             /* resvdPaRAMSets */
787             /* 31     0     63    32     95    64     127   96 */
788             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
789             /* 159  128     191  160     223  192     255  224 */
790              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
791             /* 287  256     319  288     351  320     383  352 */
792              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
793             /* 415  384     447  416     479  448     511  480 */
794              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
796             /* resvdDmaChannels */
797             /* 31     0     63    32 */
798             {0x00000000u, 0x00000000u},
800             /* resvdQdmaChannels */
801             /* 31     0 */
802             {0x00000000u},
804             /* resvdTccs */
805             /* 31     0     63    32 */
806             {0x00000000u, 0x00000000u},
807           },
809           {
810             /* Resources owned by Region 6 */
811              /* ownPaRAMSets */
812 #ifdef EDMA3_RES_USER_REQ
813             /* 31     0     63    32     95    64     127   96 */
814             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
815             /* 159  128     191  160     223  192     255  224 */
816             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
817             /* 287  256     319  288     351  320     383  352 */
818              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
819             /* 415  384     447  416     479  448     511  480 */
820              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
821 #else
822             /* 31     0     63    32     95    64     127   96 */
823             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
824             /* 159  128     191  160     223  192     255  224 */
825              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
826             /* 287  256     319  288     351  320     383  352 */
827              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
828             /* 415  384     447  416     479  448     511  480 */
829              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
830 #endif
832             /* ownDmaChannels */
833             /* 31     0     63    32 */
834             {0x00000000u, 0x00000000u},
836             /* ownQdmaChannels */
837             /* 31     0 */
838             {0x00000000u},
840             /* ownTccs */
841             /* 31     0     63    32 */
842             {0x00000000u, 0x00000000u},
844             /* Resources reserved by Region 6 */
845             /* resvdPaRAMSets */
846             /* 31     0     63    32     95    64     127   96 */
847             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
848             /* 159  128     191  160     223  192     255  224 */
849              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
850             /* 287  256     319  288     351  320     383  352 */
851              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
852             /* 415  384     447  416     479  448     511  480 */
853              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
855             /* resvdDmaChannels */
856             /* 31     0     63    32 */
857             {0x00000000u, 0x00000000u},
859             /* resvdQdmaChannels */
860             /* 31     0 */
861             {0x00000000u},
863             /* resvdTccs */
864             /* 31     0     63    32 */
865             {0x00000000u, 0x00000000u},
866           },
868           {
869             /* Resources owned by Region 7 */
870              /* ownPaRAMSets */
871 #ifdef EDMA3_RES_USER_REQ
872             /* 31     0     63    32     95    64     127   96 */
873             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
874             /* 159  128     191  160     223  192     255  224 */
875             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
876             /* 287  256     319  288     351  320     383  352 */
877              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
878             /* 415  384     447  416     479  448     511  480 */
879              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
880 #else
881             /* 31     0     63    32     95    64     127   96 */
882             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
883             /* 159  128     191  160     223  192     255  224 */
884              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
885             /* 287  256     319  288     351  320     383  352 */
886              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
887             /* 415  384     447  416     479  448     511  480 */
888              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
889 #endif
891             /* ownDmaChannels */
892             /* 31     0     63    32 */
893             {0x00000000u, 0x00000000u},
895             /* ownQdmaChannels */
896             /* 31     0 */
897             {0x00000000u},
899             /* ownTccs */
900             /* 31     0     63    32 */
901             {0x00000000u, 0x00000000u},
903             /* Resources reserved by Region 7 */
904             /* resvdPaRAMSets */
905             /* 31     0     63    32     95    64     127   96 */
906             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
907             /* 159  128     191  160     223  192     255  224 */
908              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
909             /* 287  256     319  288     351  320     383  352 */
910              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
911             /* 415  384     447  416     479  448     511  480 */
912              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
914             /* resvdDmaChannels */
915             /* 31     0     63    32 */
916             {0x00000000u, 0x00000000u},
918             /* resvdQdmaChannels */
919             /* 31     0 */
920             {0x00000000u},
922             /* resvdTccs */
923             /* 31     0     63    32 */
924             {0x00000000u, 0x00000000u},
925           }
926         }
927 };
929 /* End of File */