d1ef5967984e7b2f7a29b45f2c4e01f0ba9cafd8
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_am335x_cfg.c
1 /*
2 * sample_am335x_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 1u
45 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
47 uint16_t determineProcId(void)
48 {
49 return 0U;
50 }
52 int8_t* getGlobalAddr(int8_t* addr)
53 {
54 return (addr); /* The address is already a global address */
55 }
57 uint16_t isGblConfigRequired(uint32_t dspNum)
58 {
59 (void) dspNum;
60 return 0U;
61 }
63 /* Semaphore handles */
64 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
66 /** Total number of DMA Channels supported by the EDMA3 Controller */
67 #define EDMA3_NUM_DMA_CHANNELS (64u)
68 /** Total number of QDMA Channels supported by the EDMA3 Controller */
69 #define EDMA3_NUM_QDMA_CHANNELS (8u)
70 /** Total number of TCCs supported by the EDMA3 Controller */
71 #define EDMA3_NUM_TCC (64u)
72 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
73 #define EDMA3_NUM_PARAMSET (256u)
74 /** Total number of Event Queues in the EDMA3 Controller */
75 #define EDMA3_NUM_EVTQUE (3u)
76 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
77 #define EDMA3_NUM_TC (3u)
78 /** Number of Regions on this EDMA3 controller */
79 #define EDMA3_NUM_REGION (8u)
83 /**
84 * \brief Channel mapping existence
85 * A value of 0 (No channel mapping) implies that there is fixed association
86 * for a channel number to a parameter entry number or, in other words,
87 * PaRAM entry n corresponds to channel n.
88 */
89 #define CHANNEL_MAPPING_EXISTENCE (1u)
90 /** Existence of memory protection feature */
91 #define MEM_PROTECTION_EXISTENCE (1u)
93 /** Global Register Region of CC Registers */
94 #define CC_BASE_ADDRESS (0x49000000u)
95 /** Transfer Controller 0 Registers */
96 #define TC0_BASE_ADDRESS (0x49800000u)
97 /** Transfer Controller 1 Registers */
98 #define TC1_BASE_ADDRESS (0x49900000u)
99 /** Transfer Controller 2 Registers */
100 #define TC2_BASE_ADDRESS (0x49A00000u)
101 /** Transfer Controller 3 Registers */
102 #define TC3_BASE_ADDRESS NULL
103 /** Transfer Controller 4 Registers */
104 #define TC4_BASE_ADDRESS NULL
105 /** Transfer Controller 5 Registers */
106 #define TC5_BASE_ADDRESS NULL
107 /** Transfer Controller 6 Registers */
108 #define TC6_BASE_ADDRESS NULL
109 /** Transfer Controller 7 Registers */
110 #define TC7_BASE_ADDRESS NULL
112 /** Interrupt no. for Transfer Completion */
113 #define EDMA3_CC_XFER_COMPLETION_INT (12u)
114 /** Interrupt no. for CC Error */
115 #define EDMA3_CC_ERROR_INT (14u)
116 /** Interrupt no. for TC 0 Error */
117 #define EDMA3_TC0_ERROR_INT (112u)
118 /** Interrupt no. for TC 1 Error */
119 #define EDMA3_TC1_ERROR_INT (113u)
120 /** Interrupt no. for TC 2 Error */
121 #define EDMA3_TC2_ERROR_INT (114u)
122 /** Interrupt no. for TC 3 Error */
123 #define EDMA3_TC3_ERROR_INT (0u)
124 /** Interrupt no. for TC 4 Error */
125 #define EDMA3_TC4_ERROR_INT (0u)
126 /** Interrupt no. for TC 5 Error */
127 #define EDMA3_TC5_ERROR_INT (0u)
128 /** Interrupt no. for TC 6 Error */
129 #define EDMA3_TC6_ERROR_INT (0u)
130 /** Interrupt no. for TC 7 Error */
131 #define EDMA3_TC7_ERROR_INT (0u)
133 /**
134 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
135 * ECM events (SoC specific). These ECM events come
136 * under ECM block XXX (handling those specific ECM events). Normally, block
137 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
138 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
139 * is mapped to a specific HWI_INT YYY in the tcf file.
140 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
141 * to transfer completion interrupt.
142 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
143 * to CC error interrupts.
144 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
145 * to TC error interrupts.
146 */
147 /* EDMA 0 */
149 #define EDMA3_HWI_INT_XFER_COMP (7U)
150 #define EDMA3_HWI_INT_CC_ERR (7U)
151 #define EDMA3_HWI_INT_TC0_ERR (10U)
152 #define EDMA3_HWI_INT_TC1_ERR (10U)
153 #define EDMA3_HWI_INT_TC2_ERR (10U)
155 /**
156 * \brief Mapping of DMA channels 0-31 to Hardware Events from
157 * various peripherals, which use EDMA for data transfer.
158 * All channels need not be mapped, some can be free also.
159 * 1: Mapped
160 * 0: Not mapped
161 *
162 * This mapping will be used to allocate DMA channels when user passes
163 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
164 * copy). The same mapping is used to allocate the TCC when user passes
165 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
166 *
167 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
168 */
169 /* 31 0 */
170 #define DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFFCFCFFFu)
173 /**
174 * \brief Mapping of DMA channels 32-63 to Hardware Events from
175 * various peripherals, which use EDMA for data transfer.
176 * All channels need not be mapped, some can be free also.
177 * 1: Mapped
178 * 0: Not mapped
179 *
180 * This mapping will be used to allocate DMA channels when user passes
181 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
182 * copy). The same mapping is used to allocate the TCC when user passes
183 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
184 *
185 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
186 */
187 /* DMA channels 32-63 DOES NOT exist in DA830. */
188 #define DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF3FFFC0u)
190 /* Variable which will be used internally for referring number of Event Queues*/
191 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
193 /* Variable which will be used internally for referring number of TCs. */
194 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
196 /**
197 * Variable which will be used internally for referring transfer completion
198 * interrupt.
199 */
200 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
201 {
202 EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u, 0u,
203 0u, 0u, 0u, 0u,
204 },
205 };
207 /**
208 * Variable which will be used internally for referring channel controller's
209 * error interrupt.
210 */
211 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
213 /**
214 * Variable which will be used internally for referring transfer controllers'
215 * error interrupts.
216 */
217 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
218 {
219 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
220 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
221 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
222 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
223 }
224 };
226 /**
227 * Variables which will be used internally for referring the hardware interrupt
228 * for various EDMA3 interrupts.
229 */
230 uint32_t hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
231 uint32_t hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
232 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
233 {
234 /* EDMA3 INSTANCE# 0 */
235 {
236 EDMA3_HWI_INT_TC0_ERR,
237 EDMA3_HWI_INT_TC1_ERR,
238 EDMA3_HWI_INT_TC2_ERR,
239 0,
240 0,
241 0,
242 0,
243 0
244 }
245 };
248 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
249 {
250 {
251 /** Total number of DMA Channels supported by the EDMA3 Controller */
252 EDMA3_NUM_DMA_CHANNELS,
253 /** Total number of QDMA Channels supported by the EDMA3 Controller */
254 EDMA3_NUM_QDMA_CHANNELS,
255 /** Total number of TCCs supported by the EDMA3 Controller */
256 EDMA3_NUM_TCC,
257 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
258 EDMA3_NUM_PARAMSET,
259 /** Total number of Event Queues in the EDMA3 Controller */
260 EDMA3_NUM_EVTQUE,
261 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
262 EDMA3_NUM_TC,
263 /** Number of Regions on this EDMA3 controller */
264 EDMA3_NUM_REGION,
266 /**
267 * \brief Channel mapping existence
268 * A value of 0 (No channel mapping) implies that there is fixed association
269 * for a channel number to a parameter entry number or, in other words,
270 * PaRAM entry n corresponds to channel n.
271 */
272 CHANNEL_MAPPING_EXISTENCE,
274 /** Existence of memory protection feature */
275 MEM_PROTECTION_EXISTENCE,
277 /** Global Register Region of CC Registers */
278 (void *)(CC_BASE_ADDRESS),
279 /** Transfer Controller (TC) Registers */
280 {
281 (void *)(TC0_BASE_ADDRESS),
282 (void *)(TC1_BASE_ADDRESS),
283 (void *)(TC2_BASE_ADDRESS),
284 (void *)(TC3_BASE_ADDRESS),
285 (void *)(TC4_BASE_ADDRESS),
286 (void *)(TC5_BASE_ADDRESS),
287 (void *)(TC6_BASE_ADDRESS),
288 (void *)(TC7_BASE_ADDRESS)
289 },
290 /** Interrupt no. for Transfer Completion */
291 EDMA3_CC_XFER_COMPLETION_INT,
292 /** Interrupt no. for CC Error */
293 EDMA3_CC_ERROR_INT,
294 /** Interrupt no. for TCs Error */
295 {
296 EDMA3_TC0_ERROR_INT,
297 EDMA3_TC1_ERROR_INT,
298 EDMA3_TC2_ERROR_INT,
299 EDMA3_TC3_ERROR_INT,
300 EDMA3_TC4_ERROR_INT,
301 EDMA3_TC5_ERROR_INT,
302 EDMA3_TC6_ERROR_INT,
303 EDMA3_TC7_ERROR_INT
304 },
306 /**
307 * \brief EDMA3 TC priority setting
308 *
309 * User can program the priority of the Event Queues
310 * at a system-wide level. This means that the user can set the
311 * priority of an IO initiated by either of the TCs (Transfer Controllers)
312 * relative to IO initiated by the other bus masters on the
313 * device (ARM, DSP, USB, etc)
314 */
315 {
316 0u,
317 1u,
318 2u,
319 0u,
320 0u,
321 0u,
322 0u,
323 0u
324 },
325 /**
326 * \brief To Configure the Threshold level of number of events
327 * that can be queued up in the Event queues. EDMA3CC error register
328 * (CCERR) will indicate whether or not at any instant of time the
329 * number of events queued up in any of the event queues exceeds
330 * or equals the threshold/watermark value that is set
331 * in the queue watermark threshold register (QWMTHRA).
332 */
333 {
334 16u,
335 16u,
336 16u,
337 0u,
338 0u,
339 0u,
340 0u,
341 0u
342 },
344 /**
345 * \brief To Configure the Default Burst Size (DBS) of TCs.
346 * An optimally-sized command is defined by the transfer controller
347 * default burst size (DBS). Different TCs can have different
348 * DBS values. It is defined in Bytes.
349 */
350 {
351 16u,
352 16u,
353 16u,
354 0u,
355 0u,
356 0u,
357 0u,
358 0u
359 },
361 /**
362 * \brief Mapping from each DMA channel to a Parameter RAM set,
363 * if it exists, otherwise of no use.
364 */
365 {
366 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
367 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
368 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
369 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
370 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
371 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
372 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
373 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
374 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
375 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
376 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
377 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
378 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
379 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
380 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
381 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
382 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
383 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
384 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
385 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
386 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
387 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
388 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
389 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
390 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
391 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
392 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
393 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
394 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
395 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
396 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
397 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP
398 },
400 /**
401 * \brief Mapping from each DMA channel to a TCC. This specific
402 * TCC code will be returned when the transfer is completed
403 * on the mapped channel.
404 */
405 {
406 0u, 1u, 2u, 3u,
407 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
408 8u, 9u, 10u, 11u,
409 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, 14u, 15u,
410 16u, 17u, 18u, 19u,
411 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, 22u, 23u,
412 24u, 25u, 26u, 27u,
413 28u, 29u, 30u, 31u,
414 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
415 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, 38u, 39u,
416 40u, 41u, 42u, 43u,
417 44u, 45u, 46u, 47u,
418 48u, 49u, 50u, 51u,
419 52u, 53u, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
420 56u, 57u, 58u, 59u,
421 60u, 61u, 62u, 63u
422 },
424 /**
425 * \brief Mapping of DMA channels to Hardware Events from
426 * various peripherals, which use EDMA for data transfer.
427 * All channels need not be mapped, some can be free also.
428 */
429 {
430 DMA_CHANNEL_TO_EVENT_MAPPING_0,
431 DMA_CHANNEL_TO_EVENT_MAPPING_1
432 }
433 }
434 };
437 /* Default DRV Instance Initialization Configuration */
438 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM_REGION] =
439 {
440 {
442 {
443 /* Resources owned by Region 0 */
444 /* ownPaRAMSets */
445 /* 31 0 63 32 95 64 127 96 */
446 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
447 /* 159 128 191 160 223 192 255 224 */
448 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
449 /* 287 256 319 288 351 320 383 352 */
450 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
451 /* 415 384 447 416 479 448 511 480 */
452 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
454 /* ownDmaChannels */
455 /* 31 0 63 32 */
456 {0x00303000u, 0x00C0003Fu},
458 /* ownQdmaChannels */
459 /* 31 0 */
460 {0x000000FFu},
462 /* ownTccs */
463 /* 31 0 63 32 */
464 {0x00303000u, 0x00C0003Fu},
466 /* Resources reserved by Region 0 */
467 /* resvdPaRAMSets */
468 /* 31 0 63 32 95 64 127 96 */
469 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
470 /* 159 128 191 160 223 192 255 224 */
471 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
472 /* 287 256 319 288 351 320 383 352 */
473 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
474 /* 415 384 447 416 479 448 511 480 */
475 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
477 /* resvdDmaChannels */
478 /* 31 0 63 32 */
479 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
481 /* resvdQdmaChannels */
482 /* 31 0 */
483 {0x00000000u},
485 /* resvdTccs */
486 /* 31 0 63 32 */
487 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
488 },
490 {
491 /* Resources owned by Region 1 */
492 /* ownPaRAMSets */
493 /* 31 0 63 32 95 64 127 96 */
494 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
495 /* 159 128 191 160 223 192 255 224 */
496 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
497 /* 287 256 319 288 351 320 383 352 */
498 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
499 /* 415 384 447 416 479 448 511 480 */
500 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
502 /* ownDmaChannels */
503 /* 31 0 63 32 */
504 {0x00000000u, 0x00000000u},
506 /* ownQdmaChannels */
507 /* 31 0 */
508 {0x00000000u},
510 /* ownTccs */
511 /* 31 0 63 32 */
512 {0x00000000u, 0x00000000u},
514 /* Resources reserved by Region 1 */
515 /* resvdPaRAMSets */
516 /* 31 0 63 32 95 64 127 96 */
517 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
518 /* 159 128 191 160 223 192 255 224 */
519 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
520 /* 287 256 319 288 351 320 383 352 */
521 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
522 /* 415 384 447 416 479 448 511 480 */
523 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
525 /* resvdDmaChannels */
526 /* 31 0 63 32 */
527 {0x00000000u, 0x00000000u},
529 /* resvdQdmaChannels */
530 /* 31 0 */
531 {0x00000000u},
533 /* resvdTccs */
534 /* 31 0 63 32 */
535 {0x00000000u, 0x00000000u},
536 },
538 {
539 /* Resources owned by Region 2 */
540 /* ownPaRAMSets */
541 /* 31 0 63 32 95 64 127 96 */
542 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
543 /* 159 128 191 160 223 192 255 224 */
544 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
545 /* 287 256 319 288 351 320 383 352 */
546 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
547 /* 415 384 447 416 479 448 511 480 */
548 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
550 /* ownDmaChannels */
551 /* 31 0 63 32 */
552 {0x00000000u, 0x00000000u},
554 /* ownQdmaChannels */
555 /* 31 0 */
556 {0x00000000u},
558 /* ownTccs */
559 /* 31 0 63 32 */
560 {0x00000000u, 0x00000000u},
562 /* Resources reserved by Region 2 */
563 /* resvdPaRAMSets */
564 /* 31 0 63 32 95 64 127 96 */
565 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
566 /* 159 128 191 160 223 192 255 224 */
567 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
568 /* 287 256 319 288 351 320 383 352 */
569 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
570 /* 415 384 447 416 479 448 511 480 */
571 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
573 /* resvdDmaChannels */
574 /* 31 0 63 32 */
575 {0x00000000u, 0x00000000u},
577 /* resvdQdmaChannels */
578 /* 31 0 */
579 {0x00000000u},
581 /* resvdTccs */
582 /* 31 0 63 32 */
583 {0x00000000u, 0x00000000u},
584 },
586 {
587 /* Resources owned by Region 3 */
588 /* ownPaRAMSets */
589 /* 31 0 63 32 95 64 127 96 */
590 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
591 /* 159 128 191 160 223 192 255 224 */
592 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
593 /* 287 256 319 288 351 320 383 352 */
594 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
595 /* 415 384 447 416 479 448 511 480 */
596 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
598 /* ownDmaChannels */
599 /* 31 0 63 32 */
600 {0x00000000u, 0x00000000u},
602 /* ownQdmaChannels */
603 /* 31 0 */
604 {0x00000000u},
606 /* ownTccs */
607 /* 31 0 63 32 */
608 {0x00000000u, 0x00000000u},
610 /* Resources reserved by Region 3 */
611 /* resvdPaRAMSets */
612 /* 31 0 63 32 95 64 127 96 */
613 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
614 /* 159 128 191 160 223 192 255 224 */
615 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
616 /* 287 256 319 288 351 320 383 352 */
617 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
618 /* 415 384 447 416 479 448 511 480 */
619 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
621 /* resvdDmaChannels */
622 /* 31 0 63 32 */
623 {0x00000000u, 0x00000000u},
625 /* resvdQdmaChannels */
626 /* 31 0 */
627 {0x00000000u},
629 /* resvdTccs */
630 /* 31 0 63 32 */
631 {0x00000000u, 0x00000000u},
632 },
634 {
635 /* Resources owned by Region 4 */
636 /* ownPaRAMSets */
637 /* 31 0 63 32 95 64 127 96 */
638 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
639 /* 159 128 191 160 223 192 255 224 */
640 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
641 /* 287 256 319 288 351 320 383 352 */
642 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
643 /* 415 384 447 416 479 448 511 480 */
644 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
646 /* ownDmaChannels */
647 /* 31 0 63 32 */
648 {0x00000000u, 0x00000000u},
650 /* ownQdmaChannels */
651 /* 31 0 */
652 {0x00000000u},
654 /* ownTccs */
655 /* 31 0 63 32 */
656 {0x00000000u, 0x00000000u},
658 /* Resources reserved by Region 4 */
659 /* resvdPaRAMSets */
660 /* 31 0 63 32 95 64 127 96 */
661 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
662 /* 159 128 191 160 223 192 255 224 */
663 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
664 /* 287 256 319 288 351 320 383 352 */
665 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
666 /* 415 384 447 416 479 448 511 480 */
667 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
669 /* resvdDmaChannels */
670 /* 31 0 63 32 */
671 {0x00000000u, 0x00000000u},
673 /* resvdQdmaChannels */
674 /* 31 0 */
675 {0x00000000u},
677 /* resvdTccs */
678 /* 31 0 63 32 */
679 {0x00000000u, 0x00000000u},
680 },
682 {
683 /* Resources owned by Region 5 */
684 /* ownPaRAMSets */
685 /* 31 0 63 32 95 64 127 96 */
686 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
687 /* 159 128 191 160 223 192 255 224 */
688 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
689 /* 287 256 319 288 351 320 383 352 */
690 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
691 /* 415 384 447 416 479 448 511 480 */
692 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
694 /* ownDmaChannels */
695 /* 31 0 63 32 */
696 {0x00000000u, 0x00000000u},
698 /* ownQdmaChannels */
699 /* 31 0 */
700 {0x00000000u},
702 /* ownTccs */
703 /* 31 0 63 32 */
704 {0x00000000u, 0x00000000u},
706 /* Resources reserved by Region 5 */
707 /* resvdPaRAMSets */
708 /* 31 0 63 32 95 64 127 96 */
709 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
710 /* 159 128 191 160 223 192 255 224 */
711 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
712 /* 287 256 319 288 351 320 383 352 */
713 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
714 /* 415 384 447 416 479 448 511 480 */
715 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
717 /* resvdDmaChannels */
718 /* 31 0 63 32 */
719 {0x00000000u, 0x00000000u},
721 /* resvdQdmaChannels */
722 /* 31 0 */
723 {0x00000000u},
725 /* resvdTccs */
726 /* 31 0 63 32 */
727 {0x00000000u, 0x00000000u},
728 },
730 {
731 /* Resources owned by Region 6 */
732 /* ownPaRAMSets */
733 /* 31 0 63 32 95 64 127 96 */
734 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
735 /* 159 128 191 160 223 192 255 224 */
736 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
737 /* 287 256 319 288 351 320 383 352 */
738 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
739 /* 415 384 447 416 479 448 511 480 */
740 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
742 /* ownDmaChannels */
743 /* 31 0 63 32 */
744 {0x00000000u, 0x00000000u},
746 /* ownQdmaChannels */
747 /* 31 0 */
748 {0x00000000u},
750 /* ownTccs */
751 /* 31 0 63 32 */
752 {0x00000000u, 0x00000000u},
754 /* Resources reserved by Region 6 */
755 /* resvdPaRAMSets */
756 /* 31 0 63 32 95 64 127 96 */
757 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
758 /* 159 128 191 160 223 192 255 224 */
759 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
760 /* 287 256 319 288 351 320 383 352 */
761 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
762 /* 415 384 447 416 479 448 511 480 */
763 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
765 /* resvdDmaChannels */
766 /* 31 0 63 32 */
767 {0x00000000u, 0x00000000u},
769 /* resvdQdmaChannels */
770 /* 31 0 */
771 {0x00000000u},
773 /* resvdTccs */
774 /* 31 0 63 32 */
775 {0x00000000u, 0x00000000u},
776 },
778 {
779 /* Resources owned by Region 7 */
780 /* ownPaRAMSets */
781 /* 31 0 63 32 95 64 127 96 */
782 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
783 /* 159 128 191 160 223 192 255 224 */
784 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
785 /* 287 256 319 288 351 320 383 352 */
786 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
787 /* 415 384 447 416 479 448 511 480 */
788 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
790 /* ownDmaChannels */
791 /* 31 0 63 32 */
792 {0x00000000u, 0x00000000u},
794 /* ownQdmaChannels */
795 /* 31 0 */
796 {0x00000000u},
798 /* ownTccs */
799 /* 31 0 63 32 */
800 {0x00000000u, 0x00000000u},
802 /* Resources reserved by Region 7 */
803 /* resvdPaRAMSets */
804 /* 31 0 63 32 95 64 127 96 */
805 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
806 /* 159 128 191 160 223 192 255 224 */
807 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
808 /* 287 256 319 288 351 320 383 352 */
809 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
810 /* 415 384 447 416 479 448 511 480 */
811 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
813 /* resvdDmaChannels */
814 /* 31 0 63 32 */
815 {0x00000000u, 0x00000000u},
817 /* resvdQdmaChannels */
818 /* 31 0 */
819 {0x00000000u},
821 /* resvdTccs */
822 /* 31 0 63 32 */
823 {0x00000000u, 0x00000000u},
824 }
825 }
826 };
828 /* End of File */