Updated AM335x and AM437x sample config file with correct available resources
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_am437x_cfg.c
1 /*
2  * sample_am437x_cfg.c
3  *
4  * Platform specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES                     1u
45 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
47 uint16_t determineProcId(void)
48 {
49      return 0U;
50 }
52 int8_t*  getGlobalAddr(int8_t* addr)
53 {
54      return (addr); /* The address is already a global address */
55 }
57 uint16_t isGblConfigRequired(uint32_t dspNum)
58 {
59     (void) dspNum;
60         return 0U;
61 }
63 /* Semaphore handles */
64 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
66 /** Total number of DMA Channels supported by the EDMA3 Controller */
67 #define EDMA3_NUM_DMA_CHANNELS                        (64u)
68 /** Total number of QDMA Channels supported by the EDMA3 Controller */
69 #define EDMA3_NUM_QDMA_CHANNELS                       (8u)
70 /** Total number of TCCs supported by the EDMA3 Controller */
71 #define EDMA3_NUM_TCC                                 (64u)
72 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
73 #define EDMA3_NUM_PARAMSET                            (256u)
74 /** Total number of Event Queues in the EDMA3 Controller */
75 #define EDMA3_NUM_EVTQUE                              (3u)
76 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
77 #define EDMA3_NUM_TC                                  (3u)
78 /** Number of Regions on this EDMA3 controller */
79 #define EDMA3_NUM_REGION                              (8u)
83 /**
84  * \brief Channel mapping existence
85  * A value of 0 (No channel mapping) implies that there is fixed association
86  * for a channel number to a parameter entry number or, in other words,
87  * PaRAM entry n corresponds to channel n.
88  */
89 #define CHANNEL_MAPPING_EXISTENCE               (1u)
90 /** Existence of memory protection feature */
91 #define MEM_PROTECTION_EXISTENCE                (1u)
93 /** Global Register Region of CC Registers */
94 #define CC_BASE_ADDRESS                         (0x49000000u)
95 /** Transfer Controller 0 Registers */
96 #define TC0_BASE_ADDRESS                        (0x49800000u)
97 /** Transfer Controller 1 Registers */
98 #define TC1_BASE_ADDRESS                        (0x49900000u)
99 /** Transfer Controller 2 Registers */
100 #define TC2_BASE_ADDRESS                        (0x49A00000u)
101 /** Transfer Controller 3 Registers */
102 #define TC3_BASE_ADDRESS                        NULL
103 /** Transfer Controller 4 Registers */
104 #define TC4_BASE_ADDRESS                        NULL
105 /** Transfer Controller 5 Registers */
106 #define TC5_BASE_ADDRESS                        NULL
107 /** Transfer Controller 6 Registers */
108 #define TC6_BASE_ADDRESS                        NULL
109 /** Transfer Controller 7 Registers */
110 #define TC7_BASE_ADDRESS                        NULL
112 /** Interrupt no. for Transfer Completion */
113 #define EDMA3_CC_XFER_COMPLETION_INT                  (44u)
114 /** Interrupt no. for CC Error */
115 #define EDMA3_CC_ERROR_INT                            (46u)
116 /** Interrupt no. for TC 0 Error */
117 #define EDMA3_TC0_ERROR_INT                           (144u)
118 /** Interrupt no. for TC 1 Error */
119 #define EDMA3_TC1_ERROR_INT                           (145u)
120 /** Interrupt no. for TC 2 Error */
121 #define EDMA3_TC2_ERROR_INT                           (146u)
122 /** Interrupt no. for TC 3 Error */
123 #define EDMA3_TC3_ERROR_INT                           (0u)
124 /** Interrupt no. for TC 4 Error */
125 #define EDMA3_TC4_ERROR_INT                           (0u)
126 /** Interrupt no. for TC 5 Error */
127 #define EDMA3_TC5_ERROR_INT                           (0u)
128 /** Interrupt no. for TC 6 Error */
129 #define EDMA3_TC6_ERROR_INT                           (0u)
130 /** Interrupt no. for TC 7 Error */
131 #define EDMA3_TC7_ERROR_INT                           (0u)
133 /**
134  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
135  * ECM events (SoC specific). These ECM events come
136  * under ECM block XXX (handling those specific ECM events). Normally, block
137  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
138  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
139  * is mapped to a specific HWI_INT YYY in the tcf file.
140  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
141  * to transfer completion interrupt.
142  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
143  * to CC error interrupts.
144  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
145  * to TC error interrupts.
146  */
147 /* EDMA 0 */
149 #define EDMA3_HWI_INT_XFER_COMP                           (7U)
150 #define EDMA3_HWI_INT_CC_ERR                              (7U)
151 #define EDMA3_HWI_INT_TC0_ERR                             (10U)
152 #define EDMA3_HWI_INT_TC1_ERR                             (10U)
153 #define EDMA3_HWI_INT_TC2_ERR                             (10U)
155 /**
156  * \brief Mapping of DMA channels 0-31 to Hardware Events from
157  * various peripherals, which use EDMA for data transfer.
158  * All channels need not be mapped, some can be free also.
159  * 1: Mapped
160  * 0: Not mapped
161  *
162  * This mapping will be used to allocate DMA channels when user passes
163  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
164  * copy). The same mapping is used to allocate the TCC when user passes
165  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
166  *
167  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
168  */
169                                                                                                 /* 31     0 */
170 #define DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFF0Fu)
173 /**
174  * \brief Mapping of DMA channels 32-63 to Hardware Events from
175  * various peripherals, which use EDMA for data transfer.
176  * All channels need not be mapped, some can be free also.
177  * 1: Mapped
178  * 0: Not mapped
179  *
180  * This mapping will be used to allocate DMA channels when user passes
181  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
182  * copy). The same mapping is used to allocate the TCC when user passes
183  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
184  *
185  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
186  */
187 /* DMA channels 32-63 DOES NOT exist in DA830. */
188 #define DMA_CHANNEL_TO_EVENT_MAPPING_1          (0xFFFFFFC0u)
190 /* Variable which will be used internally for referring number of Event Queues*/
191 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {EDMA3_NUM_EVTQUE};
193 /* Variable which will be used internally for referring number of TCs.        */
194 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {EDMA3_NUM_TC};
196 /**
197  * Variable which will be used internally for referring transfer completion
198  * interrupt.
199  */
200 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
201                                                         {
202                                                         EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u, 0u,
203                                                         0u, 0u, 0u, 0u,
204                                                         },
205                         };
207 /**
208  * Variable which will be used internally for referring channel controller's
209  * error interrupt.
210  */
211 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
213 /**
214  * Variable which will be used internally for referring transfer controllers'
215  * error interrupts.
216  */
217 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =    {
218                                 {
219                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
220                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
221                                 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
222                                 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
223                                 }
224                             };
226 /**
227  * Variables which will be used internally for referring the hardware interrupt
228  * for various EDMA3 interrupts.
229  */
230 uint32_t hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
231 uint32_t hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
232 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
234     /* EDMA3 INSTANCE# 0 */
235     {
236         EDMA3_HWI_INT_TC0_ERR,
237         EDMA3_HWI_INT_TC1_ERR,
238         EDMA3_HWI_INT_TC2_ERR,
239         0,
240         0,
241         0,
242         0,
243         0
244     }
245 };
248 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
250     {
251     /** Total number of DMA Channels supported by the EDMA3 Controller */
252     EDMA3_NUM_DMA_CHANNELS,
253     /** Total number of QDMA Channels supported by the EDMA3 Controller */
254     EDMA3_NUM_QDMA_CHANNELS,
255     /** Total number of TCCs supported by the EDMA3 Controller */
256     EDMA3_NUM_TCC,
257     /** Total number of PaRAM Sets supported by the EDMA3 Controller */
258     EDMA3_NUM_PARAMSET,
259     /** Total number of Event Queues in the EDMA3 Controller */
260     EDMA3_NUM_EVTQUE,
261     /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
262     EDMA3_NUM_TC,
263     /** Number of Regions on this EDMA3 controller */
264     EDMA3_NUM_REGION,
266     /**
267      * \brief Channel mapping existence
268      * A value of 0 (No channel mapping) implies that there is fixed association
269      * for a channel number to a parameter entry number or, in other words,
270      * PaRAM entry n corresponds to channel n.
271      */
272     CHANNEL_MAPPING_EXISTENCE,
274     /** Existence of memory protection feature */
275     MEM_PROTECTION_EXISTENCE,
277     /** Global Register Region of CC Registers */
278     (void *)(CC_BASE_ADDRESS),
279     /** Transfer Controller (TC) Registers */
280         {
281         (void *)(TC0_BASE_ADDRESS),
282         (void *)(TC1_BASE_ADDRESS),
283         (void *)(TC2_BASE_ADDRESS),
284         (void *)(TC3_BASE_ADDRESS),
285         (void *)(TC4_BASE_ADDRESS),
286         (void *)(TC5_BASE_ADDRESS),
287         (void *)(TC6_BASE_ADDRESS),
288         (void *)(TC7_BASE_ADDRESS)
289         },
290     /** Interrupt no. for Transfer Completion */
291     EDMA3_CC_XFER_COMPLETION_INT,
292     /** Interrupt no. for CC Error */
293     EDMA3_CC_ERROR_INT,
294     /** Interrupt no. for TCs Error */
295         {
296         EDMA3_TC0_ERROR_INT,
297         EDMA3_TC1_ERROR_INT,
298         EDMA3_TC2_ERROR_INT,
299         EDMA3_TC3_ERROR_INT,
300         EDMA3_TC4_ERROR_INT,
301         EDMA3_TC5_ERROR_INT,
302         EDMA3_TC6_ERROR_INT,
303         EDMA3_TC7_ERROR_INT
304         },
306    /**
307      * \brief EDMA3 TC priority setting
308      *
309      * User can program the priority of the Event Queues
310      * at a system-wide level.  This means that the user can set the
311      * priority of an IO initiated by either of the TCs (Transfer Controllers)
312      * relative to IO initiated by the other bus masters on the
313      * device (ARM, DSP, USB, etc)
314      */
315         {
316         0u,
317         1u,
318         2u,
319         0u,
320         0u,
321         0u,
322         0u,
323         0u
324         },
325     /**
326      * \brief To Configure the Threshold level of number of events
327      * that can be queued up in the Event queues. EDMA3CC error register
328      * (CCERR) will indicate whether or not at any instant of time the
329      * number of events queued up in any of the event queues exceeds
330      * or equals the threshold/watermark value that is set
331      * in the queue watermark threshold register (QWMTHRA).
332      */
333         {
334         16u,
335         16u,
336         16u,
337         0u,
338         0u,
339         0u,
340         0u,
341         0u
342         },
344     /**
345      * \brief To Configure the Default Burst Size (DBS) of TCs.
346      * An optimally-sized command is defined by the transfer controller
347      * default burst size (DBS). Different TCs can have different
348      * DBS values. It is defined in Bytes.
349      */
350         {
351         16u,
352         16u,
353         16u,
354         0u,
355         0u,
356         0u,
357         0u,
358         0u
359         },
361     /**
362      * \brief Mapping from each DMA channel to a Parameter RAM set,
363      * if it exists, otherwise of no use.
364      */
365         {
366         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
367         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
368         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
369         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
370         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
371         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
372         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
373         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
374         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
375         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
376         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
377         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
378         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
379         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
380         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
381         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
382         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
383         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
384         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
385         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
386         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
387         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
388         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
389         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
390         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
391         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
392         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
393         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
394         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
395         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
396         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
397         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP
398         },
400      /**
401       * \brief Mapping from each DMA channel to a TCC. This specific
402       * TCC code will be returned when the transfer is completed
403       * on the mapped channel.
404       */
405         {
406         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
407         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
408                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
409                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
410                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
411                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
412                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
413                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
414         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
415                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
416                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
417                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
418                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
419                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
420                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
421                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP
422         },
424     /**
425      * \brief Mapping of DMA channels to Hardware Events from
426      * various peripherals, which use EDMA for data transfer.
427      * All channels need not be mapped, some can be free also.
428      */
429         {
430         DMA_CHANNEL_TO_EVENT_MAPPING_0,
431         DMA_CHANNEL_TO_EVENT_MAPPING_1
432         }
433     }
434 };
437 /* Default RM Instance Initialization Configuration */
438 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM_REGION] =
440         {
441           {
442             /* Resources owned by Region 0 */
443             /* ownPaRAMSets */
444             /* 31     0     63    32     95    64     127   96 */
445             {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
446             /* 159  128     191  160     223  192     255  224 */
447             0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
448             /* 287  256     319  288     351  320     383  352 */
449              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
450             /* 415  384     447  416     479  448     511  480 */
451              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
453             /* ownDmaChannels */
454             /* 31     0     63    32 */
455             {0xFFFFFFFFu, 0xFFFFFFFFu},
457             /* ownQdmaChannels */
458             /* 31     0 */
459             {0x000000FFU},
461             /* ownTccs */
462             /* 31     0     63    32 */
463             {0xFFFFFFFFU, 0xFFFFFFFFU},
465             /* Resources reserved by Region 0 */
466             /* resvdPaRAMSets */
467             /* 31     0     63    32     95    64     127   96 */
468             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
469             /* 159  128     191  160     223  192     255  224 */
470              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
471             /* 287  256     319  288     351  320     383  352 */
472              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
473             /* 415  384     447  416     479  448     511  480 */
474              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
476             /* resvdDmaChannels */
477             /* 31                                         0  63                                                  32 */
478             {0x00000000u, 0x00000000u},
480             /* resvdQdmaChannels */
481             /* 31     0 */
482             {0x00000000u},
484             /* resvdTccs */
485             /* 31                                         0  63                                                  32 */
486             {0x00000000u, 0x00000000u},
487           },
489           {
490             /* Resources owned by Region 1 */
491              /* ownPaRAMSets */
492             /* 31     0     63    32     95    64     127   96 */
493             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
494             /* 159  128     191  160     223  192     255  224 */
495              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
496             /* 287  256     319  288     351  320     383  352 */
497              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
498             /* 415  384     447  416     479  448     511  480 */
499              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
501             /* ownDmaChannels */
502             /* 31     0     63    32 */
503             {0x00000000u, 0x00000000u},
505             /* ownQdmaChannels */
506             /* 31     0 */
507             {0x00000000u},
509             /* ownTccs */
510             /* 31     0     63    32 */
511             {0x00000000u, 0x00000000u},
513             /* Resources reserved by Region 1 */
514             /* resvdPaRAMSets */
515             /* 31     0     63    32     95    64     127   96 */
516             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
517             /* 159  128     191  160     223  192     255  224 */
518              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
519             /* 287  256     319  288     351  320     383  352 */
520              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
521             /* 415  384     447  416     479  448     511  480 */
522              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
524             /* resvdDmaChannels */
525             /* 31     0     63    32 */
526             {0x00000000u, 0x00000000u},
528             /* resvdQdmaChannels */
529             /* 31     0 */
530             {0x00000000u},
532             /* resvdTccs */
533             /* 31     0     63    32 */
534             {0x00000000u, 0x00000000u},
535           },
537           {
538             /* Resources owned by Region 2 */
539              /* ownPaRAMSets */
540             /* 31     0     63    32     95    64     127   96 */
541             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
542             /* 159  128     191  160     223  192     255  224 */
543              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
544             /* 287  256     319  288     351  320     383  352 */
545              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
546             /* 415  384     447  416     479  448     511  480 */
547              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
549             /* ownDmaChannels */
550             /* 31     0     63    32 */
551             {0x00000000u, 0x00000000u},
553             /* ownQdmaChannels */
554             /* 31     0 */
555             {0x00000000u},
557             /* ownTccs */
558             /* 31     0     63    32 */
559             {0x00000000u, 0x00000000u},
561             /* Resources reserved by Region 2 */
562             /* resvdPaRAMSets */
563             /* 31     0     63    32     95    64     127   96 */
564             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
565             /* 159  128     191  160     223  192     255  224 */
566              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
567             /* 287  256     319  288     351  320     383  352 */
568              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
569             /* 415  384     447  416     479  448     511  480 */
570              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
572             /* resvdDmaChannels */
573             /* 31     0     63    32 */
574             {0x00000000u, 0x00000000u},
576             /* resvdQdmaChannels */
577             /* 31     0 */
578             {0x00000000u},
580             /* resvdTccs */
581             /* 31     0     63    32 */
582             {0x00000000u, 0x00000000u},
583           },
585           {
586             /* Resources owned by Region 3 */
587              /* ownPaRAMSets */
588             /* 31     0     63    32     95    64     127   96 */
589             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
590             /* 159  128     191  160     223  192     255  224 */
591              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
592             /* 287  256     319  288     351  320     383  352 */
593              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
594             /* 415  384     447  416     479  448     511  480 */
595              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
597             /* ownDmaChannels */
598             /* 31     0     63    32 */
599             {0x00000000u, 0x00000000u},
601             /* ownQdmaChannels */
602             /* 31     0 */
603             {0x00000000u},
605             /* ownTccs */
606             /* 31     0     63    32 */
607             {0x00000000u, 0x00000000u},
609             /* Resources reserved by Region 3 */
610             /* resvdPaRAMSets */
611             /* 31     0     63    32     95    64     127   96 */
612             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
613             /* 159  128     191  160     223  192     255  224 */
614              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
615             /* 287  256     319  288     351  320     383  352 */
616              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
617             /* 415  384     447  416     479  448     511  480 */
618              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
620             /* resvdDmaChannels */
621             /* 31     0     63    32 */
622             {0x00000000u, 0x00000000u},
624             /* resvdQdmaChannels */
625             /* 31     0 */
626             {0x00000000u},
628             /* resvdTccs */
629             /* 31     0     63    32 */
630             {0x00000000u, 0x00000000u},
631           },
633           {
634             /* Resources owned by Region 4 */
635              /* ownPaRAMSets */
636             /* 31     0     63    32     95    64     127   96 */
637             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
638             /* 159  128     191  160     223  192     255  224 */
639              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
640             /* 287  256     319  288     351  320     383  352 */
641              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
642             /* 415  384     447  416     479  448     511  480 */
643              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
645             /* ownDmaChannels */
646             /* 31     0     63    32 */
647             {0x00000000u, 0x00000000u},
649             /* ownQdmaChannels */
650             /* 31     0 */
651             {0x00000000u},
653             /* ownTccs */
654             /* 31     0     63    32 */
655             {0x00000000u, 0x00000000u},
657             /* Resources reserved by Region 4 */
658             /* resvdPaRAMSets */
659             /* 31     0     63    32     95    64     127   96 */
660             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
661             /* 159  128     191  160     223  192     255  224 */
662              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
663             /* 287  256     319  288     351  320     383  352 */
664              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
665             /* 415  384     447  416     479  448     511  480 */
666              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
668             /* resvdDmaChannels */
669             /* 31     0     63    32 */
670             {0x00000000u, 0x00000000u},
672             /* resvdQdmaChannels */
673             /* 31     0 */
674             {0x00000000u},
676             /* resvdTccs */
677             /* 31     0     63    32 */
678             {0x00000000u, 0x00000000u},
679           },
681           {
682             /* Resources owned by Region 5 */
683              /* ownPaRAMSets */
684             /* 31     0     63    32     95    64     127   96 */
685             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
686             /* 159  128     191  160     223  192     255  224 */
687              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
688             /* 287  256     319  288     351  320     383  352 */
689              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
690             /* 415  384     447  416     479  448     511  480 */
691              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
693             /* ownDmaChannels */
694             /* 31     0     63    32 */
695             {0x00000000u, 0x00000000u},
697             /* ownQdmaChannels */
698             /* 31     0 */
699             {0x00000000u},
701             /* ownTccs */
702             /* 31     0     63    32 */
703             {0x00000000u, 0x00000000u},
705             /* Resources reserved by Region 5 */
706             /* resvdPaRAMSets */
707             /* 31     0     63    32     95    64     127   96 */
708             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
709             /* 159  128     191  160     223  192     255  224 */
710              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
711             /* 287  256     319  288     351  320     383  352 */
712              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
713             /* 415  384     447  416     479  448     511  480 */
714              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
716             /* resvdDmaChannels */
717             /* 31     0     63    32 */
718             {0x00000000u, 0x00000000u},
720             /* resvdQdmaChannels */
721             /* 31     0 */
722             {0x00000000u},
724             /* resvdTccs */
725             /* 31     0     63    32 */
726             {0x00000000u, 0x00000000u},
727           },
729           {
730             /* Resources owned by Region 6 */
731              /* ownPaRAMSets */
732             /* 31     0     63    32     95    64     127   96 */
733             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
734             /* 159  128     191  160     223  192     255  224 */
735              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
736             /* 287  256     319  288     351  320     383  352 */
737              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
738             /* 415  384     447  416     479  448     511  480 */
739              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
741             /* ownDmaChannels */
742             /* 31     0     63    32 */
743             {0x00000000u, 0x00000000u},
745             /* ownQdmaChannels */
746             /* 31     0 */
747             {0x00000000u},
749             /* ownTccs */
750             /* 31     0     63    32 */
751             {0x00000000u, 0x00000000u},
753             /* Resources reserved by Region 6 */
754             /* resvdPaRAMSets */
755             /* 31     0     63    32     95    64     127   96 */
756             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
757             /* 159  128     191  160     223  192     255  224 */
758              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
759             /* 287  256     319  288     351  320     383  352 */
760              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
761             /* 415  384     447  416     479  448     511  480 */
762              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
764             /* resvdDmaChannels */
765             /* 31     0     63    32 */
766             {0x00000000u, 0x00000000u},
768             /* resvdQdmaChannels */
769             /* 31     0 */
770             {0x00000000u},
772             /* resvdTccs */
773             /* 31     0     63    32 */
774             {0x00000000u, 0x00000000u},
775           },
777           {
778             /* Resources owned by Region 7 */
779              /* ownPaRAMSets */
780             /* 31     0     63    32     95    64     127   96 */
781             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
782             /* 159  128     191  160     223  192     255  224 */
783              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
784             /* 287  256     319  288     351  320     383  352 */
785              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
786             /* 415  384     447  416     479  448     511  480 */
787              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
789             /* ownDmaChannels */
790             /* 31     0     63    32 */
791             {0x00000000u, 0x00000000u},
793             /* ownQdmaChannels */
794             /* 31     0 */
795             {0x00000000u},
797             /* ownTccs */
798             /* 31     0     63    32 */
799             {0x00000000u, 0x00000000u},
801             /* Resources reserved by Region 7 */
802             /* resvdPaRAMSets */
803             /* 31     0     63    32     95    64     127   96 */
804             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
805             /* 159  128     191  160     223  192     255  224 */
806              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
807             /* 287  256     319  288     351  320     383  352 */
808              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
809             /* 415  384     447  416     479  448     511  480 */
810              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
812             /* resvdDmaChannels */
813             /* 31     0     63    32 */
814             {0x00000000u, 0x00000000u},
816             /* resvdQdmaChannels */
817             /* 31     0 */
818             {0x00000000u},
820             /* resvdTccs */
821             /* 31     0     63    32 */
822             {0x00000000u, 0x00000000u},
823           }
824         }
825 };
827 /* End of File */