fixed build warning
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_c6a811x_arm_int_reg.c
1 /*
2  * sample_ti814x_int_reg.c
3  *
4  * Platform specific interrupt registration and un-registration routines.
5  *
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  *
9  *  Redistribution and use in source and binary forms, with or without
10  *  modification, are permitted provided that the following conditions
11  *  are met:
12  *
13  *    Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  *
16  *    Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the
19  *    distribution.
20  *
21  *    Neither the name of Texas Instruments Incorporated nor the names of
22  *    its contributors may be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/hal/Hwi.h>
41 #include <xdc/runtime/Error.h>
42 #include <xdc/runtime/System.h>
44 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
46 /**
47   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
48   * (Not all TC error ISRs need to be registered, register only for the
49   * available Transfer Controllers).
50   */
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
52                                                 {
53                                                 &lisrEdma3TC0ErrHandler0,
54                                                 &lisrEdma3TC1ErrHandler0,
55                                                 &lisrEdma3TC2ErrHandler0,
56                                                 &lisrEdma3TC3ErrHandler0,
57                                                 &lisrEdma3TC4ErrHandler0,
58                                                 &lisrEdma3TC5ErrHandler0,
59                                                 &lisrEdma3TC6ErrHandler0,
60                                                 &lisrEdma3TC7ErrHandler0,
61                                                 };
63 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
64 extern unsigned int ccErrorInt[];
65 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
66 extern unsigned int numEdma3Tc[];
68 /**
69  * Variables which will be used internally for referring the hardware interrupt
70  * for various EDMA3 interrupts.
71  */
72 extern unsigned int hwIntXferComp[];
73 extern unsigned int hwIntCcErr[];
74 extern unsigned int hwIntTcErr[];
76 extern unsigned int dsp_num;
77 /* This variable has to be used as an extern */
78 unsigned int gpp_num = 0;
80 Hwi_Handle hwiCCXferCompInt;
81 Hwi_Handle hwiCCErrInt;
82 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
84 /* External Instance Specific Configuration Structure */
85 extern EDMA3_DRV_GblXbarToChanConfigParams 
86                                                                 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
88 typedef struct  {
89     volatile Uint32 DSP_INTMUX[21];
90     volatile Uint32 DUCATI_INTMUX[15];
91     volatile Uint32 TPCC_EVTMUX[16];
92     volatile Uint32 TIMER_EVTCAPT;
93     volatile Uint32 GPIO_MUX;
94         volatile Uint32 ADC_EVT_CAPT;
95         volatile Uint32 ECAP_EVT_CAPT;
96 } CSL_IntmuxRegs;
98 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
101 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
111 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
112 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
113 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
116 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
117 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
118 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
121 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)
122 #define EDMA3_NUM_TCC                     (64u)
124 /*
125  * Forward decleration
126  */
127 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
128                  unsigned int *chanNum,
129                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
130 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
131                                   unsigned int chanNum);
133 void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
135 /**  To Register the ISRs with the underlying OS, if required. */
136 void registerEdma3Interrupts (unsigned int edma3Id)
137     {
138     static UInt32 cookie = 0;
139 #ifdef BUILD_C6A811X_A8
140     unsigned int numTc = 0;
141 #endif
142     Hwi_Params hwiParams; 
143     Error_Block      eb;
145     /* Initialize the Error Block                                             */
146     Error_init(&eb);
147         
148     /* Disabling the global interrupts */
149     cookie = Hwi_disable();
151     /* Initialize the HWI parameters with user specified values */
152     Hwi_Params_init(&hwiParams);
153     
154     /* argument for the ISR */
155     hwiParams.arg = edma3Id;
156         /* set the priority ID     */
157         //hwiParams.priority = hwIntXferComp[edma3Id];
158     
159     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
160                             ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
161                             (const Hwi_Params *) (&hwiParams),
162                             &eb);
163     if (TRUE == Error_check(&eb))
164     {
165         System_printf("HWI Create Failed\n",Error_getCode(&eb));
166     }
167 #ifdef BUILD_C6A811X_A8
168     /* Initialize the HWI parameters with user specified values */
169     Hwi_Params_init(&hwiParams);
170     /* argument for the ISR */
171     hwiParams.arg = edma3Id;
172         /* set the priority ID     */
173         hwiParams.priority = hwIntCcErr[edma3Id];
174         
175         hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
176                 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
177                 (const Hwi_Params *) (&hwiParams),
178                 &eb);
180     if (TRUE == Error_check(&eb))
181     {
182         System_printf("HWI Create Failed\n",Error_getCode(&eb));
183     }
185     while (numTc < numEdma3Tc[edma3Id])
186             {
187         /* Initialize the HWI parameters with user specified values */
188         Hwi_Params_init(&hwiParams);
189         /* argument for the ISR */
190         hwiParams.arg = edma3Id;
191         /* set the priority ID     */
192         hwiParams.priority = hwIntTcErr[edma3Id];
193         
194         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
195                     ((Hwi_FuncPtr)ptrEdma3TcIsrHandler[numTc]),
196                     (const Hwi_Params *) (&hwiParams),
197                     &eb);
198         if (TRUE == Error_check(&eb))
199         {
200             System_printf("HWI Create Failed\n",Error_getCode(&eb));
201         }
202         numTc++;
203         }
204    /**
205     * Enabling the HWI_ID.
206     * EDMA3 interrupts (transfer completion, CC error etc.)
207     * correspond to different ECM events (SoC specific). These ECM events come
208     * under ECM block XXX (handling those specific ECM events). Normally, block
209     * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
210     * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
211     * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
212     * mapped HWI_INT YYY, one should use the corresponding bitmask in the
213     * API C64_enableIER(), in which the YYY bit is SET.
214     */
215     Hwi_enableInterrupt(ccErrorInt[edma3Id]);
216 #if 0
217     Hwi_enableInterrupt(13);
218 #endif
219     Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
220     numTc = 0;
221     while (numTc < numEdma3Tc[edma3Id])
222             {
223         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
224         numTc++;
225         }
226 #endif
227     /* Restore interrupts */
228     Hwi_restore(cookie);
229     }
231 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
232 void unregisterEdma3Interrupts (unsigned int edma3Id)
233     {
234         static UInt32 cookie = 0;
235     unsigned int numTc = 0;
237     /* Disabling the global interrupts */
238     cookie = Hwi_disable();
240     Hwi_delete(&hwiCCXferCompInt);
241     Hwi_delete(&hwiCCErrInt);
242     while (numTc < numEdma3Tc[edma3Id])
243             {
244         Hwi_delete(&hwiTCErrInt[numTc]);
245         numTc++;
246         }
247     /* Restore interrupts */
248     Hwi_restore(cookie);
249     }
251 /**
252  * \brief   sampleMapXbarEvtToChan
253  *
254  * This function reads from the sample configuration structure which specifies 
255  * cross bar events mapped to DMA channel.
256  *
257  * \return  EDMA3_DRV_SOK if success, else error code
258  */
259 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
260                  unsigned int *chanNum,
261                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
262         {
263     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
264     unsigned int xbarEvtNum = 0;
265     int          edmaChanNum = 0;
267         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
268                 (chanNum != NULL) &&
269                 (edmaGblXbarConfig != NULL))
270                 {
271                 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
272                 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
273                 if (edmaChanNum != -1)
274                         {
275                         *chanNum = edmaChanNum;
276                         edma3Result = EDMA3_DRV_SOK;
277                         }
278                 }
279         return (edma3Result);
280         }
283 /**
284  * \brief   sampleConfigScr
285  *
286  * This function configures control config registers for the cross bar events 
287  * mapped to the EDMA channel.
288  *
289  * \return  EDMA3_DRV_SOK if success, else error code
290  */
291 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
292                                   unsigned int chanNum)
293         {
294     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
295     unsigned int scrChanOffset = 0;
296     unsigned int scrRegOffset  = 0;
297     unsigned int xBarEvtNum    = 0;
298     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
301         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
302                 (chanNum < EDMA3_NUM_TCC))
303                 {
304                 scrRegOffset = chanNum / 4;
305                 scrChanOffset = chanNum - (scrRegOffset * 4);
306                 xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
307                 
308                 switch(scrChanOffset)
309                         {
310                         case 0:
311                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
312                                         (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
313                                 break;
314                         case 1:
315                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
316                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
317                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
318                                 break;
319                         case 2:
320                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
321                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
322                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
323                                 break;
324                         case 3:
325                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
326                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
327                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
328                                 break;
329                         default:
330                                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
331                                 break;
332                         }
333                 }
334         else
335                 {
336                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
337                 }
338         return edma3Result;
339         }
341 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
342                                    unsigned int edma3Id)
343     {
344     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
345     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
346                                 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
347     if (hEdma != NULL)
348         {
349         retVal = EDMA3_DRV_initXbarEventMap(hEdma, 
350                                             sampleXbarToChanConfig,
351                                             (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan,
352                                             (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);
353         }
354     
355     return retVal;
356     }
358 void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
359     {
360 #ifdef EDMA3_DRV_DEBUG
361     /*  Added to fix warning */
362     printf("memory Protection error");
363 #endif
364     }