[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_c6a811x_cfg.c
1 /*
2 * sample_ti814x_cfg.c
3 *
4 * SoC specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54 #ifdef BUILD_C6A811X_A8
55 return 0;
56 #elif defined BUILD_C6A811X_DSP
57 return 1;
58 #elif defined BUILD_C6A811X_M3VPSS
59 return 5;
60 #elif defined BUILD_C6A811X_M3VIDEO
61 return 4;
62 #else
63 return 1;
64 #endif
65 }
67 signed char* getGlobalAddr(signed char* addr)
68 {
69 return (addr); /* The address is already a global address */
70 }
71 unsigned short isGblConfigRequired(unsigned int dspNum)
72 {
73 (void) dspNum;
74 #ifdef BUILD_C6A811X_DSP
75 return 1;
76 #else
77 return 0;
78 #endif
79 }
81 /* Semaphore handles */
82 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
84 /** Number of PaRAM Sets available */
85 #define EDMA3_NUM_PARAMSET (512u)
87 /** Number of TCCS available */
88 #define EDMA3_NUM_TCC (64u)
90 /** Number of DMA Channels available */
91 #define EDMA3_NUM_DMA_CHANNELS (64u)
93 /** Number of QDMA Channels available */
94 #define EDMA3_NUM_QDMA_CHANNELS (8u)
96 /** Number of Event Queues available */
97 #define EDMA3_NUM_EVTQUE (4u)
99 /** Number of Transfer Controllers available */
100 #define EDMA3_NUM_TC (4u)
102 /** Number of Regions */
103 #define EDMA3_NUM_REGIONS (6u)
106 /** Interrupt no. for Transfer Completion */
107 #define EDMA3_CC_XFER_COMPLETION_INT_A8 (12u)
108 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (20u)
109 #define EDMA3_CC_XFER_COMPLETION_INT_M3VPSS (63u)
110 #define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO (62u)
112 #ifdef BUILD_C6A811X_A8
113 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A8
114 #elif defined BUILD_C6A811X_DSP
115 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP
116 #elif defined BUILD_C6A811X_M3VIDEO
117 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO
118 #elif defined BUILD_C6A811X_M3VPSS
119 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
120 #else
121 #define EDMA3_CC_XFER_COMPLETION_INT (0u)
122 #endif
124 /** Interrupt no. for CC Error */
125 #define EDMA3_CC_ERROR_INT_A8 (14u)
126 #define EDMA3_CC_ERROR_INT_DSP (21u)
128 #ifdef BUILD_C6A811X_A8
129 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A8
130 #elif defined BUILD_C6A811X_DSP
131 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP
132 #else
133 #define EDMA3_CC_ERROR_INT (0u)
134 #endif
136 /** Interrupt no. for TCs Error */
137 #define EDMA3_TC0_ERROR_INT_DSP (22u)
138 #define EDMA3_TC1_ERROR_INT_DSP (27u)
139 #define EDMA3_TC2_ERROR_INT_DSP (28u)
140 #define EDMA3_TC3_ERROR_INT_DSP (29u)
141 #define EDMA3_TC0_ERROR_INT_A8 (112u)
142 #define EDMA3_TC1_ERROR_INT_A8 (113u)
143 #define EDMA3_TC2_ERROR_INT_A8 (114u)
144 #define EDMA3_TC3_ERROR_INT_A8 (115u)
146 #ifdef BUILD_C6A811X_A8
147 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A8
148 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A8
149 #define EDMA3_TC2_ERROR_INT EDMA3_TC2_ERROR_INT_A8
150 #define EDMA3_TC3_ERROR_INT EDMA3_TC3_ERROR_INT_A8
151 #elif defined BUILD_C6A811X_DSP
152 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP
153 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP
154 #define EDMA3_TC2_ERROR_INT EDMA3_TC2_ERROR_INT_DSP
155 #define EDMA3_TC3_ERROR_INT EDMA3_TC3_ERROR_INT_DSP
156 #else
157 #define EDMA3_TC0_ERROR_INT (0u)
158 #define EDMA3_TC1_ERROR_INT (0u)
159 #define EDMA3_TC2_ERROR_INT (0u)
160 #define EDMA3_TC3_ERROR_INT (0u)
161 #endif
163 #define EDMA3_TC4_ERROR_INT (0u)
164 #define EDMA3_TC5_ERROR_INT (0u)
165 #define EDMA3_TC6_ERROR_INT (0u)
166 #define EDMA3_TC7_ERROR_INT (0u)
168 /**
169 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
170 * ECM events (SoC specific). These ECM events come
171 * under ECM block XXX (handling those specific ECM events). Normally, block
172 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
173 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
174 * is mapped to a specific HWI_INT YYY in the tcf file.
175 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
176 * to transfer completion interrupt.
177 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
178 * to CC error interrupts.
179 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
180 * to TC error interrupts.
181 */
182 /* EDMA 0 */
184 #define EDMA3_HWI_INT_XFER_COMP (7u)
185 #define EDMA3_HWI_INT_CC_ERR (7u)
186 #define EDMA3_HWI_INT_TC0_ERR (10u)
187 #define EDMA3_HWI_INT_TC1_ERR (10u)
188 #define EDMA3_HWI_INT_TC2_ERR (10u)
189 #define EDMA3_HWI_INT_TC3_ERR (10u)
192 /**
193 * \brief Mapping of DMA channels 0-31 to Hardware Events from
194 * various peripherals, which use EDMA for data transfer.
195 * All channels need not be mapped, some can be free also.
196 * 1: Mapped
197 * 0: Not mapped
198 *
199 * This mapping will be used to allocate DMA channels when user passes
200 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
201 * copy). The same mapping is used to allocate the TCC when user passes
202 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
203 *
204 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
205 */
206 /* 31 0 */
207 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFCFF3F0Cu) /* TBD */
210 /**
211 * \brief Mapping of DMA channels 32-63 to Hardware Events from
212 * various peripherals, which use EDMA for data transfer.
213 * All channels need not be mapped, some can be free also.
214 * 1: Mapped
215 * 0: Not mapped
216 *
217 * This mapping will be used to allocate DMA channels when user passes
218 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
219 * copy). The same mapping is used to allocate the TCC when user passes
220 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
221 *
222 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
223 */
224 /* DMA channels 32-63 DOES NOT exist in omapl138. */
225 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF003C00u) /* TBD */
228 /* Variable which will be used internally for referring number of Event Queues*/
229 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
230 EDMA3_NUM_EVTQUE,
231 };
233 /* Variable which will be used internally for referring number of TCs. */
234 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {
235 EDMA3_NUM_TC,
236 };
238 /**
239 * Variable which will be used internally for referring transfer completion
240 * interrupt.
241 */
242 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
243 {
244 {
245 EDMA3_CC_XFER_COMPLETION_INT_A8, EDMA3_CC_XFER_COMPLETION_INT_DSP, 0u, 0u,
246 EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO, EDMA3_CC_XFER_COMPLETION_INT_M3VPSS, 0u, 0u,
247 },
248 };
250 /**
251 * Variable which will be used internally for referring channel controller's
252 * error interrupt.
253 */
254 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
255 EDMA3_CC_ERROR_INT,
256 };
258 /**
259 * Variable which will be used internally for referring transfer controllers'
260 * error interrupts.
261 */
262 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
263 {
264 {
265 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
266 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
267 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
268 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
269 }
270 };
272 /**
273 * Variables which will be used internally for referring the hardware interrupt
274 * for various EDMA3 interrupts.
275 */
276 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
277 EDMA3_HWI_INT_XFER_COMP
278 };
280 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
281 EDMA3_HWI_INT_CC_ERR
282 };
284 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
285 {
286 EDMA3_HWI_INT_TC0_ERR,
287 EDMA3_HWI_INT_TC1_ERR,
288 EDMA3_HWI_INT_TC2_ERR,
289 EDMA3_HWI_INT_TC3_ERR
290 }
291 };
293 /**
294 * \brief Base address as seen from the different cores may be different
295 * And is defined based on the core
296 */
297 #ifdef BUILD_C6A811X_DSP
298 #define EDMA3_CC_BASE_ADDR ((void *)(0x09000000))
299 #define EDMA3_TC0_BASE_ADDR ((void *)(0x09800000))
300 #define EDMA3_TC1_BASE_ADDR ((void *)(0x09900000))
301 #define EDMA3_TC2_BASE_ADDR ((void *)(0x09A00000))
302 #define EDMA3_TC3_BASE_ADDR ((void *)(0x09B00000))
303 #else
304 #define EDMA3_CC_BASE_ADDR ((void *)(0x49000000))
305 #define EDMA3_TC0_BASE_ADDR ((void *)(0x49800000))
306 #define EDMA3_TC1_BASE_ADDR ((void *)(0x49900000))
307 #define EDMA3_TC2_BASE_ADDR ((void *)(0x49A00000))
308 #define EDMA3_TC3_BASE_ADDR ((void *)(0x49B00000))
309 #endif
311 /* Driver Object Initialization Configuration */
312 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
313 {
314 {
315 /* EDMA3 INSTANCE# 0 */
316 /** Total number of DMA Channels supported by the EDMA3 Controller */
317 EDMA3_NUM_DMA_CHANNELS,
318 /** Total number of QDMA Channels supported by the EDMA3 Controller */
319 EDMA3_NUM_QDMA_CHANNELS,
320 /** Total number of TCCs supported by the EDMA3 Controller */
321 EDMA3_NUM_TCC,
322 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
323 EDMA3_NUM_PARAMSET,
324 /** Total number of Event Queues in the EDMA3 Controller */
325 EDMA3_NUM_EVTQUE,
326 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
327 EDMA3_NUM_TC,
328 /** Number of Regions on this EDMA3 controller */
329 EDMA3_NUM_REGIONS,
331 /**
332 * \brief Channel mapping existence
333 * A value of 0 (No channel mapping) implies that there is fixed association
334 * for a channel number to a parameter entry number or, in other words,
335 * PaRAM entry n corresponds to channel n.
336 */
337 1u,
339 /** Existence of memory protection feature */
340 0u,
342 /** Global Register Region of CC Registers */
343 EDMA3_CC_BASE_ADDR,
344 /** Transfer Controller (TC) Registers */
345 {
346 EDMA3_TC0_BASE_ADDR,
347 EDMA3_TC1_BASE_ADDR,
348 EDMA3_TC2_BASE_ADDR,
349 EDMA3_TC3_BASE_ADDR,
350 (void *)NULL,
351 (void *)NULL,
352 (void *)NULL,
353 (void *)NULL
354 },
355 /** Interrupt no. for Transfer Completion */
356 EDMA3_CC_XFER_COMPLETION_INT,
357 /** Interrupt no. for CC Error */
358 EDMA3_CC_ERROR_INT,
359 /** Interrupt no. for TCs Error */
360 {
361 EDMA3_TC0_ERROR_INT,
362 EDMA3_TC1_ERROR_INT,
363 EDMA3_TC2_ERROR_INT,
364 EDMA3_TC3_ERROR_INT,
365 EDMA3_TC4_ERROR_INT,
366 EDMA3_TC5_ERROR_INT,
367 EDMA3_TC6_ERROR_INT,
368 EDMA3_TC7_ERROR_INT
369 },
371 /**
372 * \brief EDMA3 TC priority setting
373 *
374 * User can program the priority of the Event Queues
375 * at a system-wide level. This means that the user can set the
376 * priority of an IO initiated by either of the TCs (Transfer Controllers)
377 * relative to IO initiated by the other bus masters on the
378 * device (ARM, DSP, USB, etc)
379 */
380 {
381 0u,
382 1u,
383 2u,
384 3u,
385 0u,
386 0u,
387 0u,
388 0u
389 },
390 /**
391 * \brief To Configure the Threshold level of number of events
392 * that can be queued up in the Event queues. EDMA3CC error register
393 * (CCERR) will indicate whether or not at any instant of time the
394 * number of events queued up in any of the event queues exceeds
395 * or equals the threshold/watermark value that is set
396 * in the queue watermark threshold register (QWMTHRA).
397 */
398 {
399 16u,
400 16u,
401 16u,
402 16u,
403 0u,
404 0u,
405 0u,
406 0u
407 },
409 /**
410 * \brief To Configure the Default Burst Size (DBS) of TCs.
411 * An optimally-sized command is defined by the transfer controller
412 * default burst size (DBS). Different TCs can have different
413 * DBS values. It is defined in Bytes.
414 */
415 {
416 16u,
417 16u,
418 16u,
419 16u,
420 0u,
421 0u,
422 0u,
423 0u
424 },
426 /**
427 * \brief Mapping from each DMA channel to a Parameter RAM set,
428 * if it exists, otherwise of no use.
429 */
430 {
431 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
432 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
433 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
434 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
435 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
436 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
437 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
438 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
439 },
441 /**
442 * \brief Mapping from each DMA channel to a TCC. This specific
443 * TCC code will be returned when the transfer is completed
444 * on the mapped channel.
445 */
446 {
447 0u, 1u, 2u, 3u,
448 4u, 5u, 6u, 7u,
449 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
450 12u, 13u, 14u, 15u,
451 16u, 17u, 18u, 19u,
452 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
453 24u, 25u, 26u, 27u,
454 28u, 29u, 30u, 31u,
455 32u, 33u, 34u, 35u,
456 36u, 37u, 38u, 39u,
457 40u, 41u, 42u, 43u,
458 44u, 45u, 46u, 47u,
459 48u, 49u, 50u, 51u,
460 52u, 53u, 54u, 55u,
461 56u, 57u, 58u, 59u,
462 60u, 61u, 62u, 63u
463 },
465 /**
466 * \brief Mapping of DMA channels to Hardware Events from
467 * various peripherals, which use EDMA for data transfer.
468 * All channels need not be mapped, some can be free also.
469 */
470 {
471 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
472 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
473 }
474 },
475 };
477 /**
478 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
479 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
480 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
481 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
482 *
483 * Only Resources owned by a perticular core are allocated by Driver
484 * Reserved resources are not allocated if requested for any available resource
485 */
487 /* Defines for Own DMA channels For different cores */
488 /* channels 0 to 31 */
489 #define EDMA3_OWN_DMA_CHANNELS_0_A8 (0xFFFFFFFFu)
490 #define EDMA3_OWN_DMA_CHANNELS_0_DSP (0xFFFFFFFFu)
491 #define EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO (0xFFFFFFFFu)
492 #define EDMA3_OWN_DMA_CHANNELS_0_M3VPSS (0xFFFFFFFFu)
493 /* Channels 32 to 63 */
494 #define EDMA3_OWN_DMA_CHANNELS_1_A8 (0xFFFFFFFFu)
495 #define EDMA3_OWN_DMA_CHANNELS_1_DSP (0xFFFFFFFFu)
496 #define EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO (0xFFFFFFFFu)
497 #define EDMA3_OWN_DMA_CHANNELS_1_M3VPSS (0xFFFFFFFFu)
499 /* Defines for Own QDMA channels For different cores */
500 #define EDMA3_OWN_QDMA_CHANNELS_0_A8 (0x000000FFu)
501 #define EDMA3_OWN_QDMA_CHANNELS_0_DSP (0x000000FFu)
502 #define EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO (0x000000FFu)
503 #define EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS (0x000000FFu)
505 /* Defines for Own TCCs For different cores */
506 #define EDMA3_OWN_TCC_0_A8 (0xFFFFFFFFu)
507 #define EDMA3_OWN_TCC_0_DSP (0xFFFFFFFFu)
508 #define EDMA3_OWN_TCC_0_M3VIDEO (0xFFFFFFFFu)
509 #define EDMA3_OWN_TCC_0_M3VPSS (0xFFFFFFFFu)
510 /* Channels 32 to 63 */
511 #define EDMA3_OWN_TCC_1_A8 (0xFFFFFFFFu)
512 #define EDMA3_OWN_TCC_1_DSP (0xFFFFFFFFu)
513 #define EDMA3_OWN_TCC_1_M3VIDEO (0xFFFFFFFFu)
514 #define EDMA3_OWN_TCC_1_M3VPSS (0xFFFFFFFFu)
516 /* Defines for Reserved DMA channels For different cores */
517 /* channels 0 to 31 */
518 #define EDMA3_RESERVED_DMA_CHANNELS_0_A8 (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
519 #define EDMA3_RESERVED_DMA_CHANNELS_0_DSP (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
520 #define EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO (0x00u)
521 #define EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS (0x00u)
522 /* Channels 32 to 63 */
523 #define EDMA3_RESERVED_DMA_CHANNELS_1_A8 (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
524 #define EDMA3_RESERVED_DMA_CHANNELS_1_DSP (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
525 #define EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO (0x00u)
526 #define EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS (0x00u)
528 /* Defines for RESERVED QDMA channels For different cores */
529 #define EDMA3_RESERVED_QDMA_CHANNELS_0_A8 (0x00u)
530 #define EDMA3_RESERVED_QDMA_CHANNELS_0_DSP (0x00u)
531 #define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO (0x00u)
532 #define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS (0x00u)
534 /* Defines for RESERVED TCCs For different cores */
535 #define EDMA3_RESERVED_TCC_0_A8 (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
536 #define EDMA3_RESERVED_TCC_0_DSP (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
537 #define EDMA3_RESERVED_TCC_0_M3VIDEO (0x00u)
538 #define EDMA3_RESERVED_TCC_0_M3VPSS (0x00u)
539 /* Channels 32 to 63 */
540 #define EDMA3_RESERVED_TCC_1_A8 (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
541 #define EDMA3_RESERVED_TCC_1_DSP (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
542 #define EDMA3_RESERVED_TCC_1_M3VIDEO (0x00u)
543 #define EDMA3_RESERVED_TCC_1_M3VPSS (0x00u)
545 /* Driver Instance Initialization Configuration */
546 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
547 {
548 /* EDMA3 INSTANCE# 0 */
549 {
550 /* Resources owned/reserved by region 0 (Configuration for Centaurus A8 Core)*/
551 {
552 /* ownPaRAMSets */
553 /* 31 0 63 32 95 64 127 96 */
554 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
555 /* 159 128 191 160 223 192 255 224 */
556 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
557 /* 287 256 319 288 351 320 383 352 */
558 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
559 /* 415 384 447 416 479 448 511 480 */
560 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
562 /* ownDmaChannels */
563 /* 31 0 63 32 */
564 {EDMA3_OWN_DMA_CHANNELS_0_A8, EDMA3_OWN_DMA_CHANNELS_1_A8},
566 /* ownQdmaChannels */
567 /* 31 0 */
568 {EDMA3_OWN_QDMA_CHANNELS_0_A8},
570 /* ownTccs */
571 /* 31 0 63 32 */
572 {EDMA3_OWN_TCC_0_A8, EDMA3_OWN_TCC_1_A8},
574 /* resvdPaRAMSets */
575 /* 31 0 63 32 95 64 127 96 */
576 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
577 /* 159 128 191 160 223 192 255 224 */
578 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
579 /* 287 256 319 288 351 320 383 352 */
580 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
581 /* 415 384 447 416 479 448 511 480 */
582 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
584 /* resvdDmaChannels */
585 /* 31 0 63 32 */
586 {EDMA3_RESERVED_DMA_CHANNELS_0_A8, EDMA3_RESERVED_DMA_CHANNELS_1_A8},
588 /* resvdQdmaChannels */
589 /* 31 0 */
590 {EDMA3_RESERVED_QDMA_CHANNELS_0_A8},
592 /* resvdTccs */
593 /* 31 0 63 32 */
594 {EDMA3_RESERVED_TCC_0_A8, EDMA3_RESERVED_TCC_1_A8},
595 },
597 /* Resources owned/reserved by region 1 (Configuration for Centaurus DSP Core)*/
598 {
599 /* ownPaRAMSets */
600 /* 31 0 63 32 95 64 127 96 */
601 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
602 /* 159 128 191 160 223 192 255 224 */
603 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
604 /* 287 256 319 288 351 320 383 352 */
605 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
606 /* 415 384 447 416 479 448 511 480 */
607 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
609 /* ownDmaChannels */
610 /* 31 0 63 32 */
611 {EDMA3_OWN_DMA_CHANNELS_0_DSP, EDMA3_OWN_DMA_CHANNELS_1_DSP},
613 /* ownQdmaChannels */
614 /* 31 0 */
615 {EDMA3_OWN_QDMA_CHANNELS_0_DSP},
617 /* ownTccs */
618 /* 31 0 63 32 */
619 {EDMA3_OWN_TCC_0_DSP, EDMA3_OWN_TCC_1_DSP},
621 /* resvdPaRAMSets */
622 /* 31 0 63 32 95 64 127 96 */
623 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
624 /* 159 128 191 160 223 192 255 224 */
625 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
626 /* 287 256 319 288 351 320 383 352 */
627 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
628 /* 415 384 447 416 479 448 511 480 */
629 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
631 /* resvdDmaChannels */
632 /* 31 0 63 32 */
633 {EDMA3_RESERVED_DMA_CHANNELS_0_DSP, EDMA3_RESERVED_DMA_CHANNELS_1_DSP},
635 /* resvdQdmaChannels */
636 /* 31 0 */
637 {EDMA3_RESERVED_QDMA_CHANNELS_0_DSP},
639 /* resvdTccs */
640 /* 31 0 63 32 */
641 {EDMA3_RESERVED_TCC_0_DSP, EDMA3_RESERVED_TCC_1_DSP},
642 },
644 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/
645 {
646 /* ownPaRAMSets */
647 /* 31 0 63 32 95 64 127 96 */
648 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
649 /* 159 128 191 160 223 192 255 224 */
650 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
651 /* 287 256 319 288 351 320 383 352 */
652 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
653 /* 415 384 447 416 479 448 511 480 */
654 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
656 /* ownDmaChannels */
657 /* 31 0 63 32 */
658 {0x00000000u, 0x00000000u},
660 /* ownQdmaChannels */
661 /* 31 0 */
662 {0x00000000u},
664 /* ownTccs */
665 /* 31 0 63 32 */
666 {0x00000000u, 0x00000000u},
668 /* resvdPaRAMSets */
669 /* 31 0 63 32 95 64 127 96 */
670 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
671 /* 159 128 191 160 223 192 255 224 */
672 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
673 /* 287 256 319 288 351 320 383 352 */
674 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
675 /* 415 384 447 416 479 448 511 480 */
676 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
678 /* resvdDmaChannels */
679 /* 31 0 63 32 */
680 {0x00000000u, 0x00000000u},
682 /* resvdQdmaChannels */
683 /* 31 0 */
684 {0x00000000u},
686 /* resvdTccs */
687 /* 31 0 63 32 */
688 {0x00000000u, 0x00000000u},
689 },
691 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
692 {
693 /* ownPaRAMSets */
694 /* 31 0 63 32 95 64 127 96 */
695 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
696 /* 159 128 191 160 223 192 255 224 */
697 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
698 /* 287 256 319 288 351 320 383 352 */
699 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
700 /* 415 384 447 416 479 448 511 480 */
701 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
703 /* ownDmaChannels */
704 /* 31 0 63 32 */
705 {0x00000000u, 0x00000000u},
707 /* ownQdmaChannels */
708 /* 31 0 */
709 {0x00000000u},
711 /* ownTccs */
712 /* 31 0 63 32 */
713 {0x00000000u, 0x00000000u},
715 /* resvdPaRAMSets */
716 /* 31 0 63 32 95 64 127 96 */
717 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
718 /* 159 128 191 160 223 192 255 224 */
719 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
720 /* 287 256 319 288 351 320 383 352 */
721 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
722 /* 415 384 447 416 479 448 511 480 */
723 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
725 /* resvdDmaChannels */
726 /* 31 0 63 32 */
727 {0x00000000u, 0x00000000u},
729 /* resvdQdmaChannels */
730 /* 31 0 */
731 {0x00000000u},
733 /* resvdTccs */
734 /* 31 0 63 32 */
735 {0x00000000u, 0x00000000u},
736 },
738 /* Resources owned/reserved by region 4 (Configuration for Centaurus M3VIDEO Core)*/
739 {
740 /* ownPaRAMSets */
741 /* 31 0 63 32 95 64 127 96 */
742 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
743 /* 159 128 191 160 223 192 255 224 */
744 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
745 /* 287 256 319 288 351 320 383 352 */
746 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
747 /* 415 384 447 416 479 448 511 480 */
748 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
750 /* ownDmaChannels */
751 /* 31 0 63 32 */
752 {EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO, EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO},
754 /* ownQdmaChannels */
755 /* 31 0 */
756 {EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO},
758 /* ownTccs */
759 /* 31 0 63 32 */
760 {EDMA3_OWN_TCC_0_M3VIDEO, EDMA3_OWN_TCC_0_M3VIDEO},
762 /* resvdPaRAMSets */
763 /* 31 0 63 32 95 64 127 96 */
764 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
765 /* 159 128 191 160 223 192 255 224 */
766 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
767 /* 287 256 319 288 351 320 383 352 */
768 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
769 /* 415 384 447 416 479 448 511 480 */
770 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
772 /* resvdDmaChannels */
773 /* 31 0 63 32 */
774 {EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO, EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO},
776 /* resvdQdmaChannels */
777 /* 31 0 */
778 {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO},
780 /* resvdTccs */
781 /* 31 0 63 32 */
782 {EDMA3_RESERVED_TCC_0_M3VIDEO, EDMA3_RESERVED_TCC_1_M3VIDEO},
783 },
785 /* Resources owned/reserved by region 5 (Configuration for Centaurus M3VPSS Core)*/
786 {
787 /* ownPaRAMSets */
788 /* 31 0 63 32 95 64 127 96 */
789 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
790 /* 159 128 191 160 223 192 255 224 */
791 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
792 /* 287 256 319 288 351 320 383 352 */
793 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
794 /* 415 384 447 416 479 448 511 480 */
795 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
797 /* ownDmaChannels */
798 /* 31 0 63 32 */
799 {EDMA3_OWN_DMA_CHANNELS_0_M3VPSS, EDMA3_OWN_DMA_CHANNELS_1_M3VPSS},
801 /* ownQdmaChannels */
802 /* 31 0 */
803 {EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS},
805 /* ownTccs */
806 /* 31 0 63 32 */
807 {EDMA3_OWN_TCC_0_M3VPSS, EDMA3_OWN_TCC_1_M3VPSS},
809 /* resvdPaRAMSets */
810 /* 31 0 63 32 95 64 127 96 */
811 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
812 /* 159 128 191 160 223 192 255 224 */
813 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
814 /* 287 256 319 288 351 320 383 352 */
815 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
816 /* 415 384 447 416 479 448 511 480 */
817 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
819 /* resvdDmaChannels */
820 /* 31 0 63 32 */
821 {EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS, EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS},
823 /* resvdQdmaChannels */
824 /* 31 0 */
825 {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS},
827 /* resvdTccs */
828 /* 31 0 63 32 */
829 {EDMA3_RESERVED_TCC_0_M3VPSS, EDMA3_RESERVED_TCC_1_M3VPSS},
830 },
832 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
833 {
834 /* ownPaRAMSets */
835 /* 31 0 63 32 95 64 127 96 */
836 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
837 /* 159 128 191 160 223 192 255 224 */
838 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
839 /* 287 256 319 288 351 320 383 352 */
840 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
841 /* 415 384 447 416 479 448 511 480 */
842 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
844 /* ownDmaChannels */
845 /* 31 0 63 32 */
846 {0x00000000u, 0x00000000u},
848 /* ownQdmaChannels */
849 /* 31 0 */
850 {0x00000000u},
852 /* ownTccs */
853 /* 31 0 63 32 */
854 {0x00000000u, 0x00000000u},
856 /* resvdPaRAMSets */
857 /* 31 0 63 32 95 64 127 96 */
858 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
859 /* 159 128 191 160 223 192 255 224 */
860 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
861 /* 287 256 319 288 351 320 383 352 */
862 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
863 /* 415 384 447 416 479 448 511 480 */
864 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
866 /* resvdDmaChannels */
867 /* 31 0 63 32 */
868 {0x00000000u, 0x00000000u},
870 /* resvdQdmaChannels */
871 /* 31 0 */
872 {0x00000000u},
874 /* resvdTccs */
875 /* 31 0 63 32 */
876 {0x00000000u, 0x00000000u},
877 },
879 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
880 {
881 /* ownPaRAMSets */
882 /* 31 0 63 32 95 64 127 96 */
883 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
884 /* 159 128 191 160 223 192 255 224 */
885 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
886 /* 287 256 319 288 351 320 383 352 */
887 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
888 /* 415 384 447 416 479 448 511 480 */
889 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
891 /* ownDmaChannels */
892 /* 31 0 63 32 */
893 {0x00000000u, 0x00000000u},
895 /* ownQdmaChannels */
896 /* 31 0 */
897 {0x00000000u},
899 /* ownTccs */
900 /* 31 0 63 32 */
901 {0x00000000u, 0x00000000u},
903 /* resvdPaRAMSets */
904 /* 31 0 63 32 95 64 127 96 */
905 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
906 /* 159 128 191 160 223 192 255 224 */
907 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
908 /* 287 256 319 288 351 320 383 352 */
909 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
910 /* 415 384 447 416 479 448 511 480 */
911 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
913 /* resvdDmaChannels */
914 /* 31 0 63 32 */
915 {0x00000000u, 0x00000000u},
917 /* resvdQdmaChannels */
918 /* 31 0 */
919 {0x00000000u},
921 /* resvdTccs */
922 /* 31 0 63 32 */
923 {0x00000000u, 0x00000000u},
924 },
925 },
926 };
928 /* Driver Instance Cross bar event to channel map Initialization Configuration */
929 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
930 {
931 /* EDMA3 INSTANCE# 0 */
932 {
933 /* Event to channel map for region 0 */
934 {
935 -1, -1, -1, -1, -1, -1, -1, -1,
936 -1, -1, -1, -1, -1, -1, -1, -1,
937 -1, -1, -1, -1, -1, -1, -1, -1,
938 -1, 26, 27, -1, -1, -1, -1, -1,
939 -1, -1, -1, -1, -1, -1, -1, -1,
940 -1, -1, -1, -1, -1, -1, -1, -1,
941 -1, -1, -1, -1, -1, -1, -1, -1,
942 -1, -1, -1, -1, -1, -1, -1
943 },
944 /* Event to channel map for region 1 */
945 {
946 -1, -1, -1, -1, -1, -1, -1, -1,
947 -1, -1, -1, -1, -1, -1, -1, -1,
948 -1, -1, -1, -1, -1, -1, -1, -1,
949 -1, 26, 27, -1, -1, -1, -1, -1,
950 -1, -1, -1, -1, -1, -1, -1, -1,
951 -1, -1, -1, -1, -1, -1, -1, -1,
952 -1, -1, -1, -1, -1, -1, -1, -1,
953 -1, -1, -1, -1, -1, -1, -1
954 },
955 /* Event to channel map for region 2 */
956 {
957 -1, -1, -1, -1, -1, -1, -1, -1,
958 -1, -1, -1, -1, -1, -1, -1, -1,
959 -1, -1, -1, -1, -1, -1, -1, -1,
960 -1, -1, -1, -1, -1, -1, -1, -1,
961 -1, -1, -1, -1, -1, -1, -1, -1,
962 -1, -1, -1, -1, -1, -1, -1, -1,
963 -1, -1, -1, -1, -1, -1, -1, -1,
964 -1, -1, -1, -1, -1, -1, -1
965 },
966 /* Event to channel map for region 3 */
967 {
968 -1, -1, -1, -1, -1, -1, -1, -1,
969 -1, -1, -1, -1, -1, -1, -1, -1,
970 -1, -1, -1, -1, -1, -1, -1, -1,
971 -1, -1, -1, -1, -1, -1, -1, -1,
972 -1, -1, -1, -1, -1, -1, -1, -1,
973 -1, -1, -1, -1, -1, -1, -1, -1,
974 -1, -1, -1, -1, -1, -1, -1, -1,
975 -1, -1, -1, -1, -1, -1, -1
976 },
977 /* Event to channel map for region 4 */
978 {
979 -1, -1, -1, -1, -1, -1, -1, -1,
980 -1, -1, -1, -1, -1, -1, -1, -1,
981 -1, -1, -1, -1, -1, -1, -1, -1,
982 -1, -1, -1, -1, -1, -1, -1, -1,
983 -1, -1, -1, -1, -1, -1, -1, -1,
984 -1, -1, -1, -1, -1, -1, -1, -1,
985 -1, -1, -1, -1, -1, -1, -1, -1,
986 -1, -1, -1, -1, -1, -1, -1
987 },
988 /* Event to channel map for region 5 */
989 {
990 -1, -1, -1, -1, -1, -1, -1, -1,
991 -1, -1, -1, -1, -1, -1, -1, -1,
992 -1, -1, -1, -1, -1, -1, -1, -1,
993 -1, -1, -1, -1, -1, -1, -1, -1,
994 -1, -1, -1, -1, -1, -1, -1, -1,
995 -1, -1, -1, -1, -1, -1, -1, -1,
996 -1, -1, -1, -1, -1, -1, -1, -1,
997 -1, -1, -1, -1, -1, -1, -1
998 },
999 /* Event to channel map for region 6 */
1000 {
1001 -1, -1, -1, -1, -1, -1, -1, -1,
1002 -1, -1, -1, -1, -1, -1, -1, -1,
1003 -1, -1, -1, -1, -1, -1, -1, -1,
1004 -1, -1, -1, -1, -1, -1, -1, -1,
1005 -1, -1, -1, -1, -1, -1, -1, -1,
1006 -1, -1, -1, -1, -1, -1, -1, -1,
1007 -1, -1, -1, -1, -1, -1, -1, -1,
1008 -1, -1, -1, -1, -1, -1, -1
1009 },
1010 /* Event to channel map for region 7 */
1011 {
1012 -1, -1, -1, -1, -1, -1, -1, -1,
1013 -1, -1, -1, -1, -1, -1, -1, -1,
1014 -1, -1, -1, -1, -1, -1, -1, -1,
1015 -1, -1, -1, -1, -1, -1, -1, -1,
1016 -1, -1, -1, -1, -1, -1, -1, -1,
1017 -1, -1, -1, -1, -1, -1, -1, -1,
1018 -1, -1, -1, -1, -1, -1, -1, -1,
1019 -1, -1, -1, -1, -1, -1, -1
1020 },
1021 }
1022 };
1024 /* End of File */