[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_c6a811x_int_reg.c
1 /*
2 * sample_c6a811x_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/family/c64p/EventCombiner.h>
41 #include <ti/sysbios/family/c64p/Hwi.h>
43 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
45 /**
46 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
47 * (Not all TC error ISRs need to be registered, register only for the
48 * available Transfer Controllers).
49 */
50 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
51 {
52 &lisrEdma3TC0ErrHandler0,
53 &lisrEdma3TC1ErrHandler0,
54 &lisrEdma3TC2ErrHandler0,
55 &lisrEdma3TC3ErrHandler0,
56 &lisrEdma3TC4ErrHandler0,
57 &lisrEdma3TC5ErrHandler0,
58 &lisrEdma3TC6ErrHandler0,
59 &lisrEdma3TC7ErrHandler0,
60 };
62 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
63 extern unsigned int ccErrorInt[];
64 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
65 extern unsigned int numEdma3Tc[];
67 /**
68 * Variables which will be used internally for referring the hardware interrupt
69 * for various EDMA3 interrupts.
70 */
71 extern unsigned int hwIntXferComp[];
72 extern unsigned int hwIntCcErr[];
73 extern unsigned int hwIntTcErr[];
75 extern unsigned int dsp_num;
77 /* External Instance Specific Configuration Structure */
78 extern EDMA3_DRV_GblXbarToChanConfigParams
79 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
81 typedef struct {
82 volatile Uint32 DSP_INTMUX[21];
83 volatile Uint32 DUCATI_INTMUX[15];
84 volatile Uint32 TPCC_EVTMUX[16];
85 volatile Uint32 TIMER_EVTCAPT;
86 volatile Uint32 GPIO_MUX;
87 } CSL_IntmuxRegs;
89 typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;
92 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
93 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
94 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
97 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
98 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
109 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
112 #define EDMA3_MAX_CROSS_BAR_EVENTS_C6A811X (127u)
113 #define EDMA3_NUM_TCC (64u)
115 /*
116 * Forward decleration
117 */
118 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
119 unsigned int *chanNum,
120 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
121 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
122 unsigned int chanNum);
125 /** To Register the ISRs with the underlying OS, if required. */
126 void registerEdma3Interrupts (unsigned int edma3Id)
127 {
128 static UInt32 cookie = 0;
129 unsigned int numTc = 0;
131 /* Disabling the global interrupts */
132 cookie = Hwi_disable();
134 /* Enable the Xfer Completion Event Interrupt */
135 EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
136 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
137 edma3Id, 1);
138 EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
140 /* Enable the CC Error Event Interrupt */
141 EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
142 (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
143 edma3Id, 1);
144 EventCombiner_enableEvent(ccErrorInt[edma3Id]);
146 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
147 while (numTc < numEdma3Tc[edma3Id])
148 {
149 EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
150 (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
151 edma3Id, 1);
152 EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
153 numTc++;
154 }
156 /**
157 * Enabling the HWI_ID.
158 * EDMA3 interrupts (transfer completion, CC error etc.)
159 * correspond to different ECM events (SoC specific). These ECM events come
160 * under ECM block XXX (handling those specific ECM events). Normally, block
161 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
162 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
163 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
164 * mapped HWI_INT YYY, one should use the corresponding bitmask in the
165 * API C64_enableIER(), in which the YYY bit is SET.
166 */
167 Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
168 Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
169 Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
171 /* Restore interrupts */
172 Hwi_restore(cookie);
173 }
175 /** To Unregister the ISRs with the underlying OS, if previously registered. */
176 void unregisterEdma3Interrupts (unsigned int edma3Id)
177 {
178 static UInt32 cookie = 0;
179 unsigned int numTc = 0;
181 /* Disabling the global interrupts */
182 cookie = Hwi_disable();
184 /* Disable the Xfer Completion Event Interrupt */
185 EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
187 /* Disable the CC Error Event Interrupt */
188 EventCombiner_disableEvent(ccErrorInt[edma3Id]);
190 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
191 while (numTc < numEdma3Tc[edma3Id])
192 {
193 EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
194 numTc++;
195 }
197 /* Restore interrupts */
198 Hwi_restore(cookie);
199 }
201 /**
202 * \brief sampleMapXbarEvtToChan
203 *
204 * This function reads from the sample configuration structure which specifies
205 * cross bar events mapped to DMA channel.
206 *
207 * \return EDMA3_DRV_SOK if success, else error code
208 */
209 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
210 unsigned int *chanNum,
211 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
212 {
213 EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
214 unsigned int xbarEvtNum = 0;
215 int edmaChanNum = 0;
217 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_C6A811X) &&
218 (chanNum != NULL) &&
219 (edmaGblXbarConfig != NULL))
220 {
221 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
222 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
223 if (edmaChanNum != -1)
224 {
225 *chanNum = edmaChanNum;
226 edma3Result = EDMA3_DRV_SOK;
227 }
228 }
229 return (edma3Result);
230 }
233 /**
234 * \brief sampleConfigScr
235 *
236 * This function configures control config registers for the cross bar events
237 * mapped to the EDMA channel.
238 *
239 * \return EDMA3_DRV_SOK if success, else error code
240 */
241 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
242 unsigned int chanNum)
243 {
244 EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
245 unsigned int scrChanOffset = 0;
246 unsigned int scrRegOffset = 0;
247 unsigned int xBarEvtNum = 0;
248 CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x08140F00);
251 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_C6A811X) &&
252 (chanNum < EDMA3_NUM_TCC))
253 {
254 scrRegOffset = chanNum / 4;
255 scrChanOffset = chanNum - (scrRegOffset * 4);
256 xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
258 switch(scrChanOffset)
259 {
260 case 0:
261 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
262 (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
263 break;
264 case 1:
265 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
266 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
267 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
268 break;
269 case 2:
270 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
271 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) &
272 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
273 break;
274 case 3:
275 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
276 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) &
277 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
278 break;
279 default:
280 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
281 break;
282 }
283 }
284 else
285 {
286 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
287 }
288 return edma3Result;
289 }
291 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
292 unsigned int edma3Id)
293 {
294 EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
295 const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
296 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
297 if (hEdma != NULL)
298 {
299 retVal = EDMA3_DRV_initXbarEventMap(hEdma,
300 sampleXbarToChanConfig,
301 &sampleMapXbarEvtToChan,
302 &sampleConfigScr);
303 }
305 return retVal;
306 }