Cleaned EDMA3 Driver Sample Initialization library
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_da830_cfg.c
1 /*
2  * sample_da830_cfg.c
3  *
4  * SoC specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES                     1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                                        1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53         {
54 #if 0   
55         volatile unsigned int *addr;
56         unsigned int core_no;
58     /* Identify the core number */
59     addr = (unsigned int *)(CGEM_REG_START+0x40000);
60     core_no = ((*addr) & 0x000F0000)>>16;
62         return core_no;
63 #endif
64         return 1;
65         }
67 unsigned short isGblConfigRequired(unsigned int dspNum)
68         {
69         (void) dspNum;
70         
71         return 1;
72         }
74 /* Semaphore handles */
75 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
77 /** Number of PaRAM Sets available */
78 #define EDMA3_NUM_PARAMSET                              (128u)
79 /** Number of TCCS available */
80 #define EDMA3_NUM_TCC                                   (32u)
81 /** Number of Event Queues available */
82 #define EDMA3_NUM_EVTQUE                                (2u)
83 /** Number of Transfer Controllers available */
84 #define EDMA3_NUM_TC                                    (2u)
85 /** Interrupt no. for Transfer Completion */
86 #define EDMA3_CC_XFER_COMPLETION_INT                    (8u)
87 /** Interrupt no. for CC Error */
88 #define EDMA3_CC_ERROR_INT                              (56u)
89 /** Interrupt no. for TCs Error */
90 #define EDMA3_TC0_ERROR_INT                             (57u)
91 #define EDMA3_TC1_ERROR_INT                             (58u)
92 #define EDMA3_TC2_ERROR_INT                             (0u)
93 #define EDMA3_TC3_ERROR_INT                             (0u)
94 #define EDMA3_TC4_ERROR_INT                             (0u)
95 #define EDMA3_TC5_ERROR_INT                             (0u)
96 #define EDMA3_TC6_ERROR_INT                             (0u)
97 #define EDMA3_TC7_ERROR_INT                             (0u)
99 /**
100 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
101 * ECM events (SoC specific). These ECM events come
102 * under ECM block XXX (handling those specific ECM events). Normally, block
103 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
104 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
105 * is mapped to a specific HWI_INT YYY in the tcf file.
106 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
107 * to transfer completion interrupt.
108 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
109 * to CC error interrupts.
110 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
111 * to TC error interrupts.
112 */
113 #define EDMA3_HWI_INT_XFER_COMP                                                 (7u)
114 #define EDMA3_HWI_INT_CC_ERR                                                    (8u)
115 #define EDMA3_HWI_INT_TC_ERR                                                    (8u)
118 /**
119  * \brief Mapping of DMA channels 0-31 to Hardware Events from
120  * various peripherals, which use EDMA for data transfer.
121  * All channels need not be mapped, some can be free also.
122  * 1: Mapped
123  * 0: Not mapped
124  *
125  * This mapping will be used to allocate DMA channels when user passes
126  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
127  * copy). The same mapping is used to allocate the TCC when user passes
128  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
129  *
130  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
131  */
132                                                                                                           /* 31     0 */
133 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xCF3FFFFFu)
135 /**
136  * \brief Mapping of DMA channels 32-63 to Hardware Events from
137  * various peripherals, which use EDMA for data transfer.
138  * All channels need not be mapped, some can be free also.
139  * 1: Mapped
140  * 0: Not mapped
141  *
142  * This mapping will be used to allocate DMA channels when user passes
143  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
144  * copy). The same mapping is used to allocate the TCC when user passes
145  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
146  *
147  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
148  */
149 /* DMA channels 32-63 DOES NOT exist in DA830. */
150 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x0u)
152 /* Variable which will be used internally for referring number of Event Queues. */
153 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
155 /* Variable which will be used internally for referring number of TCs. */
156 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
158 /**
159  * Variable which will be used internally for referring transfer completion
160  * interrupt.
161  */
162 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
163                                                         {
164                                                         0u, EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,
165                                                         0u, 0u, 0u, 0u,
166                                                         },
167                         };
169 /**
170  * Variable which will be used internally for referring channel controller's
171  * error interrupt.
172  */
173 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
175 /**
176  * Variable which will be used internally for referring transfer controllers'
177  * error interrupts.
178  */
179 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
180                                 {
181                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
182                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
183                                 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
184                                 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
185                                 }
186                             };
188 /**
189  * Variables which will be used internally for referring the hardware interrupt
190  * for various EDMA3 interrupts.
191  */
192 unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
193 unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
194 unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
197 /* Driver Object Initialization Configuration */
198 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
199         {
200             {
201             /** Total number of DMA Channels supported by the EDMA3 Controller */
202             32u,
203             /** Total number of QDMA Channels supported by the EDMA3 Controller */
204             8u,
205             /** Total number of TCCs supported by the EDMA3 Controller */
206             32u,
207             /** Total number of PaRAM Sets supported by the EDMA3 Controller */
208             128u,
209             /** Total number of Event Queues in the EDMA3 Controller */
210             2u,
211             /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
212             2u,
213             /** Number of Regions on this EDMA3 controller */
214             4u,
216             /**
217              * \brief Channel mapping existence
218              * A value of 0 (No channel mapping) implies that there is fixed association
219              * for a channel number to a parameter entry number or, in other words,
220              * PaRAM entry n corresponds to channel n.
221              */
222             0u,
224             /** Existence of memory protection feature */
225             0u,
227             /** Global Register Region of CC Registers */
228             (void *)0x01C00000u,
229             /** Transfer Controller (TC) Registers */
230                 {
231                 (void *)0x01C08000u,
232                 (void *)0x01C08400u,
233                 (void *)NULL,
234                 (void *)NULL,
235                 (void *)NULL,
236                 (void *)NULL,
237                 (void *)NULL,
238                 (void *)NULL
239                 },
240             /** Interrupt no. for Transfer Completion */
241             EDMA3_CC_XFER_COMPLETION_INT,
242             /** Interrupt no. for CC Error */
243             EDMA3_CC_ERROR_INT,
244             /** Interrupt no. for TCs Error */
245                 {
246                 EDMA3_TC0_ERROR_INT,
247                 EDMA3_TC1_ERROR_INT,
248                 EDMA3_TC2_ERROR_INT,
249                 EDMA3_TC3_ERROR_INT,
250                 EDMA3_TC4_ERROR_INT,
251                 EDMA3_TC5_ERROR_INT,
252                 EDMA3_TC6_ERROR_INT,
253                 EDMA3_TC7_ERROR_INT
254                 },
256             /**
257              * \brief EDMA3 TC priority setting
258              *
259              * User can program the priority of the Event Queues
260              * at a system-wide level.  This means that the user can set the
261              * priority of an IO initiated by either of the TCs (Transfer Controllers)
262              * relative to IO initiated by the other bus masters on the
263              * device (ARM, DSP, USB, etc)
264              */
265                 {
266                 0u,
267                 1u,
268                 0u,
269                 0u,
270                 0u,
271                 0u,
272                 0u,
273                 0u
274                 },
275             /**
276              * \brief To Configure the Threshold level of number of events
277              * that can be queued up in the Event queues. EDMA3CC error register
278              * (CCERR) will indicate whether or not at any instant of time the
279              * number of events queued up in any of the event queues exceeds
280              * or equals the threshold/watermark value that is set
281              * in the queue watermark threshold register (QWMTHRA).
282              */
283                 {
284                 16u,
285                 16u,
286                 0u,
287                 0u,
288                 0u,
289                 0u,
290                 0u,
291                 0u
292                 },
294             /**
295              * \brief To Configure the Default Burst Size (DBS) of TCs.
296              * An optimally-sized command is defined by the transfer controller
297              * default burst size (DBS). Different TCs can have different
298              * DBS values. It is defined in Bytes.
299              */
300                 {
301                 16u,
302                 16u,
303                 0u,
304                 0u,
305                 0u,
306                 0u,
307                 0u,
308                 0u
309                 },
311             /**
312              * \brief Mapping from each DMA channel to a Parameter RAM set,
313              * if it exists, otherwise of no use.
314              */
315                 {
316                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
317                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
318                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
319                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
320                 /* DMA channels 32-63 DOES NOT exist in DA830. */
321                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
322                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
323                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
324                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
325                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
326                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
327                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
328                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
329                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
330                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
331                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
332                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
333                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
334                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
335                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
336                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
337                 },
339              /**
340               * \brief Mapping from each DMA channel to a TCC. This specific
341               * TCC code will be returned when the transfer is completed
342               * on the mapped channel.
343               */
344                 {
345                 0u, 1u, 2u, 3u,
346                 4u, 5u, 6u, 7u,
347                 8u, 9u, 10u, 11u,
348                 12u, 13u, 14u, 15u,
349                 16u, 17u, 18u, 19u,
350                 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
351                 24u, 25u, 26u, 27u,
352                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31,
353                 /* DMA channels 32-63 DOES NOT exist in DA830. */
354                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
355                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
356                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
357                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
358                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
359                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
360                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
361                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
362                 },
364             /**
365              * \brief Mapping of DMA channels to Hardware Events from
366              * various peripherals, which use EDMA for data transfer.
367              * All channels need not be mapped, some can be free also.
368              */
369                 {
370                 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
371                 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
372                 },
373                 },
374         };
377 /* Driver Instance Initialization Configuration */
378 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
379         {
380                 /* EDMA3 INSTANCE# 0 */
381                 {
382                         /* Resources owned/reserved by region 0 */
383                         {
384                                 /* ownPaRAMSets */
385                                 /* 31     0     63    32     95    64     127   96 */
386                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
387                                 /* 159  128     191  160     223  192     255  224 */
388                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
389                                 /* 287  256     319  288     351  320     383  352 */
390                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
391                                 /* 415  384     447  416     479  448     511  480 */
392                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
394                                 /* ownDmaChannels */
395                                 /* 31     0     63    32 */
396                                 {0x00000000u, 0x00000000u},
398                                 /* ownQdmaChannels */
399                                 /* 31     0 */
400                                 {0x00000000u},
402                                 /* ownTccs */
403                                 /* 31     0     63    32 */
404                                 {0x00000000u, 0x00000000u},
406                                 /* resvdPaRAMSets */
407                                 /* 31     0     63    32     95    64     127   96 */
408                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
409                                 /* 159  128     191  160     223  192     255  224 */
410                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
411                                 /* 287  256     319  288     351  320     383  352 */
412                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
413                                 /* 415  384     447  416     479  448     511  480 */
414                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
416                                 /* resvdDmaChannels */
417                                 /* 31     0     63    32 */
418                                 {0x00000000u, 0x00000000u},
420                                 /* resvdQdmaChannels */
421                                 /* 31     0 */
422                                 {0x00000000u},
424                                 /* resvdTccs */
425                                 /* 31     0     63    32 */
426                                 {0x00000000u, 0x00000000u},
427                         },
428                     
429                 /* Resources owned/reserved by region 1 */
430                     {
431                         /* ownPaRAMSets */
432                         /* 31     0     63    32     95    64     127   96 */
433                         {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
434                         /* 159  128     191  160     223  192     255  224 */
435                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
436                         /* 287  256     319  288     351  320     383  352 */
437                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
438                         /* 415  384     447  416     479  448     511  480 */
439                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
441                         /* ownDmaChannels */
442                         /* 31     0     63    32 */
443                         {0xFFFFFFFFu, 0x00000000u},
445                         /* ownQdmaChannels */
446                         /* 31     0 */
447                         {0x000000FFu},
449                         /* ownTccs */
450                         /* 31     0     63    32 */
451                         {0xFFFFFFFFu, 0x00000000u},
453                         /* resvdPaRAMSets */
454                         /* 31     0     63    32     95    64     127   96 */
455                         {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
456                         /* 159  128     191  160     223  192     255  224 */
457                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
458                         /* 287  256     319  288     351  320     383  352 */
459                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
460                         /* 415  384     447  416     479  448     511  480 */
461                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
463                         /* resvdDmaChannels */
464                         /* 31                                                       0 */
465                         {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
466                         /* 63                                                     32 */
467                             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1},
469                         /* resvdQdmaChannels */
470                         /* 31     0 */
471                         {0x00000000u},
473                         /* resvdTccs */
474                         /* 31                                                       0 */
475                         {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
476                         /* 63                                                     32 */
477                             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}
478                     },
480                 /* Resources owned/reserved by region 2 */
481                         {
482                                 /* ownPaRAMSets */
483                                 /* 31     0     63    32     95    64     127   96 */
484                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
485                                 /* 159  128     191  160     223  192     255  224 */
486                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
487                                 /* 287  256     319  288     351  320     383  352 */
488                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
489                                 /* 415  384     447  416     479  448     511  480 */
490                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
492                                 /* ownDmaChannels */
493                                 /* 31     0     63    32 */
494                                 {0x00000000u, 0x00000000u},
496                                 /* ownQdmaChannels */
497                                 /* 31     0 */
498                                 {0x00000000u},
500                                 /* ownTccs */
501                                 /* 31     0     63    32 */
502                                 {0x00000000u, 0x00000000u},
504                                 /* resvdPaRAMSets */
505                                 /* 31     0     63    32     95    64     127   96 */
506                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
507                                 /* 159  128     191  160     223  192     255  224 */
508                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
509                                 /* 287  256     319  288     351  320     383  352 */
510                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
511                                 /* 415  384     447  416     479  448     511  480 */
512                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
514                                 /* resvdDmaChannels */
515                                 /* 31     0     63    32 */
516                                 {0x00000000u, 0x00000000u},
518                                 /* resvdQdmaChannels */
519                                 /* 31     0 */
520                                 {0x00000000u},
522                                 /* resvdTccs */
523                                 /* 31     0     63    32 */
524                                 {0x00000000u, 0x00000000u},
525                         },
527                 /* Resources owned/reserved by region 3 */
528                         {
529                                 /* ownPaRAMSets */
530                                 /* 31     0     63    32     95    64     127   96 */
531                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
532                                 /* 159  128     191  160     223  192     255  224 */
533                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
534                                 /* 287  256     319  288     351  320     383  352 */
535                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
536                                 /* 415  384     447  416     479  448     511  480 */
537                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
539                                 /* ownDmaChannels */
540                                 /* 31     0     63    32 */
541                                 {0x00000000u, 0x00000000u},
543                                 /* ownQdmaChannels */
544                                 /* 31     0 */
545                                 {0x00000000u},
547                                 /* ownTccs */
548                                 /* 31     0     63    32 */
549                                 {0x00000000u, 0x00000000u},
551                                 /* resvdPaRAMSets */
552                                 /* 31     0     63    32     95    64     127   96 */
553                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
554                                 /* 159  128     191  160     223  192     255  224 */
555                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
556                                 /* 287  256     319  288     351  320     383  352 */
557                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
558                                 /* 415  384     447  416     479  448     511  480 */
559                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
561                                 /* resvdDmaChannels */
562                                 /* 31     0     63    32 */
563                                 {0x00000000u, 0x00000000u},
565                                 /* resvdQdmaChannels */
566                                 /* 31     0 */
567                                 {0x00000000u},
569                                 /* resvdTccs */
570                                 /* 31     0     63    32 */
571                                 {0x00000000u, 0x00000000u},
572                         },
574                 /* Resources owned/reserved by region 4 */
575                         {
576                                 /* ownPaRAMSets */
577                                 /* 31     0     63    32     95    64     127   96 */
578                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
579                                 /* 159  128     191  160     223  192     255  224 */
580                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
581                                 /* 287  256     319  288     351  320     383  352 */
582                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
583                                 /* 415  384     447  416     479  448     511  480 */
584                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
586                                 /* ownDmaChannels */
587                                 /* 31     0     63    32 */
588                                 {0x00000000u, 0x00000000u},
590                                 /* ownQdmaChannels */
591                                 /* 31     0 */
592                                 {0x00000000u},
594                                 /* ownTccs */
595                                 /* 31     0     63    32 */
596                                 {0x00000000u, 0x00000000u},
598                                 /* resvdPaRAMSets */
599                                 /* 31     0     63    32     95    64     127   96 */
600                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
601                                 /* 159  128     191  160     223  192     255  224 */
602                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
603                                 /* 287  256     319  288     351  320     383  352 */
604                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
605                                 /* 415  384     447  416     479  448     511  480 */
606                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
608                                 /* resvdDmaChannels */
609                                 /* 31     0     63    32 */
610                                 {0x00000000u, 0x00000000u},
612                                 /* resvdQdmaChannels */
613                                 /* 31     0 */
614                                 {0x00000000u},
616                                 /* resvdTccs */
617                                 /* 31     0     63    32 */
618                                 {0x00000000u, 0x00000000u},
619                         },
621                 /* Resources owned/reserved by region 5 */
622                         {
623                                 /* ownPaRAMSets */
624                                 /* 31     0     63    32     95    64     127   96 */
625                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
626                                 /* 159  128     191  160     223  192     255  224 */
627                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
628                                 /* 287  256     319  288     351  320     383  352 */
629                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
630                                 /* 415  384     447  416     479  448     511  480 */
631                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
633                                 /* ownDmaChannels */
634                                 /* 31     0     63    32 */
635                                 {0x00000000u, 0x00000000u},
637                                 /* ownQdmaChannels */
638                                 /* 31     0 */
639                                 {0x00000000u},
641                                 /* ownTccs */
642                                 /* 31     0     63    32 */
643                                 {0x00000000u, 0x00000000u},
645                                 /* resvdPaRAMSets */
646                                 /* 31     0     63    32     95    64     127   96 */
647                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
648                                 /* 159  128     191  160     223  192     255  224 */
649                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
650                                 /* 287  256     319  288     351  320     383  352 */
651                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
652                                 /* 415  384     447  416     479  448     511  480 */
653                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
655                                 /* resvdDmaChannels */
656                                 /* 31     0     63    32 */
657                                 {0x00000000u, 0x00000000u},
659                                 /* resvdQdmaChannels */
660                                 /* 31     0 */
661                                 {0x00000000u},
663                                 /* resvdTccs */
664                                 /* 31     0     63    32 */
665                                 {0x00000000u, 0x00000000u},
666                         },
668                 /* Resources owned/reserved by region 6 */
669                         {
670                                 /* ownPaRAMSets */
671                                 /* 31     0     63    32     95    64     127   96 */
672                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
673                                 /* 159  128     191  160     223  192     255  224 */
674                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
675                                 /* 287  256     319  288     351  320     383  352 */
676                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
677                                 /* 415  384     447  416     479  448     511  480 */
678                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
680                                 /* ownDmaChannels */
681                                 /* 31     0     63    32 */
682                                 {0x00000000u, 0x00000000u},
684                                 /* ownQdmaChannels */
685                                 /* 31     0 */
686                                 {0x00000000u},
688                                 /* ownTccs */
689                                 /* 31     0     63    32 */
690                                 {0x00000000u, 0x00000000u},
692                                 /* resvdPaRAMSets */
693                                 /* 31     0     63    32     95    64     127   96 */
694                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
695                                 /* 159  128     191  160     223  192     255  224 */
696                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
697                                 /* 287  256     319  288     351  320     383  352 */
698                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
699                                 /* 415  384     447  416     479  448     511  480 */
700                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
702                                 /* resvdDmaChannels */
703                                 /* 31     0     63    32 */
704                                 {0x00000000u, 0x00000000u},
706                                 /* resvdQdmaChannels */
707                                 /* 31     0 */
708                                 {0x00000000u},
710                                 /* resvdTccs */
711                                 /* 31     0     63    32 */
712                                 {0x00000000u, 0x00000000u},
713                         },
715                 /* Resources owned/reserved by region 7 */
716                         {
717                                 /* ownPaRAMSets */
718                                 /* 31     0     63    32     95    64     127   96 */
719                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
720                                 /* 159  128     191  160     223  192     255  224 */
721                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
722                                 /* 287  256     319  288     351  320     383  352 */
723                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
724                                 /* 415  384     447  416     479  448     511  480 */
725                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
727                                 /* ownDmaChannels */
728                                 /* 31     0     63    32 */
729                                 {0x00000000u, 0x00000000u},
731                                 /* ownQdmaChannels */
732                                 /* 31     0 */
733                                 {0x00000000u},
735                                 /* ownTccs */
736                                 /* 31     0     63    32 */
737                                 {0x00000000u, 0x00000000u},
739                                 /* resvdPaRAMSets */
740                                 /* 31     0     63    32     95    64     127   96 */
741                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
742                                 /* 159  128     191  160     223  192     255  224 */
743                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
744                                 /* 287  256     319  288     351  320     383  352 */
745                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
746                                 /* 415  384     447  416     479  448     511  480 */
747                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
749                                 /* resvdDmaChannels */
750                                 /* 31     0     63    32 */
751                                 {0x00000000u, 0x00000000u},
753                                 /* resvdQdmaChannels */
754                                 /* 31     0 */
755                                 {0x00000000u},
757                                 /* resvdTccs */
758                                 /* 31     0     63    32 */
759                                 {0x00000000u, 0x00000000u},
760                         },
761             },
762         };
763                     
766 /* End of File */