[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_da830_cfg.c
1 /*
2 * sample_da830_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54 #if 0
55 volatile unsigned int *addr;
56 unsigned int core_no;
58 /* Identify the core number */
59 addr = (unsigned int *)(CGEM_REG_START+0x40000);
60 core_no = ((*addr) & 0x000F0000)>>16;
62 return core_no;
63 #endif
64 return 1;
65 }
67 signed char* getGlobalAddr(signed char* addr)
68 {
69 return (addr); /* The address is already a global address */
70 }
71 unsigned short isGblConfigRequired(unsigned int dspNum)
72 {
73 (void) dspNum;
75 return 1;
76 }
78 /* Semaphore handles */
79 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
81 /** Number of PaRAM Sets available */
82 #define EDMA3_NUM_PARAMSET (128u)
83 /** Number of TCCS available */
84 #define EDMA3_NUM_TCC (32u)
85 /** Number of Event Queues available */
86 #define EDMA3_NUM_EVTQUE (2u)
87 /** Number of Transfer Controllers available */
88 #define EDMA3_NUM_TC (2u)
89 /** Interrupt no. for Transfer Completion */
90 #define EDMA3_CC_XFER_COMPLETION_INT (8u)
91 /** Interrupt no. for CC Error */
92 #define EDMA3_CC_ERROR_INT (56u)
93 /** Interrupt no. for TCs Error */
94 #define EDMA3_TC0_ERROR_INT (57u)
95 #define EDMA3_TC1_ERROR_INT (58u)
96 #define EDMA3_TC2_ERROR_INT (0u)
97 #define EDMA3_TC3_ERROR_INT (0u)
98 #define EDMA3_TC4_ERROR_INT (0u)
99 #define EDMA3_TC5_ERROR_INT (0u)
100 #define EDMA3_TC6_ERROR_INT (0u)
101 #define EDMA3_TC7_ERROR_INT (0u)
103 /**
104 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
105 * ECM events (SoC specific). These ECM events come
106 * under ECM block XXX (handling those specific ECM events). Normally, block
107 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
108 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
109 * is mapped to a specific HWI_INT YYY in the tcf file.
110 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
111 * to transfer completion interrupt.
112 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
113 * to CC error interrupts.
114 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
115 * to TC error interrupts.
116 */
117 #define EDMA3_HWI_INT_XFER_COMP (7u)
118 #define EDMA3_HWI_INT_CC_ERR (8u)
119 #define EDMA3_HWI_INT_TC_ERR (8u)
122 /**
123 * \brief Mapping of DMA channels 0-31 to Hardware Events from
124 * various peripherals, which use EDMA for data transfer.
125 * All channels need not be mapped, some can be free also.
126 * 1: Mapped
127 * 0: Not mapped
128 *
129 * This mapping will be used to allocate DMA channels when user passes
130 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
131 * copy). The same mapping is used to allocate the TCC when user passes
132 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
133 *
134 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
135 */
136 /* 31 0 */
137 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xCF3FFFFFu)
139 /**
140 * \brief Mapping of DMA channels 32-63 to Hardware Events from
141 * various peripherals, which use EDMA for data transfer.
142 * All channels need not be mapped, some can be free also.
143 * 1: Mapped
144 * 0: Not mapped
145 *
146 * This mapping will be used to allocate DMA channels when user passes
147 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
148 * copy). The same mapping is used to allocate the TCC when user passes
149 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
150 *
151 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
152 */
153 /* DMA channels 32-63 DOES NOT exist in DA830. */
154 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u)
156 /* Variable which will be used internally for referring number of Event Queues. */
157 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
159 /* Variable which will be used internally for referring number of TCs. */
160 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
162 /**
163 * Variable which will be used internally for referring transfer completion
164 * interrupt.
165 */
166 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
167 {
168 0u, EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,
169 0u, 0u, 0u, 0u,
170 },
171 };
173 /**
174 * Variable which will be used internally for referring channel controller's
175 * error interrupt.
176 */
177 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
179 /**
180 * Variable which will be used internally for referring transfer controllers'
181 * error interrupts.
182 */
183 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
184 {
185 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
186 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
187 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
188 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
189 }
190 };
192 /**
193 * Variables which will be used internally for referring the hardware interrupt
194 * for various EDMA3 interrupts.
195 */
196 unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
197 unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
198 unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
201 /* Driver Object Initialization Configuration */
202 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
203 {
204 {
205 /** Total number of DMA Channels supported by the EDMA3 Controller */
206 32u,
207 /** Total number of QDMA Channels supported by the EDMA3 Controller */
208 8u,
209 /** Total number of TCCs supported by the EDMA3 Controller */
210 32u,
211 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
212 128u,
213 /** Total number of Event Queues in the EDMA3 Controller */
214 2u,
215 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
216 2u,
217 /** Number of Regions on this EDMA3 controller */
218 4u,
220 /**
221 * \brief Channel mapping existence
222 * A value of 0 (No channel mapping) implies that there is fixed association
223 * for a channel number to a parameter entry number or, in other words,
224 * PaRAM entry n corresponds to channel n.
225 */
226 0u,
228 /** Existence of memory protection feature */
229 0u,
231 /** Global Register Region of CC Registers */
232 (void *)0x01C00000u,
233 /** Transfer Controller (TC) Registers */
234 {
235 (void *)0x01C08000u,
236 (void *)0x01C08400u,
237 (void *)NULL,
238 (void *)NULL,
239 (void *)NULL,
240 (void *)NULL,
241 (void *)NULL,
242 (void *)NULL
243 },
244 /** Interrupt no. for Transfer Completion */
245 EDMA3_CC_XFER_COMPLETION_INT,
246 /** Interrupt no. for CC Error */
247 EDMA3_CC_ERROR_INT,
248 /** Interrupt no. for TCs Error */
249 {
250 EDMA3_TC0_ERROR_INT,
251 EDMA3_TC1_ERROR_INT,
252 EDMA3_TC2_ERROR_INT,
253 EDMA3_TC3_ERROR_INT,
254 EDMA3_TC4_ERROR_INT,
255 EDMA3_TC5_ERROR_INT,
256 EDMA3_TC6_ERROR_INT,
257 EDMA3_TC7_ERROR_INT
258 },
260 /**
261 * \brief EDMA3 TC priority setting
262 *
263 * User can program the priority of the Event Queues
264 * at a system-wide level. This means that the user can set the
265 * priority of an IO initiated by either of the TCs (Transfer Controllers)
266 * relative to IO initiated by the other bus masters on the
267 * device (ARM, DSP, USB, etc)
268 */
269 {
270 0u,
271 1u,
272 0u,
273 0u,
274 0u,
275 0u,
276 0u,
277 0u
278 },
279 /**
280 * \brief To Configure the Threshold level of number of events
281 * that can be queued up in the Event queues. EDMA3CC error register
282 * (CCERR) will indicate whether or not at any instant of time the
283 * number of events queued up in any of the event queues exceeds
284 * or equals the threshold/watermark value that is set
285 * in the queue watermark threshold register (QWMTHRA).
286 */
287 {
288 16u,
289 16u,
290 0u,
291 0u,
292 0u,
293 0u,
294 0u,
295 0u
296 },
298 /**
299 * \brief To Configure the Default Burst Size (DBS) of TCs.
300 * An optimally-sized command is defined by the transfer controller
301 * default burst size (DBS). Different TCs can have different
302 * DBS values. It is defined in Bytes.
303 */
304 {
305 16u,
306 16u,
307 0u,
308 0u,
309 0u,
310 0u,
311 0u,
312 0u
313 },
315 /**
316 * \brief Mapping from each DMA channel to a Parameter RAM set,
317 * if it exists, otherwise of no use.
318 */
319 {
320 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
321 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
322 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
323 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
324 /* DMA channels 32-63 DOES NOT exist in DA830. */
325 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
326 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
327 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
328 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
329 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
330 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
331 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
332 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
333 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
334 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
335 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
336 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
337 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
338 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
339 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
340 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
341 },
343 /**
344 * \brief Mapping from each DMA channel to a TCC. This specific
345 * TCC code will be returned when the transfer is completed
346 * on the mapped channel.
347 */
348 {
349 0u, 1u, 2u, 3u,
350 4u, 5u, 6u, 7u,
351 8u, 9u, 10u, 11u,
352 12u, 13u, 14u, 15u,
353 16u, 17u, 18u, 19u,
354 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
355 24u, 25u, 26u, 27u,
356 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31,
357 /* DMA channels 32-63 DOES NOT exist in DA830. */
358 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
359 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
360 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
361 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
362 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
363 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
364 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
365 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
366 },
368 /**
369 * \brief Mapping of DMA channels to Hardware Events from
370 * various peripherals, which use EDMA for data transfer.
371 * All channels need not be mapped, some can be free also.
372 */
373 {
374 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
375 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
376 },
377 },
378 };
381 /* Driver Instance Initialization Configuration */
382 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
383 {
384 /* EDMA3 INSTANCE# 0 */
385 {
386 /* Resources owned/reserved by region 0 */
387 {
388 /* ownPaRAMSets */
389 /* 31 0 63 32 95 64 127 96 */
390 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
391 /* 159 128 191 160 223 192 255 224 */
392 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
393 /* 287 256 319 288 351 320 383 352 */
394 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
395 /* 415 384 447 416 479 448 511 480 */
396 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
398 /* ownDmaChannels */
399 /* 31 0 63 32 */
400 {0x00000000u, 0x00000000u},
402 /* ownQdmaChannels */
403 /* 31 0 */
404 {0x00000000u},
406 /* ownTccs */
407 /* 31 0 63 32 */
408 {0x00000000u, 0x00000000u},
410 /* resvdPaRAMSets */
411 /* 31 0 63 32 95 64 127 96 */
412 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
413 /* 159 128 191 160 223 192 255 224 */
414 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
415 /* 287 256 319 288 351 320 383 352 */
416 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
417 /* 415 384 447 416 479 448 511 480 */
418 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
420 /* resvdDmaChannels */
421 /* 31 0 63 32 */
422 {0x00000000u, 0x00000000u},
424 /* resvdQdmaChannels */
425 /* 31 0 */
426 {0x00000000u},
428 /* resvdTccs */
429 /* 31 0 63 32 */
430 {0x00000000u, 0x00000000u},
431 },
433 /* Resources owned/reserved by region 1 */
434 {
435 /* ownPaRAMSets */
436 /* 31 0 63 32 95 64 127 96 */
437 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
438 /* 159 128 191 160 223 192 255 224 */
439 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
440 /* 287 256 319 288 351 320 383 352 */
441 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
442 /* 415 384 447 416 479 448 511 480 */
443 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
445 /* ownDmaChannels */
446 /* 31 0 63 32 */
447 {0xFFFFFFFFu, 0x00000000u},
449 /* ownQdmaChannels */
450 /* 31 0 */
451 {0x000000FFu},
453 /* ownTccs */
454 /* 31 0 63 32 */
455 {0xFFFFFFFFu, 0x00000000u},
457 /* resvdPaRAMSets */
458 /* 31 0 63 32 95 64 127 96 */
459 {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
460 /* 159 128 191 160 223 192 255 224 */
461 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
462 /* 287 256 319 288 351 320 383 352 */
463 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
464 /* 415 384 447 416 479 448 511 480 */
465 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
467 /* resvdDmaChannels */
468 /* 31 0 */
469 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
470 /* 63 32 */
471 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1},
473 /* resvdQdmaChannels */
474 /* 31 0 */
475 {0x00000000u},
477 /* resvdTccs */
478 /* 31 0 */
479 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
480 /* 63 32 */
481 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}
482 },
484 /* Resources owned/reserved by region 2 */
485 {
486 /* ownPaRAMSets */
487 /* 31 0 63 32 95 64 127 96 */
488 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
489 /* 159 128 191 160 223 192 255 224 */
490 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
491 /* 287 256 319 288 351 320 383 352 */
492 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
493 /* 415 384 447 416 479 448 511 480 */
494 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
496 /* ownDmaChannels */
497 /* 31 0 63 32 */
498 {0x00000000u, 0x00000000u},
500 /* ownQdmaChannels */
501 /* 31 0 */
502 {0x00000000u},
504 /* ownTccs */
505 /* 31 0 63 32 */
506 {0x00000000u, 0x00000000u},
508 /* resvdPaRAMSets */
509 /* 31 0 63 32 95 64 127 96 */
510 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
511 /* 159 128 191 160 223 192 255 224 */
512 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
513 /* 287 256 319 288 351 320 383 352 */
514 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
515 /* 415 384 447 416 479 448 511 480 */
516 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
518 /* resvdDmaChannels */
519 /* 31 0 63 32 */
520 {0x00000000u, 0x00000000u},
522 /* resvdQdmaChannels */
523 /* 31 0 */
524 {0x00000000u},
526 /* resvdTccs */
527 /* 31 0 63 32 */
528 {0x00000000u, 0x00000000u},
529 },
531 /* Resources owned/reserved by region 3 */
532 {
533 /* ownPaRAMSets */
534 /* 31 0 63 32 95 64 127 96 */
535 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
536 /* 159 128 191 160 223 192 255 224 */
537 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
538 /* 287 256 319 288 351 320 383 352 */
539 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
540 /* 415 384 447 416 479 448 511 480 */
541 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
543 /* ownDmaChannels */
544 /* 31 0 63 32 */
545 {0x00000000u, 0x00000000u},
547 /* ownQdmaChannels */
548 /* 31 0 */
549 {0x00000000u},
551 /* ownTccs */
552 /* 31 0 63 32 */
553 {0x00000000u, 0x00000000u},
555 /* resvdPaRAMSets */
556 /* 31 0 63 32 95 64 127 96 */
557 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
558 /* 159 128 191 160 223 192 255 224 */
559 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
560 /* 287 256 319 288 351 320 383 352 */
561 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
562 /* 415 384 447 416 479 448 511 480 */
563 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
565 /* resvdDmaChannels */
566 /* 31 0 63 32 */
567 {0x00000000u, 0x00000000u},
569 /* resvdQdmaChannels */
570 /* 31 0 */
571 {0x00000000u},
573 /* resvdTccs */
574 /* 31 0 63 32 */
575 {0x00000000u, 0x00000000u},
576 },
578 /* Resources owned/reserved by region 4 */
579 {
580 /* ownPaRAMSets */
581 /* 31 0 63 32 95 64 127 96 */
582 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
583 /* 159 128 191 160 223 192 255 224 */
584 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
585 /* 287 256 319 288 351 320 383 352 */
586 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
587 /* 415 384 447 416 479 448 511 480 */
588 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
590 /* ownDmaChannels */
591 /* 31 0 63 32 */
592 {0x00000000u, 0x00000000u},
594 /* ownQdmaChannels */
595 /* 31 0 */
596 {0x00000000u},
598 /* ownTccs */
599 /* 31 0 63 32 */
600 {0x00000000u, 0x00000000u},
602 /* resvdPaRAMSets */
603 /* 31 0 63 32 95 64 127 96 */
604 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
605 /* 159 128 191 160 223 192 255 224 */
606 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
607 /* 287 256 319 288 351 320 383 352 */
608 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
609 /* 415 384 447 416 479 448 511 480 */
610 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
612 /* resvdDmaChannels */
613 /* 31 0 63 32 */
614 {0x00000000u, 0x00000000u},
616 /* resvdQdmaChannels */
617 /* 31 0 */
618 {0x00000000u},
620 /* resvdTccs */
621 /* 31 0 63 32 */
622 {0x00000000u, 0x00000000u},
623 },
625 /* Resources owned/reserved by region 5 */
626 {
627 /* ownPaRAMSets */
628 /* 31 0 63 32 95 64 127 96 */
629 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
630 /* 159 128 191 160 223 192 255 224 */
631 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
632 /* 287 256 319 288 351 320 383 352 */
633 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
634 /* 415 384 447 416 479 448 511 480 */
635 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
637 /* ownDmaChannels */
638 /* 31 0 63 32 */
639 {0x00000000u, 0x00000000u},
641 /* ownQdmaChannels */
642 /* 31 0 */
643 {0x00000000u},
645 /* ownTccs */
646 /* 31 0 63 32 */
647 {0x00000000u, 0x00000000u},
649 /* resvdPaRAMSets */
650 /* 31 0 63 32 95 64 127 96 */
651 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
652 /* 159 128 191 160 223 192 255 224 */
653 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
654 /* 287 256 319 288 351 320 383 352 */
655 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
656 /* 415 384 447 416 479 448 511 480 */
657 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
659 /* resvdDmaChannels */
660 /* 31 0 63 32 */
661 {0x00000000u, 0x00000000u},
663 /* resvdQdmaChannels */
664 /* 31 0 */
665 {0x00000000u},
667 /* resvdTccs */
668 /* 31 0 63 32 */
669 {0x00000000u, 0x00000000u},
670 },
672 /* Resources owned/reserved by region 6 */
673 {
674 /* ownPaRAMSets */
675 /* 31 0 63 32 95 64 127 96 */
676 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
677 /* 159 128 191 160 223 192 255 224 */
678 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
679 /* 287 256 319 288 351 320 383 352 */
680 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
681 /* 415 384 447 416 479 448 511 480 */
682 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
684 /* ownDmaChannels */
685 /* 31 0 63 32 */
686 {0x00000000u, 0x00000000u},
688 /* ownQdmaChannels */
689 /* 31 0 */
690 {0x00000000u},
692 /* ownTccs */
693 /* 31 0 63 32 */
694 {0x00000000u, 0x00000000u},
696 /* resvdPaRAMSets */
697 /* 31 0 63 32 95 64 127 96 */
698 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
699 /* 159 128 191 160 223 192 255 224 */
700 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
701 /* 287 256 319 288 351 320 383 352 */
702 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
703 /* 415 384 447 416 479 448 511 480 */
704 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
706 /* resvdDmaChannels */
707 /* 31 0 63 32 */
708 {0x00000000u, 0x00000000u},
710 /* resvdQdmaChannels */
711 /* 31 0 */
712 {0x00000000u},
714 /* resvdTccs */
715 /* 31 0 63 32 */
716 {0x00000000u, 0x00000000u},
717 },
719 /* Resources owned/reserved by region 7 */
720 {
721 /* ownPaRAMSets */
722 /* 31 0 63 32 95 64 127 96 */
723 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
724 /* 159 128 191 160 223 192 255 224 */
725 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
726 /* 287 256 319 288 351 320 383 352 */
727 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
728 /* 415 384 447 416 479 448 511 480 */
729 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
731 /* ownDmaChannels */
732 /* 31 0 63 32 */
733 {0x00000000u, 0x00000000u},
735 /* ownQdmaChannels */
736 /* 31 0 */
737 {0x00000000u},
739 /* ownTccs */
740 /* 31 0 63 32 */
741 {0x00000000u, 0x00000000u},
743 /* resvdPaRAMSets */
744 /* 31 0 63 32 95 64 127 96 */
745 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
746 /* 159 128 191 160 223 192 255 224 */
747 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
748 /* 287 256 319 288 351 320 383 352 */
749 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
750 /* 415 384 447 416 479 448 511 480 */
751 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
753 /* resvdDmaChannels */
754 /* 31 0 63 32 */
755 {0x00000000u, 0x00000000u},
757 /* resvdQdmaChannels */
758 /* 31 0 */
759 {0x00000000u},
761 /* resvdTccs */
762 /* 31 0 63 32 */
763 {0x00000000u, 0x00000000u},
764 },
765 },
766 };
770 /* End of File */