packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c

   1 /*
   2  * sample_tda2xx_int_reg.c
   3  *
   4  * Platform specific interrupt registration and un-registration routines.
   5  *
   6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  *
   9  *  Redistribution and use in source and binary forms, with or without
  10  *  modification, are permitted provided that the following conditions
  11  *  are met:
  12  *
  13  *    Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  *
  16  *    Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the
  19  *    distribution.
  20  *
  21  *    Neither the name of Texas Instruments Incorporated nor the names of
  22  *    its contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37 */
  38
  39 #include <ti/sysbios/knl/Semaphore.h>
  40 #include <ti/sysbios/hal/Hwi.h>
  41 #include <ti/sysbios/family/shared/vayu/IntXbar.h>
  42 #include <ti/sysbios/family/arm/a15/Mmu.h>
  43 #include <xdc/runtime/Error.h>
  44 #include <xdc/runtime/System.h>
  45
  46 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
  47
  48 /**
  49   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
  50   * (Not all TC error ISRs need to be registered, register only for the
  51   * available Transfer Controllers).
  52   */
  53 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
  54                                                 {
  55                                                 (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
  56                                                 (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
  57                                                 (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
  58                                                 (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
  59                                                 (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
  60                                                 (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
  61                                                 (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
  62                                                 (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
  63                                                 };
  64
  65 extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
  66 extern uint32_t ccErrorInt[];
  67 extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
  68 extern uint32_t numEdma3Tc[];
  69 extern uint32_t ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
  70 extern uint32_t ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
  71 extern uint32_t ccErrorIntXbarInstNo[];
  72 extern uint32_t ccErrEdmaXbarIndex[];
  73 extern uint32_t tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
  74 extern uint32_t tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
  75
  76 /**
  77  * Variables which will be used internally for referring the hardware interrupt
  78  * for various EDMA3 interrupts.
  79  */
  80 extern uint32_t hwIntXferComp[];
  81 extern uint32_t hwIntCcErr[];
  82 extern uint32_t hwIntTcErr[];
  83
  84 extern uint32_t dsp_num;
  85 /* This variable has to be used as an extern */
  86 uint32_t gpp_num = 0;
  87
  88 Hwi_Handle hwiCCXferCompInt;
  89 Hwi_Handle hwiCCErrInt;
  90 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
  91
  92 /* External Instance Specific Configuration Structure */
  93 extern EDMA3_DRV_GblXbarToChanConfigParams
  94                                                                 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
  95
  96 typedef struct  {
  97     volatile Uint32 TPCC_EVTMUX[32];
  98 } CSL_IntmuxRegs;
  99
 100 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 101
 102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
 103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
 104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 105
 106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
 107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
 108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 109
 110
 111 #define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127U)
 112 #define EDMA3_NUM_TCC                     (64U)
 113
 114 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
 115 /*
 116  * Forward decleration
 117  */
 118 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
 119                  uint32_t *chanNum,
 120                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
 121 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
 122                                   uint32_t chanNum);
 123
 124 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 125
 126 /**  To Register the ISRs with the underlying OS, if required. */
 127 void registerEdma3Interrupts (uint32_t edma3Id)
 128     {
 129     static UInt32 cookie = 0;
 130     uint32_t numTc = 0;
 131
 132     /*
 133      * Skip these interrupt xbar configuration.
 134      * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.
 135      */
 136     if (edma3Id != 2 && dsp_num != 1)
 137     {
 138         IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
 139         IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
 140         IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
 141         IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
 142     }
 143
 144     Hwi_Params hwiParams;
 145     Error_Block      eb;
 146
 147     /* Initialize the Error Block                                             */
 148     Error_init(&eb);
 149
 150     /* Disabling the global interrupts */
 151     cookie = Hwi_disable();
 152
 153     /* Initialize the HWI parameters with user specified values */
 154     Hwi_Params_init(&hwiParams);
 155
 156     /* argument for the ISR */
 157     hwiParams.arg = edma3Id;
 158         /* set the priority ID     */
 159         //hwiParams.priority = hwIntXferComp[edma3Id];
 160
 161     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
 162                                         ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
 163                                         (const Hwi_Params *) (&hwiParams),
 164                                         &eb);
 165     if (TRUE == Error_check(&eb))
 166     {
 167         System_printf("HWI Create Failed\n",Error_getCode(&eb));
 168     }
 169
 170     /* Initialize the HWI parameters with user specified values */
 171     Hwi_Params_init(&hwiParams);
 172     /* argument for the ISR */
 173     hwiParams.arg = edma3Id;
 174         /* set the priority ID     */
 175         //hwiParams.priority = hwIntCcErr[edma3Id];
 176
 177         hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
 178                 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
 179                 (const Hwi_Params *) (&hwiParams),
 180                 &eb);
 181
 182     if (TRUE == Error_check(&eb))
 183     {
 184         System_printf("HWI Create Failed\n",Error_getCode(&eb));
 185     }
 186
 187     while (numTc < numEdma3Tc[edma3Id])
 188             {
 189         /* Initialize the HWI parameters with user specified values */
 190         Hwi_Params_init(&hwiParams);
 191         /* argument for the ISR */
 192         hwiParams.arg = edma3Id;
 193         /* set the priority ID     */
 194         //hwiParams.priority = hwIntTcErr[edma3Id];
 195
 196         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
 197                     (ptrEdma3TcIsrHandler[numTc]),
 198                     (const Hwi_Params *) (&hwiParams),
 199                     &eb);
 200         if (TRUE == Error_check(&eb))
 201         {
 202             System_printf("HWI Create Failed\n",Error_getCode(&eb));
 203         }
 204         numTc++;
 205         }
 206
 207     Hwi_enableInterrupt(ccErrorInt[edma3Id]);
 208     Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
 209     numTc = 0;
 210     while (numTc < numEdma3Tc[edma3Id])
 211             {
 212         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
 213         numTc++;
 214         }
 215     /* Restore interrupts */
 216     Hwi_restore(cookie);
 217     }
 218
 219 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 220 void unregisterEdma3Interrupts (uint32_t edma3Id)
 221     {
 222         static UInt32 cookie = 0;
 223     uint32_t numTc = 0;
 224
 225     /* Disabling the global interrupts */
 226     cookie = Hwi_disable();
 227
 228     Hwi_delete(&hwiCCXferCompInt);
 229     Hwi_delete(&hwiCCErrInt);
 230     while (numTc < numEdma3Tc[edma3Id])
 231             {
 232         Hwi_delete(&hwiTCErrInt[numTc]);
 233         numTc++;
 234         }
 235     /* Restore interrupts */
 236     Hwi_restore(cookie);
 237     }
 238
 239 /**
 240  * \brief   sampleMapXbarEvtToChan
 241  *
 242  * This function reads from the sample configuration structure which specifies
 243  * cross bar events mapped to DMA channel.
 244  *
 245  * \return  EDMA3_DRV_SOK if success, else error code
 246  */
 247 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
 248                  uint32_t *chanNum,
 249                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
 250         {
 251     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
 252     uint32_t xbarEvtNum = 0;
 253     int32_t          edmaChanNum = 0;
 254
 255         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
 256                 (chanNum != NULL) &&
 257                 (edmaGblXbarConfig != NULL))
 258                 {
 259                 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
 260                 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
 261                 if (edmaChanNum != -1)
 262                         {
 263                         *chanNum = edmaChanNum;
 264                         edma3Result = EDMA3_DRV_SOK;
 265                         }
 266                 }
 267         return (edma3Result);
 268         }
 269
 270
 271 /**
 272  * \brief   sampleConfigScr
 273  *
 274  * This function configures control config registers for the cross bar events
 275  * mapped to the EDMA channel.
 276  *
 277  * \return  EDMA3_DRV_SOK if success, else error code
 278  */
 279 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
 280                                   uint32_t chanNum)
 281         {
 282     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
 283     uint32_t scrChanOffset = 0;
 284     uint32_t scrRegOffset  = 0;
 285     uint32_t xBarEvtNum    = 0;
 286     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
 287
 288
 289         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
 290                 (chanNum < EDMA3_NUM_TCC))
 291                 {
 292                 scrRegOffset = chanNum / 2;
 293                 scrChanOffset = chanNum - (scrRegOffset * 2);
 294                 xBarEvtNum = eventNum + 1;
 295
 296                 switch(scrChanOffset)
 297                         {
 298                         case 0:
 299                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
 300                                         (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
 301                                 break;
 302                         case 1:
 303                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
 304                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
 305                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
 306                                 break;
 307                         default:
 308                                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
 309                                 break;
 310                         }
 311                 }
 312         else
 313                 {
 314                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
 315                 }
 316         return edma3Result;
 317         }
 318
 319 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
 320                                    uint32_t edma3Id)
 321     {
 322     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
 323     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
 324                                 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
 325     if (hEdma != NULL)
 326         {
 327         retVal = EDMA3_DRV_initXbarEventMap(hEdma,
 328                                                                         sampleXbarToChanConfig,
 329                                                                         (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan,
 330                                                                         (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);
 331         }
 332
 333     return retVal;
 334     }
 335
 336 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
 337     {
 338     printf("memory Protection error");
 339     }