Misra C Fixes for dra72x
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_dra72x_arm_int_reg.c
1 /*
2  * sample_tda2xx_int_reg.c
3  *
4  * Platform specific interrupt registration and un-registration routines.
5  *
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  *
9  *  Redistribution and use in source and binary forms, with or without
10  *  modification, are permitted provided that the following conditions
11  *  are met:
12  *
13  *    Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  *
16  *    Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the
19  *    distribution.
20  *
21  *    Neither the name of Texas Instruments Incorporated nor the names of
22  *    its contributors may be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/hal/Hwi.h>
41 #include <ti/sysbios/family/shared/vayu/IntXbar.h>
42 #include <ti/sysbios/family/arm/a15/Mmu.h>
43 #include <xdc/runtime/Error.h>
44 #include <xdc/runtime/System.h>
46 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
48 /**
49   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
50   * (Not all TC error ISRs need to be registered, register only for the
51   * available Transfer Controllers).
52   */
53 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
54                                                 {
55                                                 &lisrEdma3TC0ErrHandler0,
56                                                 &lisrEdma3TC1ErrHandler0,
57                                                 &lisrEdma3TC2ErrHandler0,
58                                                 &lisrEdma3TC3ErrHandler0,
59                                                 &lisrEdma3TC4ErrHandler0,
60                                                 &lisrEdma3TC5ErrHandler0,
61                                                 &lisrEdma3TC6ErrHandler0,
62                                                 &lisrEdma3TC7ErrHandler0,
63                                                 };
65 extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
66 extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
67 extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
68 extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
69 extern uint32_t ccXferCompIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
70 extern uint32_t ccCompEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
71 extern uint32_t ccErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES];
72 extern uint32_t ccErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES];
73 extern uint32_t tcErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
74 extern uint32_t tcErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
76 /**
77  * Variables which will be used internally for referring the hardware interrupt
78  * for various EDMA3 interrupts.
79  */
80 extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
81 extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
82 extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
84 extern uint32_t dsp_num;
85 /* This variable has to be used as an extern */
86 uint32_t gpp_num = 0;
88 Hwi_Handle hwiCCXferCompInt;
89 Hwi_Handle hwiCCErrInt;
90 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
92 /* External Instance Specific Configuration Structure */
93 extern EDMA3_DRV_GblXbarToChanConfigParams 
94                                                                 sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
96 typedef struct  {
97     volatile Uint32 TPCC_EVTMUX[32];
98 } CSL_IntmuxRegs;
100 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
111 #define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127U)
112 #define EDMA3_NUM_TCC                     (64U)
114 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
115 /*
116  * Forward decleration
117  */
118 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
119                  uint32_t *chanNum,
120                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
121 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
122                                   uint32_t chanNum);
124 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
125                                    uint32_t edma3Id);
127 /**  To Register the ISRs with the underlying OS, if required. */
128 void registerEdma3Interrupts (uint32_t edma3Id);
129 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
130 void unregisterEdma3Interrupts (uint32_t edma3Id);
132 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
134 /**  To Register the ISRs with the underlying OS, if required. */
135 void registerEdma3Interrupts (uint32_t edma3Id)
136     {
137     static UInt32 cookie = 0;
138     uint32_t numTc = 0;
140     /*
141      * Skip these interrupt xbar configuration.
142      * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.
143      */
144     if ((edma3Id != 2U) && (dsp_num != 1U))
145     {
146         IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
147         IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
148         IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
149         IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
150     }
152     Hwi_Params hwiParams;
153     Error_Block      eb;
155     /* Initialize the Error Block                                             */
156     Error_init(&eb);
158     /* Disabling the global interrupts */
159     cookie = Hwi_disable();
161     /* Initialize the HWI parameters with user specified values */
162     Hwi_Params_init(&hwiParams);
164     /* argument for the ISR */
165     hwiParams.arg = edma3Id;
166         /* set the priority ID     */
167         /* hwiParams.priority = hwIntXferComp[edma3Id]; */
168     
169     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
170                                         ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
171                                         (const Hwi_Params *) (&hwiParams),
172                                         &eb);
173     if ((bool)TRUE == Error_check(&eb))
174     {
175         System_printf("HWI Create Failed\n",Error_getCode(&eb));
176     }
178     /* Initialize the HWI parameters with user specified values */
179     Hwi_Params_init(&hwiParams);
180     /* argument for the ISR */
181     hwiParams.arg = edma3Id;
182         /* set the priority ID     */
183         /* hwiParams.priority = hwIntCcErr[edma3Id]; */
184         
185         hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
186                 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
187                 (const Hwi_Params *) (&hwiParams),
188                 &eb);
190     if ((bool)TRUE == Error_check(&eb))
191     {
192         System_printf("HWI Create Failed\n",Error_getCode(&eb));
193     }
195     while (numTc < numEdma3Tc[edma3Id])
196             {
197         /* Initialize the HWI parameters with user specified values */
198         Hwi_Params_init(&hwiParams);
199         /* argument for the ISR */
200         hwiParams.arg = edma3Id;
201         /* set the priority ID     */
202         /* hwiParams.priority = hwIntTcErr[edma3Id]; */
203         
204         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
205                     (Hwi_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
206                     (const Hwi_Params *) (&hwiParams),
207                     &eb);
208         if ((bool)TRUE == Error_check(&eb))
209         {
210             System_printf("HWI Create Failed\n",Error_getCode(&eb));
211         }
212         numTc++;
213         }
215     Hwi_enableInterrupt(ccErrorInt[edma3Id]);
216     Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
217     numTc = 0;
218     while (numTc < numEdma3Tc[edma3Id])
219             {
220         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
221         numTc++;
222         }
223     /* Restore interrupts */
224     Hwi_restore(cookie);
225     }
227 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
228 void unregisterEdma3Interrupts (uint32_t edma3Id)
229     {
230         static UInt32 cookiee = 0;
231     uint32_t numTc = 0;
233     /* Disabling the global interrupts */
234     cookiee = Hwi_disable();
236     Hwi_delete(&hwiCCXferCompInt);
237     Hwi_delete(&hwiCCErrInt);
238     while (numTc < numEdma3Tc[edma3Id])
239             {
240         Hwi_delete(&hwiTCErrInt[numTc]);
241         numTc++;
242         }
243     /* Restore interrupts */
244     Hwi_restore(cookiee);
245     }
247 /**
248  * \brief   sampleMapXbarEvtToChan
249  *
250  * This function reads from the sample configuration structure which specifies
251  * cross bar events mapped to DMA channel.
252  *
253  * \return  EDMA3_DRV_SOK if success, else error code
254  */
255 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
256                  uint32_t *chanNum,
257                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
258         {
259     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
260     uint32_t xbarEvtNum = 0;
261     int32_t          edmaChanNum = 0;
263         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
264                 (chanNum != NULL) &&
265                 (edmaGblXbarConfig != NULL))
266                 {
267                 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
268                 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
269                 if (edmaChanNum != -1)
270                         {
271                         *chanNum = edmaChanNum;
272                         edma3Result = EDMA3_DRV_SOK;
273                         }
274                 }
275         return (edma3Result);
276         }
279 /**
280  * \brief   sampleConfigScr
281  *
282  * This function configures control config registers for the cross bar events
283  * mapped to the EDMA channel.
284  *
285  * \return  EDMA3_DRV_SOK if success, else error code
286  */
287 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
288                                   uint32_t chanNum)
289         {
290     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
291     uint32_t scrChanOffset = 0;
292     uint32_t scrRegOffset  = 0;
293     uint32_t xBarEvtNum    = 0;
294     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
297         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
298                 (chanNum < EDMA3_NUM_TCC))
299                 {
300                 scrRegOffset = chanNum / 2U;
301                 scrChanOffset = chanNum - (scrRegOffset * 2U);
302                 xBarEvtNum = eventNum + 1U;
303                 
304                 switch(scrChanOffset)
305                         {
306                         case 0:
307                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
308                                         (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
309                                 break;
310                         case 1U:
311                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
312                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
313                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
314                                 break;
315                         default:
316                                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
317                                 break;
318                         }
319                 }
320         else
321                 {
322                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
323                 }
324         return edma3Result;
325         }
327 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
328                                    uint32_t edma3Id)
329     {
330     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
331     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
332                                 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
333     uint32_t sampleMapXbarEvtToChanTemp = (uint32_t)&sampleMapXbarEvtToChan;
334     uint32_t sampleConfigScrTemp = (uint32_t)&sampleConfigScr;
335     if (hEdma != NULL)
336         {
337         retVal = EDMA3_DRV_initXbarEventMap(hEdma,
338                                                                         sampleXbarToChanConfig,
339                                                                         (EDMA3_DRV_mapXbarEvtToChan)sampleMapXbarEvtToChanTemp,
340                                                                         (EDMA3_DRV_xbarConfigScr)sampleConfigScrTemp);
341         }
343     return retVal;
344     }
346 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
347     {
348 #ifdef EDMA3_DRV_DEBUG
349     /*  Added to fix Misra C error */
350     printf("memory Protection error");
351 #endif
352     }