[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_dra72x_cfg.c
1 /*
2 * sample_dra72x_cfg.c
3 *
4 * SoC specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
42 #ifdef BUILD_DRA72X_IPU
43 #include <ti/sysbios/family/arm/ducati/Core.h>
45 #endif
47 /* Number of EDMA3 controllers present in the system */
48 #define NUM_EDMA3_INSTANCES 2U
49 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
51 /* Number of DSPs present in the system */
52 #define NUM_DSPS 1U
53 const uint32_t numDsps = NUM_DSPS;
55 /* Determine the processor id by reading DNUM register. */
56 /* Statically allocate the region numbers with cores. */
57 volatile int32_t myCoreNum;
58 #define PID0_ADDRESS 0xE00FFFE0U
59 #define CORE_ID_C0 0x0
60 #define CORE_ID_C1 0x1
62 #ifdef BUILD_DRA72X_MPU
63 void __inline readProcFeatureReg(void);
64 void __inline readProcFeatureReg(void)
65 {
66 asm (" push {r0-r2} \n\t"
67 " MRC p15, 0, r0, c0, c0, 5\n\t"
68 " LDR r1, =myCoreNum\n\t"
69 " STR r0, [r1]\n\t"
70 " pop {r0-r2}\n\t");
71 }
72 #endif
74 int8_t* getGlobalAddr(int8_t* addr);
76 uint16_t determineProcId(void);
78 uint16_t isGblConfigRequired(uint32_t dspNum);
80 uint16_t determineProcId(void)
81 {
82 uint16_t regionNo = (uint16_t)numEdma3Instances;
83 #ifdef BUILD_DRA72X_DSP
84 extern __cregister volatile uint32_t DNUM;
85 #endif
87 myCoreNum = (int32_t)numDsps;
89 #ifdef BUILD_DRA72X_MPU
90 readProcFeatureReg();
91 /* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */
92 regionNo = 0U;
93 if(((uint32_t)myCoreNum & 0x03U) == 1U)
94 {
95 regionNo = 1U;
96 }
97 #elif defined(BUILD_DRA72X_IPU)
98 myCoreNum = (*(volatile uint32_t *)(PID0_ADDRESS));
99 if(Core_getIpuId() == 1U){
100 if(myCoreNum == (int32_t)CORE_ID_C0)
101 {
102 regionNo = 4U;
103 }
104 else if (myCoreNum == (int32_t)CORE_ID_C1)
105 {
106 regionNo = 5U;
107 }
108 else
109 {
110 /* Nothing to be done here*/
111 }
112 }
113 if(Core_getIpuId() == 2U){
114 if(myCoreNum == (int32_t)CORE_ID_C0)
115 {
116 regionNo = 6U;
117 }
118 else if (myCoreNum == (int32_t)CORE_ID_C1)
119 {
120 regionNo = 7U;
121 }
122 else
123 {
124 /* Nothing to be done here*/
125 }
126 }
127 #elif defined(BUILD_DRA72X_DSP)
128 regionNo = 2U;
129 #endif
130 return regionNo;
131 }
133 int8_t* getGlobalAddr(int8_t* addr)
134 {
135 return (addr); /* The address is already a global address */
136 }
137 uint16_t isGblConfigRequired(uint32_t dspNum)
138 {
139 (void) dspNum;
140 return 1U;
141 }
143 /* Semaphore handles */
144 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
146 /** Number of PaRAM Sets available */
147 #define EDMA3_NUM_PARAMSET (512U)
149 /** Number of TCCS available */
150 #define EDMA3_NUM_TCC (64U)
152 /** Number of DMA Channels available */
153 #define EDMA3_NUM_DMA_CHANNELS (64U)
155 /** Number of QDMA Channels available */
156 #define EDMA3_NUM_QDMA_CHANNELS (8U)
158 /** Number of Event Queues available */
159 #define EDMA3_NUM_EVTQUE (4U)
161 /** Number of Transfer Controllers available */
162 #define EDMA3_NUM_TC (2U)
164 /** Number of Regions */
165 #define EDMA3_NUM_REGIONS (8U)
167 /** Interrupt no. for Transfer Completion */
168 #define EDMA3_CC_XFER_COMPLETION_INT_A15 (66U)
169 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38U)
170 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34U)
171 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33U)
173 /** Based on the interrupt number to be mapped define the XBAR instance number */
174 #define COMPLETION_INT_A15_XBAR_INST_NO (29U)
175 #define COMPLETION_INT_DSP_XBAR_INST_NO (7U)
176 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12U)
177 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11U)
179 /** Interrupt no. for CC Error */
180 #define EDMA3_CC_ERROR_INT_A15 (67U)
181 #define EDMA3_CC_ERROR_INT_DSP (39U)
182 #define EDMA3_CC_ERROR_INT_IPU (35U)
184 /** Based on the interrupt number to be mapped define the XBAR instance number */
185 #define CC_ERROR_INT_A15_XBAR_INST_NO (30U)
186 #define CC_ERROR_INT_DSP_XBAR_INST_NO (8U)
187 #define CC_ERROR_INT_IPU_XBAR_INST_NO (13U)
189 /** Interrupt no. for TCs Error */
190 #define EDMA3_TC0_ERROR_INT_A15 (68U)
191 #define EDMA3_TC0_ERROR_INT_DSP (40U)
192 #define EDMA3_TC0_ERROR_INT_IPU (36U)
193 #define EDMA3_TC1_ERROR_INT_A15 (69U)
194 #define EDMA3_TC1_ERROR_INT_DSP (41U)
195 #define EDMA3_TC1_ERROR_INT_IPU (37U)
197 /** Based on the interrupt number to be mapped define the XBAR instance number */
198 #define TC0_ERROR_INT_A15_XBAR_INST_NO (31U)
199 #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9U)
200 #define TC0_ERROR_INT_IPU_XBAR_INST_NO (14U)
201 #define TC1_ERROR_INT_A15_XBAR_INST_NO (32U)
202 #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10U)
203 #define TC1_ERROR_INT_IPU_XBAR_INST_NO (15U)
205 #ifdef BUILD_DRA72X_MPU
206 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_A15)
207 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_A15)
208 #define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_A15_XBAR_INST_NO)
209 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_A15)
210 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_A15)
211 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)
212 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)
214 #elif defined BUILD_DRA72X_DSP
215 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_DSP)
216 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_DSP)
217 #define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_DSP_XBAR_INST_NO)
218 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_DSP)
219 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_DSP)
220 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_DSP_XBAR_INST_NO)
221 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_DSP_XBAR_INST_NO)
223 #elif defined BUILD_DRA72X_IPU
224 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)
225 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_IPU)
226 #define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_IPU_XBAR_INST_NO)
227 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_IPU)
228 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_IPU)
229 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_IPU_XBAR_INST_NO)
230 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_IPU_XBAR_INST_NO)
232 #else
233 #define EDMA3_CC_XFER_COMPLETION_INT (0U)
234 #define EDMA3_CC_ERROR_INT (0U)
235 #define CC_ERROR_INT_XBAR_INST_NO (0U)
236 #define EDMA3_TC0_ERROR_INT (0U)
237 #define EDMA3_TC1_ERROR_INT (0U)
238 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)
239 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)
240 #endif
242 #define EDMA3_TC2_ERROR_INT (0U)
243 #define EDMA3_TC3_ERROR_INT (0U)
244 #define EDMA3_TC4_ERROR_INT (0U)
245 #define EDMA3_TC5_ERROR_INT (0U)
246 #define EDMA3_TC6_ERROR_INT (0U)
247 #define EDMA3_TC7_ERROR_INT (0U)
249 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19U)
250 #define DSP1_EDMA3_CC_ERROR_INT (27U)
251 #define DSP1_EDMA3_TC0_ERROR_INT (28U)
252 #define DSP1_EDMA3_TC1_ERROR_INT (29U)
254 /** XBAR interrupt source index numbers for EDMA interrupts */
255 #define XBAR_EDMA_TPCC_IRQ_REGION0 (361U)
256 #define XBAR_EDMA_TPCC_IRQ_REGION1 (362U)
257 #define XBAR_EDMA_TPCC_IRQ_REGION2 (363U)
258 #define XBAR_EDMA_TPCC_IRQ_REGION3 (364U)
259 #define XBAR_EDMA_TPCC_IRQ_REGION4 (365U)
260 #define XBAR_EDMA_TPCC_IRQ_REGION5 (366U)
261 #define XBAR_EDMA_TPCC_IRQ_REGION6 (367U)
262 #define XBAR_EDMA_TPCC_IRQ_REGION7 (368U)
264 #define XBAR_EDMA_TPCC_IRQ_ERR (359U)
265 #define XBAR_EDMA_TC0_IRQ_ERR (370U)
266 #define XBAR_EDMA_TC1_IRQ_ERR (371U)
268 /**
269 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
270 * ECM events (SoC specific). These ECM events come
271 * under ECM block XXX (handling those specific ECM events). Normally, block
272 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
273 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
274 * is mapped to a specific HWI_INT YYY in the tcf file.
275 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
276 * to transfer completion interrupt.
277 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
278 * to CC error interrupts.
279 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
280 * to TC error interrupts.
281 */
282 /* EDMA 0 */
284 #define EDMA3_HWI_INT_XFER_COMP (7U)
285 #define EDMA3_HWI_INT_CC_ERR (7U)
286 #define EDMA3_HWI_INT_TC0_ERR (10U)
287 #define EDMA3_HWI_INT_TC1_ERR (10U)
288 #define EDMA3_HWI_INT_TC2_ERR (10U)
289 #define EDMA3_HWI_INT_TC3_ERR (10U)
291 /**
292 * \brief Mapping of DMA channels 0-31 to Hardware Events from
293 * various peripherals, which use EDMA for data transfer.
294 * All channels need not be mapped, some can be free also.
295 * 1: Mapped
296 * 0: Not mapped (channel available)
297 *
298 * This mapping will be used to allocate DMA channels when user passes
299 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
300 * copy). The same mapping is used to allocate the TCC when user passes
301 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
302 *
303 * For Vayu Since the xbar can be used to map event to any EDMA channel,
304 * If the application is assigning events to other channel this variable
305 * should be modified
306 *
307 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
308 */
309 /* 31 0 */
310 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA (0x3FC0C06EU) /* TBD */
311 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFU) /* TBD */
313 /**
314 * \brief Mapping of DMA channels 32-63 to Hardware Events from
315 * various peripherals, which use EDMA for data transfer.
316 * All channels need not be mapped, some can be free also.
317 * 1: Mapped
318 * 0: Not mapped (channel available)
319 *
320 * This mapping will be used to allocate DMA channels when user passes
321 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
322 * copy). The same mapping is used to allocate the TCC when user passes
323 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
324 *
325 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
326 */
327 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA (0xF3FFFFFCU) /* TBD */
328 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000U) /* TBD */
331 /* Variable which will be used internally for referring number of Event Queues*/
332 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
333 EDMA3_NUM_EVTQUE,
334 EDMA3_NUM_EVTQUE
335 };
337 /* Variable which will be used internally for referring number of TCs. */
338 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {
339 EDMA3_NUM_TC,
340 EDMA3_NUM_TC
341 };
343 /**
344 * Variable which will be used internally for referring transfer completion
345 * interrupt.
346 */
347 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
348 {
349 /* EDMA3 INSTANCE# 0 */
350 {
351 EDMA3_CC_XFER_COMPLETION_INT_A15,
352 EDMA3_CC_XFER_COMPLETION_INT_A15,
353 EDMA3_CC_XFER_COMPLETION_INT_DSP,
354 0U,
355 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
356 EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,
357 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
358 EDMA3_CC_XFER_COMPLETION_INT_IPU_C1
359 },
360 /* EDMA3 INSTANCE# 1 */
361 {
362 0U,
363 0U,
364 DSP1_EDMA3_CC_XFER_COMPLETION_INT,
365 0U,
366 0U,
367 0U,
368 0U,
369 0U
370 }
371 };
372 /** These are the Xbar instance numbers corresponding to interrupt numbers */
373 uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
374 {
375 /* EDMA3 INSTANCE# 0 */
376 {
377 COMPLETION_INT_A15_XBAR_INST_NO,
378 COMPLETION_INT_A15_XBAR_INST_NO,
379 COMPLETION_INT_DSP_XBAR_INST_NO,
380 0U,
381 COMPLETION_INT_IPU_C0_XBAR_INST_NO,
382 COMPLETION_INT_IPU_C1_XBAR_INST_NO,
383 COMPLETION_INT_IPU_C0_XBAR_INST_NO,
384 COMPLETION_INT_IPU_C1_XBAR_INST_NO,
385 },
386 /* EDMA3 INSTANCE# 1 */
387 {
388 0U,
389 0U,
390 0U,
391 0U,
392 0U,
393 0U,
394 0U,
395 0U
396 }
397 };
399 /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */
400 uint32_t ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
401 {
402 /* EDMA3 INSTANCE# 0 */
403 {
404 XBAR_EDMA_TPCC_IRQ_REGION0,
405 XBAR_EDMA_TPCC_IRQ_REGION1,
406 XBAR_EDMA_TPCC_IRQ_REGION2,
407 XBAR_EDMA_TPCC_IRQ_REGION3,
408 XBAR_EDMA_TPCC_IRQ_REGION4,
409 XBAR_EDMA_TPCC_IRQ_REGION5,
410 XBAR_EDMA_TPCC_IRQ_REGION6,
411 XBAR_EDMA_TPCC_IRQ_REGION7
412 },
413 /* EDMA3 INSTANCE# 1 */
414 {
415 XBAR_EDMA_TPCC_IRQ_REGION0,
416 XBAR_EDMA_TPCC_IRQ_REGION1,
417 XBAR_EDMA_TPCC_IRQ_REGION2,
418 XBAR_EDMA_TPCC_IRQ_REGION3,
419 XBAR_EDMA_TPCC_IRQ_REGION4,
420 XBAR_EDMA_TPCC_IRQ_REGION5,
421 XBAR_EDMA_TPCC_IRQ_REGION6,
422 XBAR_EDMA_TPCC_IRQ_REGION7
423 }
424 };
426 /**
427 * Variable which will be used internally for referring channel controller's
428 * error interrupt.
429 */
430 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] =
431 {
432 EDMA3_CC_ERROR_INT,
433 DSP1_EDMA3_CC_ERROR_INT
434 };
435 uint32_t ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =
436 {
437 CC_ERROR_INT_XBAR_INST_NO,
438 CC_ERROR_INT_XBAR_INST_NO
439 };
440 uint32_t ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
441 {
442 XBAR_EDMA_TPCC_IRQ_ERR,
443 XBAR_EDMA_TPCC_IRQ_ERR
444 };
446 /**
447 * Variable which will be used internally for referring transfer controllers'
448 * error interrupts.
449 */
450 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
451 {
452 /* EDMA3 INSTANCE# 0 */
453 {
454 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
455 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
456 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
457 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
458 },
459 /* EDMA3 INSTANCE# 1 */
460 {
461 DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,
462 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
463 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
464 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
465 }
466 };
467 uint32_t tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
468 {
469 /* EDMA3 INSTANCE# 0 */
470 {
471 TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
472 0U, 0U,
473 0U, 0U,
474 0U, 0U,
475 },
476 /* EDMA3 INSTANCE# 1 */
477 {
478 TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
479 0U, 0U,
480 0U, 0U,
481 0U, 0U,
482 }
483 };
485 uint32_t tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
486 {
487 /* EDMA3 INSTANCE# 0 */
488 {
489 XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
490 0U, 0U,
491 0U, 0U, 0U, 0U,
492 },
493 /* EDMA3 INSTANCE# 1 */
494 {
495 XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
496 0U, 0U,
497 0U, 0U, 0U, 0U,
498 }
499 };
502 /**
503 * Variables which will be used internally for referring the hardware interrupt
504 * for various EDMA3 interrupts.
505 */
506 uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =
507 {
508 EDMA3_HWI_INT_XFER_COMP,
509 EDMA3_HWI_INT_XFER_COMP
510 };
512 uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =
513 {
514 EDMA3_HWI_INT_CC_ERR,
515 EDMA3_HWI_INT_CC_ERR
516 };
518 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
519 {
520 /* EDMA3 INSTANCE# 0 */
521 {
522 EDMA3_HWI_INT_TC0_ERR,
523 EDMA3_HWI_INT_TC1_ERR,
524 EDMA3_HWI_INT_TC2_ERR,
525 EDMA3_HWI_INT_TC3_ERR,
526 0,
527 0,
528 0,
529 0
530 },
531 /* EDMA3 INSTANCE# 1 */
532 {
533 EDMA3_HWI_INT_TC0_ERR,
534 EDMA3_HWI_INT_TC1_ERR,
535 EDMA3_HWI_INT_TC2_ERR,
536 EDMA3_HWI_INT_TC3_ERR,
537 0,
538 0,
539 0,
540 0
541 }
542 };
544 /**
545 * \brief Base address as seen from the different cores may be different
546 * And is defined based on the core
547 */
548 #if ((defined BUILD_DRA72X_MPU) || (defined BUILD_DRA72X_DSP))
549 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))
550 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))
551 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))
552 #elif (defined BUILD_DRA72X_IPU)
553 #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))
554 #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))
555 #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))
556 #else
557 #define EDMA3_CC_BASE_ADDR ((void *)(0x0))
558 #define EDMA3_TC0_BASE_ADDR ((void *)(0x0))
559 #define EDMA3_TC1_BASE_ADDR ((void *)(0x0))
560 #endif
562 #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000))
563 #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000))
564 #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000))
566 /* Driver Object Initialization Configuration */
567 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
568 {
569 {
570 /* EDMA3 INSTANCE# 0 */
571 /** Total number of DMA Channels supported by the EDMA3 Controller */
572 EDMA3_NUM_DMA_CHANNELS,
573 /** Total number of QDMA Channels supported by the EDMA3 Controller */
574 EDMA3_NUM_QDMA_CHANNELS,
575 /** Total number of TCCs supported by the EDMA3 Controller */
576 EDMA3_NUM_TCC,
577 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
578 EDMA3_NUM_PARAMSET,
579 /** Total number of Event Queues in the EDMA3 Controller */
580 EDMA3_NUM_EVTQUE,
581 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
582 EDMA3_NUM_TC,
583 /** Number of Regions on this EDMA3 controller */
584 EDMA3_NUM_REGIONS,
586 /**
587 * \brief Channel mapping existence
588 * A value of 0 (No channel mapping) implies that there is fixed association
589 * for a channel number to a parameter entry number or, in other words,
590 * PaRAM entry n corresponds to channel n.
591 */
592 1U,
594 /** Existence of memory protection feature */
595 0U,
597 /** Global Register Region of CC Registers */
598 EDMA3_CC_BASE_ADDR,
599 /** Transfer Controller (TC) Registers */
600 {
601 EDMA3_TC0_BASE_ADDR,
602 EDMA3_TC1_BASE_ADDR,
603 (void *)NULL,
604 (void *)NULL,
605 (void *)NULL,
606 (void *)NULL,
607 (void *)NULL,
608 (void *)NULL
609 },
610 /** Interrupt no. for Transfer Completion */
611 EDMA3_CC_XFER_COMPLETION_INT,
612 /** Interrupt no. for CC Error */
613 EDMA3_CC_ERROR_INT,
614 /** Interrupt no. for TCs Error */
615 {
616 EDMA3_TC0_ERROR_INT,
617 EDMA3_TC1_ERROR_INT,
618 EDMA3_TC2_ERROR_INT,
619 EDMA3_TC3_ERROR_INT,
620 EDMA3_TC4_ERROR_INT,
621 EDMA3_TC5_ERROR_INT,
622 EDMA3_TC6_ERROR_INT,
623 EDMA3_TC7_ERROR_INT
624 },
626 /**
627 * \brief EDMA3 TC priority setting
628 *
629 * User can program the priority of the Event Queues
630 * at a system-wide level. This means that the user can set the
631 * priority of an IO initiated by either of the TCs (Transfer Controllers)
632 * relative to IO initiated by the other bus masters on the
633 * device (ARM, DSP, USB, etc)
634 */
635 {
636 0U,
637 1U,
638 0U,
639 0U,
640 0U,
641 0U,
642 0U,
643 0U
644 },
645 /**
646 * \brief To Configure the Threshold level of number of events
647 * that can be queued up in the Event queues. EDMA3CC error register
648 * (CCERR) will indicate whether or not at any instant of time the
649 * number of events queued up in any of the event queues exceeds
650 * or equals the threshold/watermark value that is set
651 * in the queue watermark threshold register (QWMTHRA).
652 */
653 {
654 16U,
655 16U,
656 0U,
657 0U,
658 0U,
659 0U,
660 0U,
661 0U
662 },
664 /**
665 * \brief To Configure the Default Burst Size (DBS) of TCs.
666 * An optimally-sized command is defined by the transfer controller
667 * default burst size (DBS). Different TCs can have different
668 * DBS values. It is defined in Bytes.
669 */
670 {
671 16U,
672 16U,
673 0U,
674 0U,
675 0U,
676 0U,
677 0U,
678 0U
679 },
681 /**
682 * \brief Mapping from each DMA channel to a Parameter RAM set,
683 * if it exists, otherwise of no use.
684 */
685 {
686 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
687 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
688 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
689 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
690 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
691 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
692 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
693 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
694 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
695 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
696 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
697 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
698 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
699 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
700 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
701 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
702 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
703 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
704 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
705 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
706 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
707 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
708 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
709 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
710 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
711 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
712 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
713 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
714 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
715 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
716 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
717 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
718 },
720 /**
721 * \brief Mapping from each DMA channel to a TCC. This specific
722 * TCC code will be returned when the transfer is completed
723 * on the mapped channel.
724 */
725 {
726 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
727 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
728 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
729 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
730 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
731 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
732 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
733 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
734 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
735 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
736 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
737 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
738 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
739 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
740 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
741 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
742 },
744 /**
745 * \brief Mapping of DMA channels to Hardware Events from
746 * various peripherals, which use EDMA for data transfer.
747 * All channels need not be mapped, some can be free also.
748 */
749 {
750 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,
751 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA
752 }
753 },
754 {
755 /* EDMA3 INSTANCE# 1 */
756 /** Total number of DMA Channels supported by the EDMA3 Controller */
757 EDMA3_NUM_DMA_CHANNELS,
758 /** Total number of QDMA Channels supported by the EDMA3 Controller */
759 EDMA3_NUM_QDMA_CHANNELS,
760 /** Total number of TCCs supported by the EDMA3 Controller */
761 EDMA3_NUM_TCC,
762 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
763 EDMA3_NUM_PARAMSET,
764 /** Total number of Event Queues in the EDMA3 Controller */
765 EDMA3_NUM_EVTQUE,
766 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
767 EDMA3_NUM_TC,
768 /** Number of Regions on this EDMA3 controller */
769 EDMA3_NUM_REGIONS,
771 /**
772 * \brief Channel mapping existence
773 * A value of 0 (No channel mapping) implies that there is fixed association
774 * for a channel number to a parameter entry number or, in other words,
775 * PaRAM entry n corresponds to channel n.
776 */
777 1U,
779 /** Existence of memory protection feature */
780 0U,
782 /** Global Register Region of CC Registers */
783 DSP1_EDMA3_CC_BASE_ADDR,
784 /** Transfer Controller (TC) Registers */
785 {
786 DSP1_EDMA3_TC0_BASE_ADDR,
787 DSP1_EDMA3_TC1_BASE_ADDR,
788 (void *)NULL,
789 (void *)NULL,
790 (void *)NULL,
791 (void *)NULL,
792 (void *)NULL,
793 (void *)NULL
794 },
795 /** Interrupt no. for Transfer Completion */
796 DSP1_EDMA3_CC_XFER_COMPLETION_INT,
797 /** Interrupt no. for CC Error */
798 DSP1_EDMA3_CC_ERROR_INT,
799 /** Interrupt no. for TCs Error */
800 {
801 DSP1_EDMA3_TC0_ERROR_INT,
802 DSP1_EDMA3_TC1_ERROR_INT,
803 EDMA3_TC2_ERROR_INT,
804 EDMA3_TC3_ERROR_INT,
805 EDMA3_TC4_ERROR_INT,
806 EDMA3_TC5_ERROR_INT,
807 EDMA3_TC6_ERROR_INT,
808 EDMA3_TC7_ERROR_INT
809 },
811 /**
812 * \brief EDMA3 TC priority setting
813 *
814 * User can program the priority of the Event Queues
815 * at a system-wide level. This means that the user can set the
816 * priority of an IO initiated by either of the TCs (Transfer Controllers)
817 * relative to IO initiated by the other bus masters on the
818 * device (ARM, DSP, USB, etc)
819 */
820 {
821 0U,
822 1U,
823 0U,
824 0U,
825 0U,
826 0U,
827 0U,
828 0U
829 },
830 /**
831 * \brief To Configure the Threshold level of number of events
832 * that can be queued up in the Event queues. EDMA3CC error register
833 * (CCERR) will indicate whether or not at any instant of time the
834 * number of events queued up in any of the event queues exceeds
835 * or equals the threshold/watermark value that is set
836 * in the queue watermark threshold register (QWMTHRA).
837 */
838 {
839 16U,
840 16U,
841 0U,
842 0U,
843 0U,
844 0U,
845 0U,
846 0U
847 },
849 /**
850 * \brief To Configure the Default Burst Size (DBS) of TCs.
851 * An optimally-sized command is defined by the transfer controller
852 * default burst size (DBS). Different TCs can have different
853 * DBS values. It is defined in Bytes.
854 */
855 {
856 16U,
857 16U,
858 0U,
859 0U,
860 0U,
861 0U,
862 0U,
863 0U
864 },
866 /**
867 * \brief Mapping from each DMA channel to a Parameter RAM set,
868 * if it exists, otherwise of no use.
869 */
870 {
871 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
872 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
873 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
874 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
875 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
876 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
877 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
878 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
879 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
880 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
881 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
882 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
883 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
884 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
885 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
886 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
887 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
888 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
889 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
890 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
891 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
892 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
893 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
894 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
895 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
896 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
897 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
898 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
899 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
900 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
901 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
902 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
903 },
905 /**
906 * \brief Mapping from each DMA channel to a TCC. This specific
907 * TCC code will be returned when the transfer is completed
908 * on the mapped channel.
909 */
910 {
911 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
912 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
913 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
914 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
915 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
916 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
917 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
918 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
919 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
920 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
921 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
922 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
923 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
924 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
925 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
926 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
927 },
929 /**
930 * \brief Mapping of DMA channels to Hardware Events from
931 * various peripherals, which use EDMA for data transfer.
932 * All channels need not be mapped, some can be free also.
933 */
934 {
935 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,
936 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA
937 }
938 }
939 };
941 /**
942 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
943 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
944 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
945 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
946 *
947 * Only Resources owned by a perticular core are allocated by Driver
948 * Reserved resources are not allocated if requested for any available resource
949 */
951 /* Driver Instance Initialization Configuration */
952 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
953 {
954 /* EDMA3 INSTANCE# 0 */
955 {
956 /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/
957 {
958 /* ownPaRAMSets */
959 /* 31 0 63 32 95 64 127 96 */
960 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
961 /* 159 128 191 160 223 192 255 224 */
962 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
963 /* 287 256 319 288 351 320 383 352 */
964 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
965 /* 415 384 447 416 479 448 511 480 */
966 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
968 /* ownDmaChannels */
969 /* 31 0 63 32 */
970 {0xFFFFFFFFU, 0xFFFFFFFFU},
972 /* ownQdmaChannels */
973 /* 31 0 */
974 {0x000000FFU},
976 /* ownTccs */
977 /* 31 0 63 32 */
978 {0xFFFFFFFFU, 0xFFFFFFFFU},
980 /* resvdPaRAMSets */
981 /* 31 0 63 32 95 64 127 96 */
982 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
983 /* 159 128 191 160 223 192 255 224 */
984 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
985 /* 287 256 319 288 351 320 383 352 */
986 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
987 /* 415 384 447 416 479 448 511 480 */
988 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
990 /* resvdDmaChannels */
991 /* 31 0 63 32 */
992 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
994 /* resvdQdmaChannels */
995 /* 31 0 */
996 {0x00U},
998 /* resvdTccs */
999 /* 31 0 63 32 */
1000 {0x00U, 0x00U},
1001 },
1003 /* Resources owned/reserved by region 1 (Associated to MPU core 1) */
1004 {
1005 /* ownPaRAMSets */
1006 /* 31 0 63 32 95 64 127 96 */
1007 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1008 /* 159 128 191 160 223 192 255 224 */
1009 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1010 /* 287 256 319 288 351 320 383 352 */
1011 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1012 /* 415 384 447 416 479 448 511 480 */
1013 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1015 /* ownDmaChannels */
1016 /* 31 0 63 32 */
1017 {0xFFFFFFFFU, 0xFFFFFFFFU},
1019 /* ownQdmaChannels */
1020 /* 31 0 */
1021 {0x000000FFU},
1023 /* ownTccs */
1024 /* 31 0 63 32 */
1025 {0xFFFFFFFFU, 0xFFFFFFFFU},
1027 /* resvdPaRAMSets */
1028 /* 31 0 63 32 95 64 127 96 */
1029 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1030 /* 159 128 191 160 223 192 255 224 */
1031 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1032 /* 287 256 319 288 351 320 383 352 */
1033 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1034 /* 415 384 447 416 479 448 511 480 */
1035 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1037 /* resvdDmaChannels */
1038 /* 31 0 63 32 */
1039 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1041 /* resvdQdmaChannels */
1042 /* 31 0 */
1043 {0x00U},
1045 /* resvdTccs */
1046 /* 31 0 63 32 */
1047 {0x00U, 0x00U},
1048 },
1050 /* Resources owned/reserved by region 2 (Associated to DSP1)*/
1051 {
1052 /* ownPaRAMSets */
1053 /* 31 0 63 32 95 64 127 96 */
1054 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1055 /* 159 128 191 160 223 192 255 224 */
1056 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1057 /* 287 256 319 288 351 320 383 352 */
1058 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1059 /* 415 384 447 416 479 448 511 480 */
1060 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1062 /* ownDmaChannels */
1063 /* 31 0 63 32 */
1064 {0xFFFFFFFFU, 0xFFFFFFFFU},
1066 /* ownQdmaChannels */
1067 /* 31 0 */
1068 {0x000000FFU},
1070 /* ownTccs */
1071 /* 31 0 63 32 */
1072 {0xFFFFFFFFU, 0xFFFFFFFFU},
1074 /* resvdPaRAMSets */
1075 /* 31 0 63 32 95 64 127 96 */
1076 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1077 /* 159 128 191 160 223 192 255 224 */
1078 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1079 /* 287 256 319 288 351 320 383 352 */
1080 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1081 /* 415 384 447 416 479 448 511 480 */
1082 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1084 /* resvdDmaChannels */
1085 /* 31 0 63 32 */
1086 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1088 /* resvdQdmaChannels */
1089 /* 31 0 */
1090 {0x00U},
1092 /* resvdTccs */
1093 /* 31 0 63 32 */
1094 {0x00U, 0x00U},
1095 },
1097 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
1098 {
1099 /* ownPaRAMSets */
1100 /* 31 0 63 32 95 64 127 96 */
1101 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1102 /* 159 128 191 160 223 192 255 224 */
1103 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1104 /* 287 256 319 288 351 320 383 352 */
1105 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1106 /* 415 384 447 416 479 448 511 480 */
1107 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1109 /* ownDmaChannels */
1110 /* 31 0 63 32 */
1111 {0x00000000U, 0x00000000U},
1113 /* ownQdmaChannels */
1114 /* 31 0 */
1115 {0x00000000U},
1117 /* ownTccs */
1118 /* 31 0 63 32 */
1119 {0x00000000U, 0x00000000U},
1121 /* resvdPaRAMSets */
1122 /* 31 0 63 32 95 64 127 96 */
1123 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1124 /* 159 128 191 160 223 192 255 224 */
1125 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1126 /* 287 256 319 288 351 320 383 352 */
1127 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1128 /* 415 384 447 416 479 448 511 480 */
1129 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1131 /* resvdDmaChannels */
1132 /* 31 0 63 32 */
1133 {0x00000000U, 0x00000000U},
1135 /* resvdQdmaChannels */
1136 /* 31 0 */
1137 {0x00000000U},
1139 /* resvdTccs */
1140 /* 31 0 63 32 */
1141 {0x00000000U, 0x00000000U},
1142 },
1144 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/
1145 {
1146 /* ownPaRAMSets */
1147 /* 31 0 63 32 95 64 127 96 */
1148 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1149 /* 159 128 191 160 223 192 255 224 */
1150 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1151 /* 287 256 319 288 351 320 383 352 */
1152 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1153 /* 415 384 447 416 479 448 511 480 */
1154 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1156 /* ownDmaChannels */
1157 /* 31 0 63 32 */
1158 {0xFFFFFFFFU, 0xFFFFFFFFU},
1160 /* ownQdmaChannels */
1161 /* 31 0 */
1162 {0x000000FFU},
1164 /* ownTccs */
1165 /* 31 0 63 32 */
1166 {0xFFFFFFFFU, 0xFFFFFFFFU},
1168 /* resvdPaRAMSets */
1169 /* 31 0 63 32 95 64 127 96 */
1170 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1171 /* 159 128 191 160 223 192 255 224 */
1172 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1173 /* 287 256 319 288 351 320 383 352 */
1174 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1175 /* 415 384 447 416 479 448 511 480 */
1176 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1178 /* resvdDmaChannels */
1179 /* 31 0 63 32 */
1180 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1182 /* resvdQdmaChannels */
1183 /* 31 0 */
1184 {0x00U},
1186 /* resvdTccs */
1187 /* 31 0 63 32 */
1188 {0x00U, 0x00U},
1189 },
1191 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/
1192 {
1193 /* ownPaRAMSets */
1194 /* 31 0 63 32 95 64 127 96 */
1195 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1196 /* 159 128 191 160 223 192 255 224 */
1197 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1198 /* 287 256 319 288 351 320 383 352 */
1199 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1200 /* 415 384 447 416 479 448 511 480 */
1201 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1203 /* ownDmaChannels */
1204 /* 31 0 63 32 */
1205 {0xFFFFFFFFU, 0xFFFFFFFFU},
1207 /* ownQdmaChannels */
1208 /* 31 0 */
1209 {0x000000FFU},
1211 /* ownTccs */
1212 /* 31 0 63 32 */
1213 {0xFFFFFFFFU, 0xFFFFFFFFU},
1215 /* resvdPaRAMSets */
1216 /* 31 0 63 32 95 64 127 96 */
1217 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1218 /* 159 128 191 160 223 192 255 224 */
1219 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1220 /* 287 256 319 288 351 320 383 352 */
1221 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1222 /* 415 384 447 416 479 448 511 480 */
1223 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1225 /* resvdDmaChannels */
1226 /* 31 0 63 32 */
1227 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1229 /* resvdQdmaChannels */
1230 /* 31 0 */
1231 {0x00U},
1233 /* resvdTccs */
1234 /* 31 0 63 32 */
1235 {0x00U, 0x00U},
1236 },
1238 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/
1239 {
1240 /* ownPaRAMSets */
1241 /* 31 0 63 32 95 64 127 96 */
1242 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1243 /* 159 128 191 160 223 192 255 224 */
1244 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1245 /* 287 256 319 288 351 320 383 352 */
1246 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1247 /* 415 384 447 416 479 448 511 480 */
1248 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1250 /* ownDmaChannels */
1251 /* 31 0 63 32 */
1252 {0xFFFFFFFFU, 0xFFFFFFFFU},
1254 /* ownQdmaChannels */
1255 /* 31 0 */
1256 {0x000000FFU},
1258 /* ownTccs */
1259 /* 31 0 63 32 */
1260 {0xFFFFFFFFU, 0xFFFFFFFFU},
1262 /* resvdPaRAMSets */
1263 /* 31 0 63 32 95 64 127 96 */
1264 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1265 /* 159 128 191 160 223 192 255 224 */
1266 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1267 /* 287 256 319 288 351 320 383 352 */
1268 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1269 /* 415 384 447 416 479 448 511 480 */
1270 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1272 /* resvdDmaChannels */
1273 /* 31 0 63 32 */
1274 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1276 /* resvdQdmaChannels */
1277 /* 31 0 */
1278 {0x00U},
1280 /* resvdTccs */
1281 /* 31 0 63 32 */
1282 {0x00U, 0x00U},
1283 },
1285 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/
1286 {
1287 /* ownPaRAMSets */
1288 /* 31 0 63 32 95 64 127 96 */
1289 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1290 /* 159 128 191 160 223 192 255 224 */
1291 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1292 /* 287 256 319 288 351 320 383 352 */
1293 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1294 /* 415 384 447 416 479 448 511 480 */
1295 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1297 /* ownDmaChannels */
1298 /* 31 0 63 32 */
1299 {0xFFFFFFFFU, 0xFFFFFFFFU},
1301 /* ownQdmaChannels */
1302 /* 31 0 */
1303 {0x000000FFU},
1305 /* ownTccs */
1306 /* 31 0 63 32 */
1307 {0xFFFFFFFFU, 0xFFFFFFFFU},
1309 /* resvdPaRAMSets */
1310 /* 31 0 63 32 95 64 127 96 */
1311 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1312 /* 159 128 191 160 223 192 255 224 */
1313 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1314 /* 287 256 319 288 351 320 383 352 */
1315 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1316 /* 415 384 447 416 479 448 511 480 */
1317 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1319 /* resvdDmaChannels */
1320 /* 31 0 63 32 */
1321 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1323 /* resvdQdmaChannels */
1324 /* 31 0 */
1325 {0x00U},
1327 /* resvdTccs */
1328 /* 31 0 63 32 */
1329 {0x00U, 0x00U},
1330 },
1331 },
1332 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
1333 {
1334 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/
1335 {
1336 /* ownPaRAMSets */
1337 /* 31 0 63 32 95 64 127 96 */
1338 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1339 /* 159 128 191 160 223 192 255 224 */
1340 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1341 /* 287 256 319 288 351 320 383 352 */
1342 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1343 /* 415 384 447 416 479 448 511 480 */
1344 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1346 /* ownDmaChannels */
1347 /* 31 0 63 32 */
1348 {0x00000000U, 0x00000000U},
1350 /* ownQdmaChannels */
1351 /* 31 0 */
1352 {0x00000000U},
1354 /* ownTccs */
1355 /* 31 0 63 32 */
1356 {0x00000000U, 0x00000000U},
1358 /* resvdPaRAMSets */
1359 /* 31 0 63 32 95 64 127 96 */
1360 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1361 /* 159 128 191 160 223 192 255 224 */
1362 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1363 /* 287 256 319 288 351 320 383 352 */
1364 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1365 /* 415 384 447 416 479 448 511 480 */
1366 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1368 /* resvdDmaChannels */
1369 /* 31 0 63 32 */
1370 {0x00000000U, 0x00000000U},
1372 /* resvdQdmaChannels */
1373 /* 31 0 */
1374 {0x00000000U},
1376 /* resvdTccs */
1377 /* 31 0 63 32 */
1378 {0x00000000U, 0x00000000U},
1379 },
1381 /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
1382 {
1383 /* ownPaRAMSets */
1384 /* 31 0 63 32 95 64 127 96 */
1385 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1386 /* 159 128 191 160 223 192 255 224 */
1387 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1388 /* 287 256 319 288 351 320 383 352 */
1389 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1390 /* 415 384 447 416 479 448 511 480 */
1391 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1393 /* ownDmaChannels */
1394 /* 31 0 63 32 */
1395 {0x00000000U, 0x00000000U},
1397 /* ownQdmaChannels */
1398 /* 31 0 */
1399 {0x00000000U},
1401 /* ownTccs */
1402 /* 31 0 63 32 */
1403 {0x00000000U, 0x00000000U},
1405 /* resvdPaRAMSets */
1406 /* 31 0 63 32 95 64 127 96 */
1407 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1408 /* 159 128 191 160 223 192 255 224 */
1409 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1410 /* 287 256 319 288 351 320 383 352 */
1411 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1412 /* 415 384 447 416 479 448 511 480 */
1413 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1415 /* resvdDmaChannels */
1416 /* 31 0 63 32 */
1417 {0x00000000U, 0x00000000U},
1419 /* resvdQdmaChannels */
1420 /* 31 0 */
1421 {0x00000000U},
1423 /* resvdTccs */
1424 /* 31 0 63 32 */
1425 {0x00000000U, 0x00000000U},
1426 },
1428 /* Resources owned/reserved by region 2 (Associated to DSP core)*/
1429 {
1430 /* ownPaRAMSets */
1431 /* 31 0 63 32 95 64 127 96 */
1432 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1433 /* 159 128 191 160 223 192 255 224 */
1434 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1435 /* 287 256 319 288 351 320 383 352 */
1436 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1437 /* 415 384 447 416 479 448 511 480 */
1438 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1440 /* ownDmaChannels */
1441 /* 31 0 63 32 */
1442 {0xFFFFFFFFU, 0xFFFFFFFFU},
1444 /* ownQdmaChannels */
1445 /* 31 0 */
1446 {0x000000FFU},
1448 /* ownTccs */
1449 /* 31 0 63 32 */
1450 {0xFFFFFFFFU, 0xFFFFFFFFU},
1452 /* resvdPaRAMSets */
1453 /* 31 0 63 32 95 64 127 96 */
1454 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1455 /* 159 128 191 160 223 192 255 224 */
1456 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1457 /* 287 256 319 288 351 320 383 352 */
1458 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1459 /* 415 384 447 416 479 448 511 480 */
1460 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1462 /* resvdDmaChannels */
1463 /* 31 0 63 32 */
1464 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},
1466 /* resvdQdmaChannels */
1467 /* 31 0 */
1468 {0x00U},
1470 /* resvdTccs */
1471 /* 31 0 63 32 */
1472 {0x00U, 0x00U},
1473 },
1475 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
1476 {
1477 /* ownPaRAMSets */
1478 /* 31 0 63 32 95 64 127 96 */
1479 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1480 /* 159 128 191 160 223 192 255 224 */
1481 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1482 /* 287 256 319 288 351 320 383 352 */
1483 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1484 /* 415 384 447 416 479 448 511 480 */
1485 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1487 /* ownDmaChannels */
1488 /* 31 0 63 32 */
1489 {0x00000000U, 0x00000000U},
1491 /* ownQdmaChannels */
1492 /* 31 0 */
1493 {0x00000000U},
1495 /* ownTccs */
1496 /* 31 0 63 32 */
1497 {0x00000000U, 0x00000000U},
1499 /* resvdPaRAMSets */
1500 /* 31 0 63 32 95 64 127 96 */
1501 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1502 /* 159 128 191 160 223 192 255 224 */
1503 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1504 /* 287 256 319 288 351 320 383 352 */
1505 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1506 /* 415 384 447 416 479 448 511 480 */
1507 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1509 /* resvdDmaChannels */
1510 /* 31 0 63 32 */
1511 {0x00000000U, 0x00000000U},
1513 /* resvdQdmaChannels */
1514 /* 31 0 */
1515 {0x00000000U},
1517 /* resvdTccs */
1518 /* 31 0 63 32 */
1519 {0x00000000U, 0x00000000U},
1520 },
1522 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
1523 {
1524 /* ownPaRAMSets */
1525 /* 31 0 63 32 95 64 127 96 */
1526 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1527 /* 159 128 191 160 223 192 255 224 */
1528 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1529 /* 287 256 319 288 351 320 383 352 */
1530 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1531 /* 415 384 447 416 479 448 511 480 */
1532 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1534 /* ownDmaChannels */
1535 /* 31 0 63 32 */
1536 {0x00000000U, 0x00000000U},
1538 /* ownQdmaChannels */
1539 /* 31 0 */
1540 {0x00000000U},
1542 /* ownTccs */
1543 /* 31 0 63 32 */
1544 {0x00000000U, 0x00000000U},
1546 /* resvdPaRAMSets */
1547 /* 31 0 63 32 95 64 127 96 */
1548 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1549 /* 159 128 191 160 223 192 255 224 */
1550 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1551 /* 287 256 319 288 351 320 383 352 */
1552 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1553 /* 415 384 447 416 479 448 511 480 */
1554 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1556 /* resvdDmaChannels */
1557 /* 31 0 63 32 */
1558 {0x00000000U, 0x00000000U},
1560 /* resvdQdmaChannels */
1561 /* 31 0 */
1562 {0x00000000U},
1564 /* resvdTccs */
1565 /* 31 0 63 32 */
1566 {0x00000000U, 0x00000000U},
1567 },
1569 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
1570 {
1571 /* ownPaRAMSets */
1572 /* 31 0 63 32 95 64 127 96 */
1573 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1574 /* 159 128 191 160 223 192 255 224 */
1575 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1576 /* 287 256 319 288 351 320 383 352 */
1577 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1578 /* 415 384 447 416 479 448 511 480 */
1579 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1581 /* ownDmaChannels */
1582 /* 31 0 63 32 */
1583 {0x00000000U, 0x00000000U},
1585 /* ownQdmaChannels */
1586 /* 31 0 */
1587 {0x00000000U},
1589 /* ownTccs */
1590 /* 31 0 63 32 */
1591 {0x00000000U, 0x00000000U},
1593 /* resvdPaRAMSets */
1594 /* 31 0 63 32 95 64 127 96 */
1595 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1596 /* 159 128 191 160 223 192 255 224 */
1597 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1598 /* 287 256 319 288 351 320 383 352 */
1599 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1600 /* 415 384 447 416 479 448 511 480 */
1601 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1603 /* resvdDmaChannels */
1604 /* 31 0 63 32 */
1605 {0x00000000U, 0x00000000U},
1607 /* resvdQdmaChannels */
1608 /* 31 0 */
1609 {0x00000000U},
1611 /* resvdTccs */
1612 /* 31 0 63 32 */
1613 {0x00000000U, 0x00000000U},
1614 },
1616 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
1617 {
1618 /* ownPaRAMSets */
1619 /* 31 0 63 32 95 64 127 96 */
1620 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1621 /* 159 128 191 160 223 192 255 224 */
1622 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1623 /* 287 256 319 288 351 320 383 352 */
1624 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1625 /* 415 384 447 416 479 448 511 480 */
1626 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1628 /* ownDmaChannels */
1629 /* 31 0 63 32 */
1630 {0x00000000U, 0x00000000U},
1632 /* ownQdmaChannels */
1633 /* 31 0 */
1634 {0x00000000U},
1636 /* ownTccs */
1637 /* 31 0 63 32 */
1638 {0x00000000U, 0x00000000U},
1640 /* resvdPaRAMSets */
1641 /* 31 0 63 32 95 64 127 96 */
1642 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1643 /* 159 128 191 160 223 192 255 224 */
1644 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1645 /* 287 256 319 288 351 320 383 352 */
1646 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1647 /* 415 384 447 416 479 448 511 480 */
1648 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1650 /* resvdDmaChannels */
1651 /* 31 0 63 32 */
1652 {0x00000000U, 0x00000000U},
1654 /* resvdQdmaChannels */
1655 /* 31 0 */
1656 {0x00000000U},
1658 /* resvdTccs */
1659 /* 31 0 63 32 */
1660 {0x00000000U, 0x00000000U},
1661 },
1663 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
1664 {
1665 /* ownPaRAMSets */
1666 /* 31 0 63 32 95 64 127 96 */
1667 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1668 /* 159 128 191 160 223 192 255 224 */
1669 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1670 /* 287 256 319 288 351 320 383 352 */
1671 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1672 /* 415 384 447 416 479 448 511 480 */
1673 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1675 /* ownDmaChannels */
1676 /* 31 0 63 32 */
1677 {0x00000000U, 0x00000000U},
1679 /* ownQdmaChannels */
1680 /* 31 0 */
1681 {0x00000000U},
1683 /* ownTccs */
1684 /* 31 0 63 32 */
1685 {0x00000000U, 0x00000000U},
1687 /* resvdPaRAMSets */
1688 /* 31 0 63 32 95 64 127 96 */
1689 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1690 /* 159 128 191 160 223 192 255 224 */
1691 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1692 /* 287 256 319 288 351 320 383 352 */
1693 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1694 /* 415 384 447 416 479 448 511 480 */
1695 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1697 /* resvdDmaChannels */
1698 /* 31 0 63 32 */
1699 {0x00000000U, 0x00000000U},
1701 /* resvdQdmaChannels */
1702 /* 31 0 */
1703 {0x00000000U},
1705 /* resvdTccs */
1706 /* 31 0 63 32 */
1707 {0x00000000U, 0x00000000U},
1708 },
1709 }
1710 };
1712 /* Driver Instance Cross bar event to channel map Initialization Configuration */
1713 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
1714 {
1715 /* EDMA3 INSTANCE# 0 */
1716 {
1717 /* Event to channel map for region 0 */
1718 {
1719 {-1, -1, -1, -1, -1, -1, -1, -1,
1720 -1, -1, -1, -1, -1, -1, -1, -1,
1721 -1, -1, -1, -1, -1, -1, -1, -1,
1722 -1, -1, -1, -1, -1, -1, -1, -1,
1723 -1, -1, -1, -1, -1, -1, -1, -1,
1724 -1, -1, -1, -1, -1, -1, -1, -1,
1725 -1, -1, -1, -1, -1, -1, -1, -1,
1726 -1, -1, -1, -1, -1, -1, -1}
1727 },
1728 /* Event to channel map for region 1 */
1729 {
1730 {-1, -1, -1, -1, -1, -1, -1, -1,
1731 -1, -1, -1, -1, -1, -1, -1, -1,
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1736 -1, -1, -1, -1, -1, -1, -1, -1,
1737 -1, -1, -1, -1, -1, -1, -1}
1738 },
1739 /* Event to channel map for region 2 */
1740 {
1741 {-1, -1, -1, -1, -1, -1, -1, -1,
1742 -1, -1, -1, -1, -1, -1, -1, -1,
1743 -1, -1, -1, -1, -1, -1, -1, -1,
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1747 -1, -1, -1, -1, -1, -1, -1, -1,
1748 -1, -1, -1, -1, -1, -1, -1}
1749 },
1750 /* Event to channel map for region 3 */
1751 {
1752 {-1, -1, -1, -1, -1, -1, -1, -1,
1753 -1, -1, -1, -1, -1, -1, -1, -1,
1754 -1, -1, -1, -1, -1, -1, -1, -1,
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1758 -1, -1, -1, -1, -1, -1, -1, -1,
1759 -1, -1, -1, -1, -1, -1, -1}
1760 },
1761 /* Event to channel map for region 4 */
1762 {
1763 {-1, -1, -1, -1, -1, -1, -1, -1,
1764 -1, -1, -1, -1, -1, -1, -1, -1,
1765 -1, -1, -1, -1, -1, -1, -1, -1,
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1769 -1, -1, -1, -1, -1, -1, -1, -1,
1770 -1, -1, -1, -1, -1, -1, -1}
1771 },
1772 /* Event to channel map for region 5 */
1773 {
1774 {-1, -1, -1, -1, -1, -1, -1, -1,
1775 -1, -1, -1, -1, -1, -1, -1, -1,
1776 -1, -1, -1, -1, -1, -1, -1, -1,
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1780 -1, -1, -1, -1, -1, -1, -1, -1,
1781 -1, -1, -1, -1, -1, -1, -1}
1782 },
1783 /* Event to channel map for region 6 */
1784 {
1785 {-1, -1, -1, -1, -1, -1, -1, -1,
1786 -1, -1, -1, -1, -1, -1, -1, -1,
1787 -1, -1, -1, -1, -1, -1, -1, -1,
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1791 -1, -1, -1, -1, -1, -1, -1, -1,
1792 -1, -1, -1, -1, -1, -1, -1}
1793 },
1794 /* Event to channel map for region 7 */
1795 {
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1797 -1, -1, -1, -1, -1, -1, -1, -1,
1798 -1, -1, -1, -1, -1, -1, -1, -1,
1799 -1, -1, -1, -1, -1, -1, -1, -1,
1800 -1, -1, -1, -1, -1, -1, -1, -1,
1801 -1, -1, -1, -1, -1, -1, -1, -1,
1802 -1, -1, -1, -1, -1, -1, -1, -1,
1803 -1, -1, -1, -1, -1, -1, -1}
1804 },
1805 },
1806 /* EDMA3 INSTANCE# 1 */
1807 {
1808 /* Event to channel map for region 0 */
1809 {
1810 {-1, -1, -1, -1, -1, -1, -1, -1,
1811 -1, -1, -1, -1, -1, -1, -1, -1,
1812 -1, -1, -1, -1, -1, -1, -1, -1,
1813 -1, -1, -1, -1, -1, -1, -1, -1,
1814 -1, -1, -1, -1, -1, -1, -1, -1,
1815 -1, -1, -1, -1, -1, -1, -1, -1,
1816 -1, -1, -1, -1, -1, -1, -1, -1,
1817 -1, -1, -1, -1, -1, -1, -1}
1818 },
1819 /* Event to channel map for region 1 */
1820 {
1821 {-1, -1, -1, -1, -1, -1, -1, -1,
1822 -1, -1, -1, -1, -1, -1, -1, -1,
1823 -1, -1, -1, -1, -1, -1, -1, -1,
1824 -1, -1, -1, -1, -1, -1, -1, -1,
1825 -1, -1, -1, -1, -1, -1, -1, -1,
1826 -1, -1, -1, -1, -1, -1, -1, -1,
1827 -1, -1, -1, -1, -1, -1, -1, -1,
1828 -1, -1, -1, -1, -1, -1, -1}
1829 },
1830 /* Event to channel map for region 2 */
1831 {
1832 {-1, -1, -1, -1, -1, -1, -1, -1,
1833 -1, -1, -1, -1, -1, -1, -1, -1,
1834 -1, -1, -1, -1, -1, -1, -1, -1,
1835 -1, -1, -1, -1, -1, -1, -1, -1,
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1838 -1, -1, -1, -1, -1, -1, -1, -1,
1839 -1, -1, -1, -1, -1, -1, -1}
1840 },
1841 /* Event to channel map for region 3 */
1842 {
1843 {-1, -1, -1, -1, -1, -1, -1, -1,
1844 -1, -1, -1, -1, -1, -1, -1, -1,
1845 -1, -1, -1, -1, -1, -1, -1, -1,
1846 -1, -1, -1, -1, -1, -1, -1, -1,
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1849 -1, -1, -1, -1, -1, -1, -1, -1,
1850 -1, -1, -1, -1, -1, -1, -1}
1851 },
1852 /* Event to channel map for region 4 */
1853 {
1854 {-1, -1, -1, -1, -1, -1, -1, -1,
1855 -1, -1, -1, -1, -1, -1, -1, -1,
1856 -1, -1, -1, -1, -1, -1, -1, -1,
1857 -1, -1, -1, -1, -1, -1, -1, -1,
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1859 -1, -1, -1, -1, -1, -1, -1, -1,
1860 -1, -1, -1, -1, -1, -1, -1, -1,
1861 -1, -1, -1, -1, -1, -1, -1}
1862 },
1863 /* Event to channel map for region 5 */
1864 {
1865 {-1, -1, -1, -1, -1, -1, -1, -1,
1866 -1, -1, -1, -1, -1, -1, -1, -1,
1867 -1, -1, -1, -1, -1, -1, -1, -1,
1868 -1, -1, -1, -1, -1, -1, -1, -1,
1869 -1, -1, -1, -1, -1, -1, -1, -1,
1870 -1, -1, -1, -1, -1, -1, -1, -1,
1871 -1, -1, -1, -1, -1, -1, -1, -1,
1872 -1, -1, -1, -1, -1, -1, -1}
1873 },
1874 /* Event to channel map for region 6 */
1875 {
1876 {-1, -1, -1, -1, -1, -1, -1, -1,
1877 -1, -1, -1, -1, -1, -1, -1, -1,
1878 -1, -1, -1, -1, -1, -1, -1, -1,
1879 -1, -1, -1, -1, -1, -1, -1, -1,
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1881 -1, -1, -1, -1, -1, -1, -1, -1,
1882 -1, -1, -1, -1, -1, -1, -1, -1,
1883 -1, -1, -1, -1, -1, -1, -1}
1884 },
1885 /* Event to channel map for region 7 */
1886 {
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1888 -1, -1, -1, -1, -1, -1, -1, -1,
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1894 -1, -1, -1, -1, -1, -1, -1}
1895 },
1896 }
1897 };
1899 /* End of File */