OMAPL137 Integration: Config files for OMAPL137EVM
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_omapl137_arm_cfg.c
1 /*
2  * sample_omapl137_cfg.c
3  *
4  * SoC specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES         1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                    1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54     return 0;
55 }
57 signed char*  getGlobalAddr(signed char* addr)
58 {
59      return (addr); /* The address is already a global address */
60 }
62 unsigned short isGblConfigRequired(unsigned int dspNum)
63 {
64     (void) dspNum;
65     return 0;
66 }
68 /* Semaphore handles */
69 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
71 /** Number of PaRAM Sets available */
72 #define EDMA3_NUM_PARAMSET                              (128u)
73 /** Number of TCCS available */
74 #define EDMA3_NUM_TCC                                   (32u)
76 /** Number of Event Queues available                                          */
77 #define EDMA3_0_NUM_EVTQUE                              (2u)
79 /** Number of Transfer Controllers available                                  */
80 #define EDMA3_0_NUM_TC                                  (2u)
83 /** Interrupt no. for Transfer Completion                                     */
84 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (11u)
86 /** Interrupt no. for CC Error                                                */
87 #define EDMA3_0_CC_ERROR_INT                            (12u)
89 /** Interrupt no. for TCs Error                                               */
90 #define EDMA3_0_TC0_ERROR_INT                           (13u)
91 #define EDMA3_0_TC1_ERROR_INT                           (32u)
92 #define EDMA3_0_TC2_ERROR_INT                           (0u)
93 #define EDMA3_0_TC3_ERROR_INT                           (0u)
94 #define EDMA3_0_TC4_ERROR_INT                           (0u)
95 #define EDMA3_0_TC5_ERROR_INT                           (0u)
96 #define EDMA3_0_TC6_ERROR_INT                           (0u)
97 #define EDMA3_0_TC7_ERROR_INT                           (0u)
100 /**
101  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
102  * ECM events (SoC specific). These ECM events come
103  * under ECM block XXX (handling those specific ECM events). Normally, block
104  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
105  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
106  * is mapped to a specific HWI_INT YYY in the tcf file.
107  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
108  * to transfer completion interrupt.
109  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
110  * to CC error interrupts.
111  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
112  * to TC error interrupts.
113  */
114 /* EDMA 0 */
115 #define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
116 #define EDMA3_0_HWI_INT_CC_ERR                              (7u)
117 #define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
118 #define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
121 /**
122  * \brief Mapping of DMA channels 0-31 to Hardware Events from
123  * various peripherals, which use EDMA for data transfer.
124  * All channels need not be mapped, some can be free also.
125  * 1: Mapped
126  * 0: Not mapped
127  *
128  * This mapping will be used to allocate DMA channels when user passes
129  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
130  * copy). The same mapping is used to allocate the TCC when user passes
131  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
132  *
133  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
134  */
135                                                       /* 31     0 */
136 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFF3FF3FFu)
138 /**
139  * \brief Mapping of DMA channels 32-63 to Hardware Events from
140  * various peripherals, which use EDMA for data transfer.
141  * All channels need not be mapped, some can be free also.
142  * 1: Mapped
143  * 0: Not mapped
144  *
145  * This mapping will be used to allocate DMA channels when user passes
146  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
147  * copy). The same mapping is used to allocate the TCC when user passes
148  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
149  *
150  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
151  */
152 /* DMA channels 32-63 DOES NOT exist in omapl138. */
153 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
155 /* Variable which will be used internally for referring number of Event Queues*/
156 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
157                                                         EDMA3_0_NUM_EVTQUE
158                                                     };
160 /* Variable which will be used internally for referring number of TCs.        */
161 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
162                                                     EDMA3_0_NUM_TC
163                                                 };
165 /**
166  * Variable which will be used internally for referring transfer completion
167  * interrupt.
168  */
169 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
170                 {
171                     EDMA3_0_CC_XFER_COMPLETION_INT, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
172                 },
173             };
175 /**
176  * Variable which will be used internally for referring channel controller's
177  * error interrupt.
178  */
179 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
180                                                     EDMA3_0_CC_ERROR_INT
181                                                };
183 /**
184  * Variable which will be used internally for referring transfer controllers'
185  * error interrupts.
186  */
187 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
188                                {
189                                    EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
190                                    EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
191                                    EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
192                                    EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
193                                }
194                             };
196 /**
197  * Variables which will be used internally for referring the hardware interrupt
198  * for various EDMA3 interrupts.
199  */
200 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
201                                                     EDMA3_0_HWI_INT_XFER_COMP
202                                                   };
204 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
205                                                    EDMA3_0_HWI_INT_CC_ERR
206                                                };
208 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
209                                                      {
210                                                         EDMA3_0_HWI_INT_TC0_ERR,
211                                                         EDMA3_0_HWI_INT_TC1_ERR,
212                                                      }
213                                                };
215 /* Driver Object Initialization Configuration */
216 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
218     {
219         /* EDMA3 INSTANCE# 0 */
220         /** Total number of DMA Channels supported by the EDMA3 Controller    */
221         32u,
222         /** Total number of QDMA Channels supported by the EDMA3 Controller   */
223         8u,
224         /** Total number of TCCs supported by the EDMA3 Controller            */
225         32u,
226         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
227         128u,
228         /** Total number of Event Queues in the EDMA3 Controller              */
229         2u,
230         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
231         2u,
232         /** Number of Regions on this EDMA3 controller                        */
233         4u,
235         /**
236          * \brief Channel mapping existence
237          * A value of 0 (No channel mapping) implies that there is fixed association
238          * for a channel number to a parameter entry number or, in other words,
239          * PaRAM entry n corresponds to channel n.
240          */
241         0u,
243         /** Existence of memory protection feature */
244         0u,
246         /** Global Register Region of CC Registers */
247         (void *)0x01C00000u,
248         /** Transfer Controller (TC) Registers */
249         {
250             (void *)0x01C08000u,
251             (void *)0x01C08400u,
252             (void *)NULL,
253             (void *)NULL,
254             (void *)NULL,
255             (void *)NULL,
256             (void *)NULL,
257             (void *)NULL
258         },
259         /** Interrupt no. for Transfer Completion */
260         EDMA3_0_CC_XFER_COMPLETION_INT,
261         /** Interrupt no. for CC Error */
262         EDMA3_0_CC_ERROR_INT,
263         /** Interrupt no. for TCs Error */
264         {
265             EDMA3_0_TC0_ERROR_INT,
266             EDMA3_0_TC1_ERROR_INT,
267             EDMA3_0_TC2_ERROR_INT,
268             EDMA3_0_TC3_ERROR_INT,
269             EDMA3_0_TC4_ERROR_INT,
270             EDMA3_0_TC5_ERROR_INT,
271             EDMA3_0_TC6_ERROR_INT,
272             EDMA3_0_TC7_ERROR_INT
273         },
275         /**
276          * \brief EDMA3 TC priority setting
277          *
278          * User can program the priority of the Event Queues
279          * at a system-wide level.  This means that the user can set the
280          * priority of an IO initiated by either of the TCs (Transfer Controllers)
281          * relative to IO initiated by the other bus masters on the
282          * device (ARM, DSP, USB, etc)
283          */
284         {
285             0u,
286             1u,
287             0u,
288             0u,
289             0u,
290             0u,
291             0u,
292             0u
293         },
294         /**
295          * \brief To Configure the Threshold level of number of events
296          * that can be queued up in the Event queues. EDMA3CC error register
297          * (CCERR) will indicate whether or not at any instant of time the
298          * number of events queued up in any of the event queues exceeds
299          * or equals the threshold/watermark value that is set
300          * in the queue watermark threshold register (QWMTHRA).
301          */
302         {
303             16u,
304             16u,
305             0u,
306             0u,
307             0u,
308             0u,
309             0u,
310             0u
311         },
313         /**
314          * \brief To Configure the Default Burst Size (DBS) of TCs.
315          * An optimally-sized command is defined by the transfer controller
316          * default burst size (DBS). Different TCs can have different
317          * DBS values. It is defined in Bytes.
318          */
319             {
320             16u,
321             16u,
322             0u,
323             0u,
324             0u,
325             0u,
326             0u,
327             0u
328             },
330         /**
331          * \brief Mapping from each DMA channel to a Parameter RAM set,
332          * if it exists, otherwise of no use.
333          */
334             {
335             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
336             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
337             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
338             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
339             /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
340             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
341             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
342             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
343             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
344             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
345             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
346             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
347             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
348             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
349             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
350             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
351             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
352             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
353             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
354             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
355             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
356             },
358          /**
359           * \brief Mapping from each DMA channel to a TCC. This specific
360           * TCC code will be returned when the transfer is completed
361           * on the mapped channel.
362           */
363             {
364             0u, 1u, 2u, 3u,
365             4u, 5u, 6u, 7u,
366             8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
367             12u, 13u, 14u, 15u,
368             16u, 17u, 18u, 19u,
369             20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
370             24u, 25u, 26u, 27u,
371             28u, 29u, 30u, 31u,
372             /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
373             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
374             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
375             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
376             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
377             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
378             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
379             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
380             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
381             },
383         /**
384          * \brief Mapping of DMA channels to Hardware Events from
385          * various peripherals, which use EDMA for data transfer.
386          * All channels need not be mapped, some can be free also.
387          */
388             {
389             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
390             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
391             }
392         },
393 };
396 /* Driver Instance Initialization Configuration */
397 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
399     /* EDMA3 INSTANCE# 0 */
400     {
401         /* Resources owned/reserved by region 0 */
402         {
403             /* ownPaRAMSets */
404             /* 31     0     63    32     95    64     127   96 */
405             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
406             /* 159  128     191  160     223  192     255  224 */
407              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
408             /* 287  256     319  288     351  320     383  352 */
409              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
410             /* 415  384     447  416     479  448     511  480 */
411              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
413             /* ownDmaChannels */
414             /* 31     0     63    32 */
415             {0xFFFFFFFFu, 0x00000000u},
417             /* ownQdmaChannels */
418             /* 31     0 */
419             {0x000000FFu},
421             /* ownTccs */
422             /* 31     0     63    32 */
423             {0xFFFFFFFFu, 0x00000000u},
425             /* Resources reserved by Region 1 */
426             /* resvdPaRAMSets */
427             /* 31     0     63    32     95    64     127   96 */
428             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
429             /* 159  128     191  160     223  192     255  224 */
430              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
431             /* 287  256     319  288     351  320     383  352 */
432              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
433             /* 415  384     447  416     479  448     511  480 */
434              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
436             /* resvdDmaChannels */
437             /* 31       0 */
438             {0xFF3FF3FFu,
439             /* 63..32 */
440             0x00000000u},
442             /* resvdQdmaChannels */
443             /* 31     0 */
444             {0x00000000u},
446             /* resvdTccs */
447             /* 31       0 */
448             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
449             /* 63..32 */
450             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
451         },
452         /* Resources owned/reserved by region 1 */
453         {
454             /* ownPaRAMSets */
455             /* 31     0     63    32     95    64     127   96 */
456             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
457             /* 159  128     191  160     223  192     255  224 */
458              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
459             /* 287  256     319  288     351  320     383  352 */
460              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
461             /* 415  384     447  416     479  448     511  480 */
462              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
464             /* ownDmaChannels */
465             /* 31     0     63    32 */
466             {0xFFFFFFFFu, 0x00000000u},
468             /* ownQdmaChannels */
469             /* 31     0 */
470             {0x000000FFu},
472             /* ownTccs */
473             /* 31     0     63    32 */
474             {0xFFFFFFFFu, 0x00000000u},
476             /* Resources reserved by Region 1 */
477             /* resvdPaRAMSets */
478             /* 31     0     63    32     95    64     127   96 */
479             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
480             /* 159  128     191  160     223  192     255  224 */
481              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
482             /* 287  256     319  288     351  320     383  352 */
483              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
484             /* 415  384     447  416     479  448     511  480 */
485              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
487             /* resvdDmaChannels */
488             /* 31       0 */
489             {0xFF3FF3FFu,
490             /* 63..32 */
491             0x00000000u},
493             /* resvdQdmaChannels */
494             /* 31     0 */
495             {0x00000000u},
497             /* resvdTccs */
498             /* 31       0 */
499             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
500             /* 63..32 */
501             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
502         },
503         /* Resources owned/reserved by region 2 */
504         {
505             /* ownPaRAMSets */
506             /* 31     0     63    32     95    64     127   96 */
507             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
508             /* 159  128     191  160     223  192     255  224 */
509              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
510             /* 287  256     319  288     351  320     383  352 */
511              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
512             /* 415  384     447  416     479  448     511  480 */
513              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
515             /* ownDmaChannels */
516             /* 31     0     63    32 */
517             {0x00000000u, 0x00000000u},
519             /* ownQdmaChannels */
520             /* 31     0 */
521             {0x00000000u},
523             /* ownTccs */
524             /* 31     0     63    32 */
525             {0x00000000u, 0x00000000u},
527             /* resvdPaRAMSets */
528             /* 31     0     63    32     95    64     127   96 */
529             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
530             /* 159  128     191  160     223  192     255  224 */
531              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
532             /* 287  256     319  288     351  320     383  352 */
533              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
534             /* 415  384     447  416     479  448     511  480 */
535              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
537             /* resvdDmaChannels */
538             /* 31     0     63    32 */
539             {0x00000000u, 0x00000000u},
541             /* resvdQdmaChannels */
542             /* 31     0 */
543             {0x00000000u},
545             /* resvdTccs */
546             /* 31     0     63    32 */
547             {0x00000000u, 0x00000000u},
548         },
550         /* Resources owned/reserved by region 3 */
551         {
552             /* ownPaRAMSets */
553             /* 31     0     63    32     95    64     127   96 */
554             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
555             /* 159  128     191  160     223  192     255  224 */
556              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
557             /* 287  256     319  288     351  320     383  352 */
558              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
559             /* 415  384     447  416     479  448     511  480 */
560              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
562             /* ownDmaChannels */
563             /* 31     0     63    32 */
564             {0x00000000u, 0x00000000u},
566             /* ownQdmaChannels */
567             /* 31     0 */
568             {0x00000000u},
570             /* ownTccs */
571             /* 31     0     63    32 */
572             {0x00000000u, 0x00000000u},
574             /* resvdPaRAMSets */
575             /* 31     0     63    32     95    64     127   96 */
576             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
577             /* 159  128     191  160     223  192     255  224 */
578              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
579             /* 287  256     319  288     351  320     383  352 */
580              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
581             /* 415  384     447  416     479  448     511  480 */
582              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
584             /* resvdDmaChannels */
585             /* 31     0     63    32 */
586             {0x00000000u, 0x00000000u},
588             /* resvdQdmaChannels */
589             /* 31     0 */
590             {0x00000000u},
592             /* resvdTccs */
593             /* 31     0     63    32 */
594             {0x00000000u, 0x00000000u},
595         },
597         /* Resources owned/reserved by region 4 */
598         {
599             /* ownPaRAMSets */
600             /* 31     0     63    32     95    64     127   96 */
601             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
602             /* 159  128     191  160     223  192     255  224 */
603              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
604             /* 287  256     319  288     351  320     383  352 */
605              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
606             /* 415  384     447  416     479  448     511  480 */
607              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
609             /* ownDmaChannels */
610             /* 31     0     63    32 */
611             {0x00000000u, 0x00000000u},
613             /* ownQdmaChannels */
614             /* 31     0 */
615             {0x00000000u},
617             /* ownTccs */
618             /* 31     0     63    32 */
619             {0x00000000u, 0x00000000u},
621             /* resvdPaRAMSets */
622             /* 31     0     63    32     95    64     127   96 */
623             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
624             /* 159  128     191  160     223  192     255  224 */
625              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
626             /* 287  256     319  288     351  320     383  352 */
627              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
628             /* 415  384     447  416     479  448     511  480 */
629              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
631             /* resvdDmaChannels */
632             /* 31     0     63    32 */
633             {0x00000000u, 0x00000000u},
635             /* resvdQdmaChannels */
636             /* 31     0 */
637             {0x00000000u},
639             /* resvdTccs */
640             /* 31     0     63    32 */
641             {0x00000000u, 0x00000000u},
642         },
644         /* Resources owned/reserved by region 5 */
645         {
646             /* ownPaRAMSets */
647             /* 31     0     63    32     95    64     127   96 */
648             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
649             /* 159  128     191  160     223  192     255  224 */
650              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
651             /* 287  256     319  288     351  320     383  352 */
652              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
653             /* 415  384     447  416     479  448     511  480 */
654              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
656             /* ownDmaChannels */
657             /* 31     0     63    32 */
658             {0x00000000u, 0x00000000u},
660             /* ownQdmaChannels */
661             /* 31     0 */
662             {0x00000000u},
664             /* ownTccs */
665             /* 31     0     63    32 */
666             {0x00000000u, 0x00000000u},
668             /* resvdPaRAMSets */
669             /* 31     0     63    32     95    64     127   96 */
670             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
671             /* 159  128     191  160     223  192     255  224 */
672              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
673             /* 287  256     319  288     351  320     383  352 */
674              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
675             /* 415  384     447  416     479  448     511  480 */
676              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
678             /* resvdDmaChannels */
679             /* 31     0     63    32 */
680             {0x00000000u, 0x00000000u},
682             /* resvdQdmaChannels */
683             /* 31     0 */
684             {0x00000000u},
686             /* resvdTccs */
687             /* 31     0     63    32 */
688             {0x00000000u, 0x00000000u},
689         },
691         /* Resources owned/reserved by region 6 */
692         {
693             /* ownPaRAMSets */
694             /* 31     0     63    32     95    64     127   96 */
695             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
696             /* 159  128     191  160     223  192     255  224 */
697              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
698             /* 287  256     319  288     351  320     383  352 */
699              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
700             /* 415  384     447  416     479  448     511  480 */
701              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
703             /* ownDmaChannels */
704             /* 31     0     63    32 */
705             {0x00000000u, 0x00000000u},
707             /* ownQdmaChannels */
708             /* 31     0 */
709             {0x00000000u},
711             /* ownTccs */
712             /* 31     0     63    32 */
713             {0x00000000u, 0x00000000u},
715             /* resvdPaRAMSets */
716             /* 31     0     63    32     95    64     127   96 */
717             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
718             /* 159  128     191  160     223  192     255  224 */
719              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
720             /* 287  256     319  288     351  320     383  352 */
721              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
722             /* 415  384     447  416     479  448     511  480 */
723              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
725             /* resvdDmaChannels */
726             /* 31     0     63    32 */
727             {0x00000000u, 0x00000000u},
729             /* resvdQdmaChannels */
730             /* 31     0 */
731             {0x00000000u},
733             /* resvdTccs */
734             /* 31     0     63    32 */
735             {0x00000000u, 0x00000000u},
736         },
738         /* Resources owned/reserved by region 7 */
739         {
740             /* ownPaRAMSets */
741             /* 31     0     63    32     95    64     127   96 */
742             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
743             /* 159  128     191  160     223  192     255  224 */
744              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
745             /* 287  256     319  288     351  320     383  352 */
746              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
747             /* 415  384     447  416     479  448     511  480 */
748              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
750             /* ownDmaChannels */
751             /* 31     0     63    32 */
752             {0x00000000u, 0x00000000u},
754             /* ownQdmaChannels */
755             /* 31     0 */
756             {0x00000000u},
758             /* ownTccs */
759             /* 31     0     63    32 */
760             {0x00000000u, 0x00000000u},
762             /* resvdPaRAMSets */
763             /* 31     0     63    32     95    64     127   96 */
764             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
765             /* 159  128     191  160     223  192     255  224 */
766              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
767             /* 287  256     319  288     351  320     383  352 */
768              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
769             /* 415  384     447  416     479  448     511  480 */
770              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
772             /* resvdDmaChannels */
773             /* 31     0     63    32 */
774             {0x00000000u, 0x00000000u},
776             /* resvdQdmaChannels */
777             /* 31     0 */
778             {0x00000000u},
780             /* resvdTccs */
781             /* 31     0     63    32 */
782             {0x00000000u, 0x00000000u},
783         },
784     }
785 };
787 /* End of File */