[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tci6486_int_reg.c
1 /*
2 * sample_tci6486_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/family/c64p/EventCombiner.h>
41 #include <ti/sysbios/family/c64p/Hwi.h>
43 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
45 // #include <stdio.h>
46 /**
47 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
48 * (Not all TC error ISRs need to be registered, register only for the
49 * available Transfer Controllers).
50 */
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
52 {
53 &lisrEdma3TC0ErrHandler0,
54 &lisrEdma3TC1ErrHandler0,
55 &lisrEdma3TC2ErrHandler0,
56 &lisrEdma3TC3ErrHandler0,
57 &lisrEdma3TC4ErrHandler0,
58 &lisrEdma3TC5ErrHandler0,
59 &lisrEdma3TC6ErrHandler0,
60 &lisrEdma3TC7ErrHandler0,
61 };
63 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
64 extern unsigned int ccErrorInt[];
65 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
66 extern unsigned int numEdma3Tc[];
68 /**
69 * Variables which will be used internally for referring the hardware interrupt
70 * for various EDMA3 interrupts.
71 */
72 extern unsigned int hwIntXferComp[];
73 extern unsigned int hwIntCcErr;
74 extern unsigned int hwIntTcErr[];
76 extern unsigned int dsp_num;
78 /** To Register the ISRs with the underlying OS, if required. */
79 void registerEdma3Interrupts (unsigned int edma3Id)
80 {
81 static UInt32 cookie = 0;
82 unsigned int numTc = 0;
84 /* Disabling the global interrupts */
85 cookie = Hwi_disable();
87 /* Enable the Xfer Completion Event Interrupt */
88 EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
89 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
90 NULL, 1);
91 EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
93 /* Enable the CC Error Event Interrupt */
94 EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
95 (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
96 NULL, 1);
97 EventCombiner_enableEvent(ccErrorInt[edma3Id]);
99 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
100 while (numTc < numEdma3Tc[edma3Id])
101 {
102 EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
103 (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
104 NULL, 1);
105 EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
106 numTc++;
107 }
109 /**
110 * Enabling the HWI_ID.
111 * EDMA3 interrupts (transfer completion, CC error etc.)
112 * correspond to different ECM events (SoC specific). These ECM events come
113 * under ECM block XXX (handling those specific ECM events). Normally, block
114 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
115 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
116 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
117 * mapped HWI_INT YYY, one should use the corresponding bitmask in the
118 * API C64_enableIER(), in which the YYY bit is SET.
119 */
120 Hwi_enableInterrupt(hwIntXferComp[dsp_num]);
121 Hwi_enableInterrupt(hwIntCcErr);
122 numTc = 0;
123 while (numTc < numEdma3Tc[edma3Id])
124 {
125 Hwi_enableInterrupt(hwIntTcErr[numTc]);
126 numTc++;
127 }
129 /* Restore interrupts */
130 Hwi_restore(cookie);
131 }
133 /** To Unregister the ISRs with the underlying OS, if previously registered. */
134 void unregisterEdma3Interrupts (unsigned int edma3Id)
135 {
136 static UInt32 cookie = 0;
137 unsigned int numTc = 0;
139 /* Disabling the global interrupts */
140 cookie = Hwi_disable();
142 /* Disable the Xfer Completion Event Interrupt */
143 EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
145 /* Disable the CC Error Event Interrupt */
146 EventCombiner_disableEvent(ccErrorInt[edma3Id]);
148 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
149 while (numTc < numEdma3Tc[edma3Id])
150 {
151 EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
152 numTc++;
153 }
155 /* Restore interrupts */
156 Hwi_restore(cookie);
157 }