packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6498_int_reg.c

   1 /*
   2  * bios6_int_register_tci_6498.c
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  *
   7  *  Redistribution and use in source and binary forms, with or without
   8  *  modification, are permitted provided that the following conditions
   9  *  are met:
  10  *
  11  *    Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  *
  14  *    Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the
  17  *    distribution.
  18  *
  19  *    Neither the name of Texas Instruments Incorporated nor the names of
  20  *    its contributors may be used to endorse or promote products derived
  21  *    from this software without specific prior written permission.
  22  *
  23  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  24  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  25  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  26  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  27  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  28  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  29  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  30  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  31  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  32  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35 */
  36
  37 #include <ti/sysbios/ipc/Semaphore.h>
  38 #include <ti/sysbios/family/c64p/EventCombiner.h>
  39 #include <ti/sysbios/family/c64p/Hwi.h>
  40
  41 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
  42
  43 #include <stdio.h>
  44 #include <csl_intc.h>
  45 #include <csl_cpIntcAux.h>
  46
  47 /** CSL handles for interrupt registration */
  48 CSL_CPINTC_Handle hnd = NULL;
  49
  50 void cpintc0_isr(UArg arg0);
  51
  52 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
  53 extern unsigned int ccErrorInt[];
  54 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
  55 extern unsigned int numEdma3Tc[];
  56
  57 unsigned int cp_intc0_channel_mapping[3] = {3,4,5};
  58 unsigned int gem_event_id[3] = {59,60,61};
  59 unsigned int hwiInterrupt = 8;
  60
  61 /* gem_event_to_intc0_event_map[EDMA3 #][DSP #] */
  62 unsigned int gem_event_to_intc0_event_map[3][4] = {
  63                                                                                         {3, 19, 35, 51},
  64                                                                                         {4, 20, 36, 52},
  65                                                                                         {5, 21, 37, 53},
  66                                                                                         };
  67
  68 extern unsigned int dsp_num;
  69
  70 void init_cp_intc (unsigned int edma3Id)
  71         {
  72         unsigned int numTc = 0;
  73
  74         /* Open the handle to the CPINT Instance */
  75         if (hnd == 0)
  76                 {
  77                 hnd = CSL_CPINTC_open(0);
  78                 if (hnd == 0)
  79                         {
  80                         printf ("Error: Unable to open CPINTC-0\n");
  81                         return;
  82                         }
  83                 }
  84
  85         /* Disable all host interrupts. */
  86         CSL_CPINTC_disableAllHostInterrupt(hnd);
  87
  88         /* Configure no nesting support in the CPINTC Module. */
  89         CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING);
  90
  91         /* We now map CP_INTC Channel to Host Interrupt */
  92         CSL_CPINTC_mapChannelToHostInterrupt (hnd,
  93                                                                         cp_intc0_channel_mapping[edma3Id],
  94                                                                         gem_event_to_intc0_event_map[edma3Id][dsp_num]);
  95
  96         /* We now map System Interrupt ccXferCompInt to CP_INTC channel */
  97         CSL_CPINTC_mapSystemIntrToChannel (hnd,
  98                                                                         ccXferCompInt[edma3Id][dsp_num],
  99                                                                         cp_intc0_channel_mapping[edma3Id]);
 100
 101         /* We now enable system interrupt ccXferCompInt  */
 102         CSL_CPINTC_enableSysInterrupt (hnd, ccXferCompInt[edma3Id][dsp_num]);
 103
 104         /* We now map System Interrupt ccErrorInt to CP_INTC channel */
 105         CSL_CPINTC_mapSystemIntrToChannel (hnd,ccErrorInt[edma3Id],
 106                                                                                 cp_intc0_channel_mapping[edma3Id]);
 107
 108         /* We now enable system interrupt ccErrorInt */
 109         CSL_CPINTC_enableSysInterrupt (hnd, ccErrorInt[edma3Id]);
 110
 111         /* Enable the TC Error Event Interrupt, according to the number of TCs. */
 112         while (numTc < numEdma3Tc[edma3Id])
 113                 {
 114                 /* We now map System Interrupt tcErrorInt to CP_INTC channel */
 115                 CSL_CPINTC_mapSystemIntrToChannel (hnd,
 116                                                                                 tcErrorInt[edma3Id][numTc],
 117                                                                                 cp_intc0_channel_mapping[edma3Id]);
 118
 119                 /* We now enable system interrupt tcErrorInt */
 120                 CSL_CPINTC_enableSysInterrupt (hnd, tcErrorInt[edma3Id][numTc]);
 121
 122                 numTc++;
 123                 }
 124
 125         /* We enable host interrupts. */
 126         CSL_CPINTC_enableHostInterrupt (hnd,
 127                                                                 gem_event_to_intc0_event_map[edma3Id][dsp_num]);
 128
 129         /* Enable all host interrupts also. */
 130         CSL_CPINTC_enableAllHostInterrupt(hnd);
 131         }
 132
 133 void deinit_cp_intc (unsigned int edma3Id)
 134         {
 135         unsigned int numTc = 0;
 136
 137         /* Disable all host interrupts. */
 138         CSL_CPINTC_disableAllHostInterrupt(hnd);
 139
 140         /* Disable system interrupt ccXferCompInt  */
 141         CSL_CPINTC_disableSysInterrupt (hnd, ccXferCompInt[edma3Id][dsp_num]);
 142
 143         /* Disable system interrupt ccErrorInt */
 144         CSL_CPINTC_disableSysInterrupt (hnd, ccErrorInt[edma3Id]);
 145
 146         /* Enable the TC Error Event Interrupt, according to the number of TCs. */
 147         while (numTc < numEdma3Tc[edma3Id])
 148                 {
 149                 /* Disable system interrupt tcErrorInt */
 150                 CSL_CPINTC_disableSysInterrupt (hnd, tcErrorInt[edma3Id][numTc]);
 151
 152                 numTc++;
 153                 }
 154
 155         /* Disable host interrupt */
 156         CSL_CPINTC_disableHostInterrupt (hnd,
 157                                                                 gem_event_to_intc0_event_map[edma3Id][dsp_num]);
 158
 159         /* Enable all host interrupts  */
 160         CSL_CPINTC_enableAllHostInterrupt(hnd);
 161         }
 162
 163 void cpintc0_isr(UArg arg0)
 164         {
 165     CSL_CPINTCSystemInterrupt sysIntr;
 166         unsigned int edma3Id = (unsigned int)arg0;
 167
 168     /* We enable host interrupts. */
 169     CSL_CPINTC_disableHostInterrupt (hnd, gem_event_to_intc0_event_map[edma3Id][dsp_num]);
 170
 171     if (CSL_CPINTC_isInterruptPending(hnd) == TRUE)
 172         {
 173         /* Step 1: Get the Source of the interrupt */
 174         sysIntr = CSL_CPINTC_getPendingInterrupt(hnd);
 175
 176         /* Step 2: Clear the status of the interrupt. */
 177         CSL_CPINTC_clearSysInterrupt(hnd, sysIntr);
 178
 179         /* Step 2: Call the appropriate ISR handler */
 180         if ( sysIntr == ccXferCompInt[edma3Id][dsp_num] ) {
 181             lisrEdma3ComplHandler0(arg0);
 182         }
 183         else if ( sysIntr == ccErrorInt[edma3Id] ) {
 184             lisrEdma3CCErrHandler0(arg0);
 185         }
 186         else if ( sysIntr == tcErrorInt[edma3Id][0] ) {
 187             lisrEdma3TC0ErrHandler0(arg0);
 188         }
 189         else if ( sysIntr == tcErrorInt[edma3Id][1] ) {
 190             lisrEdma3TC1ErrHandler0(arg0);
 191         }
 192         else if ( sysIntr == tcErrorInt[edma3Id][2] ) {
 193             lisrEdma3TC2ErrHandler0(arg0);
 194         }
 195         else if ( sysIntr == tcErrorInt[edma3Id][3] ) {
 196             lisrEdma3TC3ErrHandler0(arg0);
 197         }
 198         else if ( sysIntr == tcErrorInt[edma3Id][4] ) {
 199             lisrEdma3TC4ErrHandler0(arg0);
 200         }
 201         else if ( sysIntr == tcErrorInt[edma3Id][5] ) {
 202             lisrEdma3TC5ErrHandler0(arg0);
 203         }
 204         else if ( sysIntr == tcErrorInt[edma3Id][6] ) {
 205             lisrEdma3TC6ErrHandler0(arg0);
 206         }
 207         else if ( sysIntr == tcErrorInt[edma3Id][7] ) {
 208             lisrEdma3TC7ErrHandler0(arg0);
 209         }
 210         } /* while */
 211
 212     /* We enable host interrupts. */
 213     CSL_CPINTC_enableHostInterrupt (hnd,
 214                                                                 gem_event_to_intc0_event_map[edma3Id][dsp_num]);
 215         }
 216
 217 /**  To Register the ISRs with the underlying OS, if required. */
 218 void registerEdma3Interrupts (unsigned int edma3Id)
 219     {
 220     static UInt32 cookie = 0;
 221
 222         /* Initialize the CP_INTC module for the EDMA3 hardware first */
 223         init_cp_intc(edma3Id);
 224
 225     /* Disabling the global interrupts */
 226     cookie = Hwi_disable();
 227
 228     /* Enable the global cp_intc0 isr, which will handle all the EDMA3 interrupts */
 229     EventCombiner_dispatchPlug (gem_event_id[edma3Id],
 230                                                         (EventCombiner_FuncPtr)(&cpintc0_isr),
 231                                 edma3Id, 1);
 232         EventCombiner_enableEvent(gem_event_id[edma3Id]);
 233
 234     Hwi_enableInterrupt(hwiInterrupt);
 235
 236     /* Restore interrupts */
 237     Hwi_restore(cookie);
 238     }
 239
 240 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 241 void unregisterEdma3Interrupts (unsigned int edma3Id)
 242     {
 243     static UInt32 cookie = 0;
 244
 245     /* Disabling the global interrupts */
 246     cookie = Hwi_disable();
 247
 248     /* Disable the global cp_intc0 isr, which will handle all the EDMA3 interrupts */
 249     EventCombiner_disableEvent(gem_event_id[edma3Id]);
 250
 251     /* Restore interrupts */
 252     Hwi_restore(cookie);
 253
 254         /* De-initialize the CP_INTC module too */
 255         deinit_cp_intc(edma3Id);
 256     }
 257