packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6638k2k_int_reg.c

   1 /*
   2  * sample_tci6638k2k_int_reg.c
   3  *
   4  * Platform specific interrupt registration and un-registration routines.
   5  *
   6  * Copyright (C) 2012-2017 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  *
   9  *  Redistribution and use in source and binary forms, with or without
  10  *  modification, are permitted provided that the following conditions
  11  *  are met:
  12  *
  13  *    Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  *
  16  *    Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the
  19  *    distribution.
  20  *
  21  *    Neither the name of Texas Instruments Incorporated nor the names of
  22  *    its contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37 */
  38
  39 #include <ti/sysbios/knl/Semaphore.h>
  40 #include <ti/sysbios/family/c64p/Hwi.h>
  41 #include <ti/sysbios/family/c64p/EventCombiner.h>
  42 #include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
  43
  44 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
  45
  46 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
  47 extern unsigned int ccErrorInt[];
  48 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
  49 extern unsigned int numEdma3Tc[];
  50
  51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
  52                                                 {
  53                                                 &lisrEdma3TC0ErrHandler0,
  54                                                 &lisrEdma3TC1ErrHandler0,
  55                                                 &lisrEdma3TC2ErrHandler0,
  56                                                 &lisrEdma3TC3ErrHandler0,
  57                                                 &lisrEdma3TC4ErrHandler0,
  58                                                 &lisrEdma3TC5ErrHandler0,
  59                                                 &lisrEdma3TC6ErrHandler0,
  60                                                 &lisrEdma3TC7ErrHandler0,
  61                                                 };
  62
  63 unsigned int hwiInterrupt = 8;
  64
  65 /* Host interrupts for transfer completion */
  66 /* First 4 cores are connected from CP_INTC0 and last 4 cores are connected from CP_INTC1 */
  67 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
  68 unsigned int ccXferHostInt[5][8] = {
  69                     /*     CP_INTC0     |      CP_INTC1    */
  70                                                                                 {68u, 78u, 88u, 98u, 68u, 78u, 88u, 98u},
  71                                                                                 {69u, 79u, 89u, 99u, 69u, 79u, 89u, 99u},
  72                                                                                 {70u, 80u, 90u, 100u, 70u, 80u, 90u, 100u},
  73                                                                                 {71u, 81u, 91u, 101u, 71u, 81u, 91u, 101u},
  74                                                                                 {72u, 82u, 92u, 102u, 72u, 82u, 92u, 102u},
  75                                                                                 };
  76 unsigned int edma3ErrHostInt[5][8] = {
  77                                                                                 {73u, 83u, 93u, 103u, 73u, 83u, 93u, 103u},
  78                                                                                 {64u, 74u, 84u, 94u, 64u, 74u, 84u, 94u},
  79                                                                                 {65u, 75u, 85u, 95u, 65u, 75u, 85u, 95u},
  80                                                                                 {66u, 76u, 86u, 96u, 66u, 76u, 86u, 96u},
  81                                                                                 {67u, 77u, 87u, 97u, 67u, 77u, 87u, 97u},
  82                                                                                 };
  83
  84
  85 extern unsigned int dsp_num;
  86
  87 /**  To Register the ISRs with the underlying OS, if required */
  88 void registerEdma3Interrupts (unsigned int edma3Id)
  89     {
  90     static UInt32 cookie = 0;
  91     Int eventId = 0;    /* GEM event id */
  92     unsigned int numTc = 0;
  93
  94     /* Use CP_INTC0 for DSP core 0-3 and CP_INTC1 for DSP core 4-7 */
  95     unsigned int cpIntcNum = (dsp_num > 3)? 1: 0;
  96
  97     /* Disabling the global interrupts */
  98     cookie = Hwi_disable();
  99
 100         /* Transfer completion ISR */
 101         CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
 102                                                 lisrEdma3ComplHandler0,
 103                                                 edma3Id,
 104                                                 TRUE);
 105         CpIntc_mapSysIntToHostInt(cpIntcNum, ccXferCompInt[edma3Id][dsp_num],
 106                                                                 ccXferHostInt[edma3Id][dsp_num]);
 107         CpIntc_enableHostInt(cpIntcNum, ccXferHostInt[edma3Id][dsp_num]);
 108     eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
 109     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
 110                                 ccXferHostInt[edma3Id][dsp_num], TRUE);
 111         EventCombiner_enableEvent(eventId);
 112
 113         /* CC Error ISR */
 114         CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
 115                                                 edma3Id, TRUE);
 116         CpIntc_mapSysIntToHostInt(cpIntcNum, ccErrorInt[edma3Id],
 117                                                                 edma3ErrHostInt[edma3Id][dsp_num]);
 118         /* TC Error ISR */
 119     while (numTc < numEdma3Tc[edma3Id])
 120             {
 121                 CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
 122                                                         (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
 123                                                         edma3Id, TRUE);
 124                 CpIntc_mapSysIntToHostInt(cpIntcNum, tcErrorInt[edma3Id][numTc],
 125                                                                         edma3ErrHostInt[edma3Id][dsp_num]);
 126         numTc++;
 127         }
 128         /* Enable the host interrupt which is common for both CC and TC error */
 129         CpIntc_enableHostInt(cpIntcNum, edma3ErrHostInt[edma3Id][dsp_num]);
 130     eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
 131     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
 132                                 edma3ErrHostInt[edma3Id][dsp_num], TRUE);
 133         EventCombiner_enableEvent(eventId);
 134
 135     Hwi_enableInterrupt(hwiInterrupt);
 136
 137     /* enable the 'global' switch */
 138     CpIntc_enableAllHostInts(cpIntcNum);
 139
 140     /* Restore interrupts */
 141     Hwi_restore(cookie);
 142     }
 143
 144 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 145 void unregisterEdma3Interrupts (unsigned int edma3Id)
 146     {
 147     static UInt32 cookie = 0;
 148     Int eventId = 0;    /* GEM event id */
 149
 150     /* Use CP_INTC0 for DSP core 0-3 and CP_INTC1 for DSP core 4-7 */
 151     unsigned int cpIntcNum = (dsp_num > 3)? 1: 0;
 152
 153     /* Disabling the global interrupts */
 154     cookie = Hwi_disable();
 155
 156         /* Transfer completion ISR */
 157         CpIntc_disableHostInt(cpIntcNum, ccXferHostInt[edma3Id][dsp_num]);
 158     eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
 159         EventCombiner_disableEvent(eventId);
 160
 161         /* CC/TC Error ISR */
 162         CpIntc_disableHostInt(cpIntcNum, edma3ErrHostInt[edma3Id][dsp_num]);
 163     eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
 164         EventCombiner_disableEvent(eventId);
 165
 166     /* Restore interrupts */
 167     Hwi_restore(cookie);
 168     }
 169
 170 /**
 171  * \brief   enableXferCompInterrupt
 172  *
 173  * This function enables the tranfer completion interrupt of EDMA3.
 174  *
 175  * \return  nil
 176  */
 177 void enableXferCompInterrupt(uint32_t edma3Id)
 178 {
 179         int32_t eventId = 0;    /* GEM event id */
 180     eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
 181         EventCombiner_enableEvent(eventId);
 182 }
 183
 184 /**
 185  * \brief   disableXferCompInterrupt
 186  *
 187  * This function disables the tranfer completion interrupt of EDMA3.
 188  *
 189  * \return  nil
 190  */
 191 void disableXferCompInterrupt(uint32_t edma3Id)
 192 {
 193     int32_t eventId = 0;        /* GEM event id */
 194     eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
 195         EventCombiner_disableEvent(eventId);
 196 }
 197
 198 /**
 199  * \brief   enableErrorInterrupt
 200  *
 201  * This function enables the error interrupt of EDMA3.
 202  *
 203  * \return  nil
 204  */
 205 void enableErrorInterrupt(uint32_t edma3Id)
 206 {
 207     int32_t eventId = 0;        /* GEM event id */
 208     eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
 209         EventCombiner_enableEvent(eventId);
 210 }
 211
 212 /**
 213  * \brief   disableErrorInterrupt
 214  *
 215  * This function disables the error interrupt of EDMA3.
 216  *
 217  * \return  nil
 218  */
 219 void disableErrorInterrupt(uint32_t edma3Id)
 220 {
 221     int32_t eventId = 0;        /* GEM event id */
 222     eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
 223         EventCombiner_disableEvent(eventId);
 224 }
 225