[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_arm_int_reg.c
1 /*\r
2 * sample_tda2xx_int_reg.c\r
3 *\r
4 * Platform specific interrupt registration and un-registration routines.\r
5 *\r
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7 *\r
8 *\r
9 * Redistribution and use in source and binary forms, with or without\r
10 * modification, are permitted provided that the following conditions\r
11 * are met:\r
12 *\r
13 * Redistributions of source code must retain the above copyright\r
14 * notice, this list of conditions and the following disclaimer.\r
15 *\r
16 * Redistributions in binary form must reproduce the above copyright\r
17 * notice, this list of conditions and the following disclaimer in the\r
18 * documentation and/or other materials provided with the\r
19 * distribution.\r
20 *\r
21 * Neither the name of Texas Instruments Incorporated nor the names of\r
22 * its contributors may be used to endorse or promote products derived\r
23 * from this software without specific prior written permission.\r
24 *\r
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36 *\r
37 */\r
38 \r
39 #include <ti/sysbios/knl/Semaphore.h>\r
40 #include <ti/sysbios/hal/Hwi.h>\r
41 #include <ti/sysbios/family/shared/vayu/IntXbar.h>\r
42 #include <ti/sysbios/family/arm/a15/Mmu.h>\r
43 #include <xdc/runtime/Error.h>\r
44 #include <xdc/runtime/System.h>\r
45 \r
46 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
47 \r
48 /**\r
49 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user\r
50 * (Not all TC error ISRs need to be registered, register only for the\r
51 * available Transfer Controllers).\r
52 */\r
53 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =\r
54 {\r
55 (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,\r
56 (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,\r
57 (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,\r
58 (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,\r
59 (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,\r
60 (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,\r
61 (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,\r
62 (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,\r
63 };\r
64 \r
65 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
66 extern unsigned int ccErrorInt[];\r
67 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
68 extern unsigned int numEdma3Tc[];\r
69 extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];\r
70 extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];\r
71 extern unsigned int ccErrorIntXbarInstNo[];\r
72 extern unsigned int ccErrEdmaXbarIndex[];\r
73 extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];\r
74 extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];\r
75 \r
76 /**\r
77 * Variables which will be used internally for referring the hardware interrupt\r
78 * for various EDMA3 interrupts.\r
79 */\r
80 extern unsigned int hwIntXferComp[];\r
81 extern unsigned int hwIntCcErr[];\r
82 extern unsigned int hwIntTcErr[];\r
83 \r
84 extern unsigned int dsp_num;\r
85 /* This variable has to be used as an extern */\r
86 unsigned int gpp_num = 0;\r
87 \r
88 Hwi_Handle hwiCCXferCompInt;\r
89 Hwi_Handle hwiCCErrInt;\r
90 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];\r
91 \r
92 /* External Instance Specific Configuration Structure */\r
93 extern EDMA3_DRV_GblXbarToChanConfigParams \r
94 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
95 \r
96 typedef struct {\r
97 volatile Uint32 TPCC_EVTMUX[32];\r
98 } CSL_IntmuxRegs;\r
99 \r
100 typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;\r
101 \r
102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
105 \r
106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
109 \r
110 \r
111 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)\r
112 #define EDMA3_NUM_TCC (64u)\r
113 \r
114 #define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)\r
115 /*\r
116 * Forward decleration\r
117 */\r
118 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
119 unsigned int *chanNum,\r
120 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
121 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
122 unsigned int chanNum);\r
123 \r
124 void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
125 \r
126 /** To Register the ISRs with the underlying OS, if required. */\r
127 void registerEdma3Interrupts (unsigned int edma3Id)\r
128 {\r
129 static UInt32 cookie = 0;\r
130 unsigned int numTc = 0;\r
131 \r
132 IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);\r
133 IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);\r
134 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);\r
135 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);\r
136 \r
137 Hwi_Params hwiParams; \r
138 Error_Block eb;\r
139 \r
140 /* Initialize the Error Block */\r
141 Error_init(&eb);\r
142 \r
143 /* Disabling the global interrupts */\r
144 cookie = Hwi_disable();\r
145 \r
146 /* Initialize the HWI parameters with user specified values */\r
147 Hwi_Params_init(&hwiParams);\r
148 \r
149 /* argument for the ISR */\r
150 hwiParams.arg = edma3Id;\r
151 /* set the priority ID */\r
152 //hwiParams.priority = hwIntXferComp[edma3Id];\r
153 \r
154 hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],\r
155 ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),\r
156 (const Hwi_Params *) (&hwiParams),\r
157 &eb);\r
158 if (TRUE == Error_check(&eb))\r
159 {\r
160 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
161 }\r
162 \r
163 /* Initialize the HWI parameters with user specified values */\r
164 Hwi_Params_init(&hwiParams);\r
165 /* argument for the ISR */\r
166 hwiParams.arg = edma3Id;\r
167 /* set the priority ID */\r
168 //hwiParams.priority = hwIntCcErr[edma3Id];\r
169 \r
170 hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
171 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),\r
172 (const Hwi_Params *) (&hwiParams),\r
173 &eb);\r
174 \r
175 if (TRUE == Error_check(&eb))\r
176 {\r
177 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
178 }\r
179 \r
180 while (numTc < numEdma3Tc[edma3Id])\r
181 {\r
182 /* Initialize the HWI parameters with user specified values */\r
183 Hwi_Params_init(&hwiParams);\r
184 /* argument for the ISR */\r
185 hwiParams.arg = edma3Id;\r
186 /* set the priority ID */\r
187 //hwiParams.priority = hwIntTcErr[edma3Id];\r
188 \r
189 hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
190 (ptrEdma3TcIsrHandler[numTc]),\r
191 (const Hwi_Params *) (&hwiParams),\r
192 &eb);\r
193 if (TRUE == Error_check(&eb))\r
194 {\r
195 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
196 }\r
197 numTc++;\r
198 }\r
199 \r
200 Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
201 Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);\r
202 numTc = 0;\r
203 while (numTc < numEdma3Tc[edma3Id])\r
204 {\r
205 Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
206 numTc++;\r
207 }\r
208 /* Restore interrupts */\r
209 Hwi_restore(cookie);\r
210 }\r
211 \r
212 /** To Unregister the ISRs with the underlying OS, if previously registered. */\r
213 void unregisterEdma3Interrupts (unsigned int edma3Id)\r
214 {\r
215 static UInt32 cookie = 0;\r
216 unsigned int numTc = 0;\r
217 \r
218 /* Disabling the global interrupts */\r
219 cookie = Hwi_disable();\r
220 \r
221 Hwi_delete(&hwiCCXferCompInt);\r
222 Hwi_delete(&hwiCCErrInt);\r
223 while (numTc < numEdma3Tc[edma3Id])\r
224 {\r
225 Hwi_delete(&hwiTCErrInt[numTc]);\r
226 numTc++;\r
227 }\r
228 /* Restore interrupts */\r
229 Hwi_restore(cookie);\r
230 }\r
231 \r
232 /**\r
233 * \brief sampleMapXbarEvtToChan\r
234 *\r
235 * This function reads from the sample configuration structure which specifies \r
236 * cross bar events mapped to DMA channel.\r
237 *\r
238 * \return EDMA3_DRV_SOK if success, else error code\r
239 */\r
240 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
241 unsigned int *chanNum,\r
242 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
243 {\r
244 EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
245 unsigned int xbarEvtNum = 0;\r
246 int edmaChanNum = 0;\r
247 \r
248 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
249 (chanNum != NULL) &&\r
250 (edmaGblXbarConfig != NULL))\r
251 {\r
252 xbarEvtNum = eventNum - EDMA3_NUM_TCC;\r
253 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];\r
254 if (edmaChanNum != -1)\r
255 {\r
256 *chanNum = edmaChanNum;\r
257 edma3Result = EDMA3_DRV_SOK;\r
258 }\r
259 }\r
260 return (edma3Result);\r
261 }\r
262 \r
263 \r
264 /**\r
265 * \brief sampleConfigScr\r
266 *\r
267 * This function configures control config registers for the cross bar events \r
268 * mapped to the EDMA channel.\r
269 *\r
270 * \return EDMA3_DRV_SOK if success, else error code\r
271 */\r
272 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
273 unsigned int chanNum)\r
274 {\r
275 EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
276 unsigned int scrChanOffset = 0;\r
277 unsigned int scrRegOffset = 0;\r
278 unsigned int xBarEvtNum = 0;\r
279 CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);\r
280 \r
281 \r
282 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
283 (chanNum < EDMA3_NUM_TCC))\r
284 {\r
285 scrRegOffset = chanNum / 2;\r
286 scrChanOffset = chanNum - (scrRegOffset * 2);\r
287 xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;\r
288 \r
289 switch(scrChanOffset)\r
290 {\r
291 case 0:\r
292 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
293 (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
294 break;\r
295 case 1:\r
296 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
297 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
298 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
299 break;\r
300 default:\r
301 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
302 break;\r
303 }\r
304 }\r
305 else\r
306 {\r
307 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
308 }\r
309 return edma3Result;\r
310 }\r
311 \r
312 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
313 unsigned int edma3Id)\r
314 {\r
315 EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
316 const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
317 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);\r
318 if (hEdma != NULL)\r
319 {\r
320 retVal = EDMA3_DRV_initXbarEventMap(hEdma, \r
321 sampleXbarToChanConfig, \r
322 (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan, \r
323 (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);\r
324 }\r
325 \r
326 return retVal;\r
327 }\r
328 \r
329 void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
330 {\r
331 printf("memory Protection error");\r
332 }\r