ba2e01154f96c93763af31548532e4c2cd495dd9
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_arm_int_reg.c
1 /*\r
2 * sample_tda2xx_int_reg.c\r
3 *\r
4 * Platform specific interrupt registration and un-registration routines.\r
5 *\r
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7 *\r
8 *\r
9 * Redistribution and use in source and binary forms, with or without\r
10 * modification, are permitted provided that the following conditions\r
11 * are met:\r
12 *\r
13 * Redistributions of source code must retain the above copyright\r
14 * notice, this list of conditions and the following disclaimer.\r
15 *\r
16 * Redistributions in binary form must reproduce the above copyright\r
17 * notice, this list of conditions and the following disclaimer in the\r
18 * documentation and/or other materials provided with the\r
19 * distribution.\r
20 *\r
21 * Neither the name of Texas Instruments Incorporated nor the names of\r
22 * its contributors may be used to endorse or promote products derived\r
23 * from this software without specific prior written permission.\r
24 *\r
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36 *\r
37 */\r
38 \r
39 #include <ti/sysbios/knl/Semaphore.h>\r
40 #include <ti/sysbios/hal/Hwi.h>\r
41 #include <ti/sysbios/family/shared/vayu/IntXbar.h>\r
42 #include <ti/sysbios/family/arm/a15/Mmu.h>\r
43 #include <xdc/runtime/Error.h>\r
44 #include <xdc/runtime/System.h>\r
45 \r
46 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
47 \r
48 /**\r
49 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user\r
50 * (Not all TC error ISRs need to be registered, register only for the\r
51 * available Transfer Controllers).\r
52 */\r
53 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =\r
54 {\r
55 &lisrEdma3TC0ErrHandler0,\r
56 &lisrEdma3TC1ErrHandler0,\r
57 &lisrEdma3TC2ErrHandler0,\r
58 &lisrEdma3TC3ErrHandler0,\r
59 &lisrEdma3TC4ErrHandler0,\r
60 &lisrEdma3TC5ErrHandler0,\r
61 &lisrEdma3TC6ErrHandler0,\r
62 &lisrEdma3TC7ErrHandler0,\r
63 };\r
64 \r
65 extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
66 extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];\r
67 extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
68 extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];\r
69 extern uint32_t ccXferCompIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
70 extern uint32_t ccCompEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
71 extern uint32_t ccErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES];\r
72 extern uint32_t ccErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES];\r
73 extern uint32_t tcErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
74 extern uint32_t tcErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
75 \r
76 /**\r
77 * Variables which will be used internally for referring the hardware interrupt\r
78 * for various EDMA3 interrupts.\r
79 */\r
80 extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];\r
81 extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
82 extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
83 \r
84 extern uint32_t dsp_num;\r
85 /* This variable has to be used as an extern */\r
86 uint32_t gpp_num = 0;\r
87 \r
88 Hwi_Handle hwiCCXferCompInt;\r
89 Hwi_Handle hwiCCErrInt;\r
90 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];\r
91 \r
92 /* External Instance Specific Configuration Structure */\r
93 extern EDMA3_DRV_GblXbarToChanConfigParams \r
94 sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
95 \r
96 typedef struct {\r
97 volatile Uint32 TPCC_EVTMUX[32];\r
98 } CSL_IntmuxRegs;\r
99 \r
100 typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;\r
101 \r
102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
105 \r
106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
109 \r
110 \r
111 #define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127u)\r
112 #define EDMA3_NUM_TCC (64u)\r
113 \r
114 #define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)\r
115 /*\r
116 * Forward decleration\r
117 */\r
118 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,\r
119 uint32_t *chanNum,\r
120 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
121 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,\r
122 uint32_t chanNum);\r
123 \r
124 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
125 uint32_t edma3Id);\r
126 \r
127 /** To Register the ISRs with the underlying OS, if required. */\r
128 void registerEdma3Interrupts (uint32_t edma3Id);\r
129 /** To Unregister the ISRs with the underlying OS, if previously registered. */\r
130 void unregisterEdma3Interrupts (uint32_t edma3Id);\r
131 \r
132 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);\r
133 \r
134 /** To Register the ISRs with the underlying OS, if required. */\r
135 void registerEdma3Interrupts (uint32_t edma3Id)\r
136 {\r
137 static UInt32 cookie = 0;\r
138 uint32_t numTc = 0;\r
139 \r
140 /*\r
141 * Skip these interrupt xbar configuration.\r
142 * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.\r
143 */\r
144 if ((edma3Id != 2U) && (dsp_num != 1U))\r
145 {\r
146 IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);\r
147 IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);\r
148 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);\r
149 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);\r
150 }\r
151 \r
152 Hwi_Params hwiParams; \r
153 Error_Block eb;\r
154 \r
155 /* Initialize the Error Block */\r
156 Error_init(&eb);\r
157 \r
158 /* Disabling the global interrupts */\r
159 cookie = Hwi_disable();\r
160 \r
161 /* Initialize the HWI parameters with user specified values */\r
162 Hwi_Params_init(&hwiParams);\r
163 \r
164 /* argument for the ISR */\r
165 hwiParams.arg = edma3Id;\r
166 /* set the priority ID */\r
167 /* hwiParams.priority = hwIntXferComp[edma3Id]; */\r
168 \r
169 hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],\r
170 ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),\r
171 (const Hwi_Params *) (&hwiParams),\r
172 &eb);\r
173 if ((bool)TRUE == Error_check(&eb))\r
174 {\r
175 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
176 }\r
177 \r
178 /* Initialize the HWI parameters with user specified values */\r
179 Hwi_Params_init(&hwiParams);\r
180 /* argument for the ISR */\r
181 hwiParams.arg = edma3Id;\r
182 /* set the priority ID */\r
183 /* hwiParams.priority = hwIntCcErr[edma3Id]; */\r
184 \r
185 hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
186 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),\r
187 (const Hwi_Params *) (&hwiParams),\r
188 &eb);\r
189 \r
190 if ((bool)TRUE == Error_check(&eb))\r
191 {\r
192 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
193 }\r
194 \r
195 while (numTc < numEdma3Tc[edma3Id])\r
196 {\r
197 /* Initialize the HWI parameters with user specified values */\r
198 Hwi_Params_init(&hwiParams);\r
199 /* argument for the ISR */\r
200 hwiParams.arg = edma3Id;\r
201 /* set the priority ID */\r
202 /* hwiParams.priority = hwIntTcErr[edma3Id]; */\r
203 \r
204 hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
205 (ptrEdma3TcIsrHandler[numTc]),\r
206 (const Hwi_Params *) (&hwiParams),\r
207 &eb);\r
208 if ((bool)TRUE == Error_check(&eb))\r
209 {\r
210 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
211 }\r
212 numTc++;\r
213 }\r
214 \r
215 Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
216 Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);\r
217 numTc = 0;\r
218 while (numTc < numEdma3Tc[edma3Id])\r
219 {\r
220 Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
221 numTc++;\r
222 }\r
223 /* Restore interrupts */\r
224 Hwi_restore(cookie);\r
225 }\r
226 \r
227 /** To Unregister the ISRs with the underlying OS, if previously registered. */\r
228 void unregisterEdma3Interrupts (uint32_t edma3Id)\r
229 {\r
230 static UInt32 cookiee = 0;\r
231 uint32_t numTc = 0;\r
232 \r
233 /* Disabling the global interrupts */\r
234 cookiee = Hwi_disable();\r
235 \r
236 Hwi_delete(&hwiCCXferCompInt);\r
237 Hwi_delete(&hwiCCErrInt);\r
238 while (numTc < numEdma3Tc[edma3Id])\r
239 {\r
240 Hwi_delete(&hwiTCErrInt[numTc]);\r
241 numTc++;\r
242 }\r
243 /* Restore interrupts */\r
244 Hwi_restore(cookiee);\r
245 }\r
246 \r
247 /**\r
248 * \brief sampleMapXbarEvtToChan\r
249 *\r
250 * This function reads from the sample configuration structure which specifies \r
251 * cross bar events mapped to DMA channel.\r
252 *\r
253 * \return EDMA3_DRV_SOK if success, else error code\r
254 */\r
255 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,\r
256 uint32_t *chanNum,\r
257 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
258 {\r
259 EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
260 uint32_t xbarEvtNum = 0;\r
261 int32_t edmaChanNum = 0;\r
262 \r
263 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
264 (chanNum != NULL) &&\r
265 (edmaGblXbarConfig != NULL))\r
266 {\r
267 xbarEvtNum = eventNum - EDMA3_NUM_TCC;\r
268 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];\r
269 if (edmaChanNum != -1)\r
270 {\r
271 *chanNum = edmaChanNum;\r
272 edma3Result = EDMA3_DRV_SOK;\r
273 }\r
274 }\r
275 return (edma3Result);\r
276 }\r
277 \r
278 \r
279 /**\r
280 * \brief sampleConfigScr\r
281 *\r
282 * This function configures control config registers for the cross bar events \r
283 * mapped to the EDMA channel.\r
284 *\r
285 * \return EDMA3_DRV_SOK if success, else error code\r
286 */\r
287 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,\r
288 uint32_t chanNum)\r
289 {\r
290 EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
291 uint32_t scrChanOffset = 0;\r
292 uint32_t scrRegOffset = 0;\r
293 uint32_t xBarEvtNum = 0;\r
294 CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);\r
295 \r
296 \r
297 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
298 (chanNum < EDMA3_NUM_TCC))\r
299 {\r
300 scrRegOffset = chanNum / 2U;\r
301 scrChanOffset = chanNum - (scrRegOffset * 2U);\r
302 xBarEvtNum = eventNum + 1U;\r
303 \r
304 switch(scrChanOffset)\r
305 {\r
306 case 0:\r
307 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
308 (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
309 break;\r
310 case 1U:\r
311 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
312 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
313 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
314 break;\r
315 default:\r
316 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
317 break;\r
318 }\r
319 }\r
320 else\r
321 {\r
322 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
323 }\r
324 return edma3Result;\r
325 }\r
326 \r
327 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
328 uint32_t edma3Id)\r
329 {\r
330 EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
331 const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
332 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);\r
333 if (hEdma != NULL)\r
334 {\r
335 retVal = EDMA3_DRV_initXbarEventMap(hEdma, \r
336 sampleXbarToChanConfig, \r
337 (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan, \r
338 (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);\r
339 }\r
340 \r
341 return retVal;\r
342 }\r
343 \r
344 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)\r
345 {\r
346 #ifdef EDMA3_DRV_DEBUG\r
347 /* Added to fix Misra C error */\r
348 printf("memory Protection error");\r
349 #endif\r
350 }\r