[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_arm_int_reg.c
1 /*\r
2 * sample_tda2xx_int_reg.c\r
3 *\r
4 * Platform specific interrupt registration and un-registration routines.\r
5 *\r
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7 *\r
8 *\r
9 * Redistribution and use in source and binary forms, with or without\r
10 * modification, are permitted provided that the following conditions\r
11 * are met:\r
12 *\r
13 * Redistributions of source code must retain the above copyright\r
14 * notice, this list of conditions and the following disclaimer.\r
15 *\r
16 * Redistributions in binary form must reproduce the above copyright\r
17 * notice, this list of conditions and the following disclaimer in the\r
18 * documentation and/or other materials provided with the\r
19 * distribution.\r
20 *\r
21 * Neither the name of Texas Instruments Incorporated nor the names of\r
22 * its contributors may be used to endorse or promote products derived\r
23 * from this software without specific prior written permission.\r
24 *\r
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36 *\r
37 */\r
38 \r
39 #include <ti/sysbios/knl/Semaphore.h>\r
40 #include <ti/sysbios/hal/Hwi.h>\r
41 #include <ti/sysbios/hal/vayu/IntXbar.h>\r
42 #include <ti/sysbios/family/arm/a15/Mmu.h>\r
43 #include <xdc/runtime/Error.h>\r
44 #include <xdc/runtime/System.h>\r
45 \r
46 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
47 \r
48 /**\r
49 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user\r
50 * (Not all TC error ISRs need to be registered, register only for the\r
51 * available Transfer Controllers).\r
52 */\r
53 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =\r
54 {\r
55 &lisrEdma3TC0ErrHandler0,\r
56 &lisrEdma3TC1ErrHandler0,\r
57 &lisrEdma3TC2ErrHandler0,\r
58 &lisrEdma3TC3ErrHandler0,\r
59 &lisrEdma3TC4ErrHandler0,\r
60 &lisrEdma3TC5ErrHandler0,\r
61 &lisrEdma3TC6ErrHandler0,\r
62 &lisrEdma3TC7ErrHandler0,\r
63 };\r
64 \r
65 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
66 extern unsigned int ccErrorInt[];\r
67 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
68 extern unsigned int numEdma3Tc[];\r
69 extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];\r
70 extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];\r
71 extern unsigned int ccErrorIntXbarInstNo[];\r
72 extern unsigned int ccErrEdmaXbarIndex[];\r
73 extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];\r
74 extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];\r
75 \r
76 /**\r
77 * Variables which will be used internally for referring the hardware interrupt\r
78 * for various EDMA3 interrupts.\r
79 */\r
80 extern unsigned int hwIntXferComp[];\r
81 extern unsigned int hwIntCcErr[];\r
82 extern unsigned int hwIntTcErr[];\r
83 \r
84 extern unsigned int dsp_num;\r
85 /* This variable has to be used as an extern */\r
86 unsigned int gpp_num = 0;\r
87 \r
88 Hwi_Handle hwiCCXferCompInt;\r
89 Hwi_Handle hwiCCErrInt;\r
90 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];\r
91 \r
92 /* External Instance Specific Configuration Structure */\r
93 extern EDMA3_DRV_GblXbarToChanConfigParams \r
94 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
95 \r
96 typedef struct {\r
97 volatile Uint32 TPCC_EVTMUX[32];\r
98 } CSL_IntmuxRegs;\r
99 \r
100 typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;\r
101 \r
102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
105 \r
106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
109 \r
110 \r
111 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)\r
112 #define EDMA3_NUM_TCC (64u)\r
113 /*\r
114 * Forward decleration\r
115 */\r
116 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
117 unsigned int *chanNum,\r
118 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
119 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
120 unsigned int chanNum);\r
121 \r
122 void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
123 \r
124 /** To Register the ISRs with the underlying OS, if required. */\r
125 void registerEdma3Interrupts (unsigned int edma3Id)\r
126 {\r
127 static UInt32 cookie = 0;\r
128 unsigned int numTc = 0;\r
129 \r
130 IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);\r
131 IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);\r
132 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);\r
133 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);\r
134 \r
135 Hwi_Params hwiParams; \r
136 Error_Block eb;\r
137 \r
138 /* Initialize the Error Block */\r
139 Error_init(&eb);\r
140 \r
141 /* Disabling the global interrupts */\r
142 cookie = Hwi_disable();\r
143 \r
144 /* Initialize the HWI parameters with user specified values */\r
145 Hwi_Params_init(&hwiParams);\r
146 \r
147 /* argument for the ISR */\r
148 hwiParams.arg = edma3Id;\r
149 /* set the priority ID */\r
150 //hwiParams.priority = hwIntXferComp[edma3Id];\r
151 \r
152 hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],\r
153 (&lisrEdma3ComplHandler0),\r
154 (const Hwi_Params *) (&hwiParams),\r
155 &eb);\r
156 if (TRUE == Error_check(&eb))\r
157 {\r
158 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
159 }\r
160 \r
161 /* Initialize the HWI parameters with user specified values */\r
162 Hwi_Params_init(&hwiParams);\r
163 /* argument for the ISR */\r
164 hwiParams.arg = edma3Id;\r
165 /* set the priority ID */\r
166 //hwiParams.priority = hwIntCcErr[edma3Id];\r
167 \r
168 hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
169 (&lisrEdma3CCErrHandler0),\r
170 (const Hwi_Params *) (&hwiParams),\r
171 &eb);\r
172 \r
173 if (TRUE == Error_check(&eb))\r
174 {\r
175 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
176 }\r
177 \r
178 while (numTc < numEdma3Tc[edma3Id])\r
179 {\r
180 /* Initialize the HWI parameters with user specified values */\r
181 Hwi_Params_init(&hwiParams);\r
182 /* argument for the ISR */\r
183 hwiParams.arg = edma3Id;\r
184 /* set the priority ID */\r
185 //hwiParams.priority = hwIntTcErr[edma3Id];\r
186 \r
187 hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
188 (ptrEdma3TcIsrHandler[numTc]),\r
189 (const Hwi_Params *) (&hwiParams),\r
190 &eb);\r
191 if (TRUE == Error_check(&eb))\r
192 {\r
193 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
194 }\r
195 numTc++;\r
196 }\r
197 \r
198 Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
199 Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);\r
200 numTc = 0;\r
201 while (numTc < numEdma3Tc[edma3Id])\r
202 {\r
203 Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
204 numTc++;\r
205 }\r
206 /* Restore interrupts */\r
207 Hwi_restore(cookie);\r
208 }\r
209 \r
210 /** To Unregister the ISRs with the underlying OS, if previously registered. */\r
211 void unregisterEdma3Interrupts (unsigned int edma3Id)\r
212 {\r
213 static UInt32 cookie = 0;\r
214 unsigned int numTc = 0;\r
215 \r
216 /* Disabling the global interrupts */\r
217 cookie = Hwi_disable();\r
218 \r
219 Hwi_delete(&hwiCCXferCompInt);\r
220 Hwi_delete(&hwiCCErrInt);\r
221 while (numTc < numEdma3Tc[edma3Id])\r
222 {\r
223 Hwi_delete(&hwiTCErrInt[numTc]);\r
224 numTc++;\r
225 }\r
226 /* Restore interrupts */\r
227 Hwi_restore(cookie);\r
228 }\r
229 \r
230 /**\r
231 * \brief sampleMapXbarEvtToChan\r
232 *\r
233 * This function reads from the sample configuration structure which specifies \r
234 * cross bar events mapped to DMA channel.\r
235 *\r
236 * \return EDMA3_DRV_SOK if success, else error code\r
237 */\r
238 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
239 unsigned int *chanNum,\r
240 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
241 {\r
242 EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
243 unsigned int xbarEvtNum = 0;\r
244 int edmaChanNum = 0;\r
245 \r
246 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
247 (chanNum != NULL) &&\r
248 (edmaGblXbarConfig != NULL))\r
249 {\r
250 xbarEvtNum = eventNum - EDMA3_NUM_TCC;\r
251 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];\r
252 if (edmaChanNum != -1)\r
253 {\r
254 *chanNum = edmaChanNum;\r
255 edma3Result = EDMA3_DRV_SOK;\r
256 }\r
257 }\r
258 return (edma3Result);\r
259 }\r
260 \r
261 \r
262 /**\r
263 * \brief sampleConfigScr\r
264 *\r
265 * This function configures control config registers for the cross bar events \r
266 * mapped to the EDMA channel.\r
267 *\r
268 * \return EDMA3_DRV_SOK if success, else error code\r
269 */\r
270 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
271 unsigned int chanNum)\r
272 {\r
273 EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
274 unsigned int scrChanOffset = 0;\r
275 unsigned int scrRegOffset = 0;\r
276 unsigned int xBarEvtNum = 0;\r
277 CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);\r
278 \r
279 \r
280 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
281 (chanNum < EDMA3_NUM_TCC))\r
282 {\r
283 scrRegOffset = chanNum / 2;\r
284 scrChanOffset = chanNum - (scrRegOffset * 2);\r
285 xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;\r
286 \r
287 switch(scrChanOffset)\r
288 {\r
289 case 0:\r
290 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
291 (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
292 break;\r
293 case 1:\r
294 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
295 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
296 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
297 break;\r
298 default:\r
299 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
300 break;\r
301 }\r
302 }\r
303 else\r
304 {\r
305 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
306 }\r
307 return edma3Result;\r
308 }\r
309 \r
310 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
311 unsigned int edma3Id)\r
312 {\r
313 EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
314 const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
315 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);\r
316 if (hEdma != NULL)\r
317 {\r
318 retVal = EDMA3_DRV_initXbarEventMap(hEdma, \r
319 sampleXbarToChanConfig, \r
320 &sampleMapXbarEvtToChan, \r
321 &sampleConfigScr);\r
322 }\r
323 \r
324 return retVal;\r
325 }\r
326 \r
327 void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
328 {\r
329 printf("memory Protection error");\r
330 }\r