13743b483bb8f2a6ba9253b456732d5ef4663e74
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2 * sample_tda2xx_cfg.c\r
3 *\r
4 * SoC specific EDMA3 hardware related information like number of transfer\r
5 * controllers, various interrupt ids etc. It is used while interrupts\r
6 * enabling / disabling. It needs to be ported for different SoCs.\r
7 *\r
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9 *\r
10 *\r
11 * Redistribution and use in source and binary forms, with or without\r
12 * modification, are permitted provided that the following conditions\r
13 * are met:\r
14 *\r
15 * Redistributions of source code must retain the above copyright\r
16 * notice, this list of conditions and the following disclaimer.\r
17 *\r
18 * Redistributions in binary form must reproduce the above copyright\r
19 * notice, this list of conditions and the following disclaimer in the\r
20 * documentation and/or other materials provided with the\r
21 * distribution.\r
22 *\r
23 * Neither the name of Texas Instruments Incorporated nor the names of\r
24 * its contributors may be used to endorse or promote products derived\r
25 * from this software without specific prior written permission.\r
26 *\r
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38 *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
42 #ifdef BUILD_TDA2XX_IPU\r
43 #include <ti/sysbios/family/arm/ducati/Core.h> \r
44 \r
45 #endif\r
46 \r
47 /* Number of EDMA3 controllers present in the system */\r
48 #define NUM_EDMA3_INSTANCES 2u\r
49 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
50 \r
51 /* Number of DSPs present in the system */\r
52 #define NUM_DSPS 1u\r
53 const unsigned int numDsps = NUM_DSPS;\r
54 \r
55 /* Determine the processor id by reading DNUM register. */\r
56 /* Statically allocate the region numbers with cores. */\r
57 int myCoreNum;\r
58 #define PID0_ADDRESS 0xE00FFFE0\r
59 #define CORE_ID_C0 0x0\r
60 #define CORE_ID_C1 0x1\r
61 \r
62 unsigned short determineProcId()\r
63 {\r
64 unsigned short regionNo = numEdma3Instances;\r
65 #ifdef BUILD_TDA2XX_DSP\r
66 extern __cregister volatile unsigned int DNUM;\r
67 #endif\r
68 myCoreNum = numDsps;\r
69 #ifdef BUILD_TDA2XX_MPU\r
70 \r
71 asm (" push {r0-r2} \n\t"\r
72 " MRC p15, 0, r0, c0, c0, 5\n\t"\r
73 " LDR r1, =myCoreNum\n\t"\r
74 " STR r0, [r1]\n\t"\r
75 " pop {r0-r2}\n\t");\r
76 if((myCoreNum & 0x03) == 1)\r
77 regionNo = 1;\r
78 else\r
79 regionNo = 0;\r
80 #elif defined(BUILD_TDA2XX_IPU)\r
81 myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
82 if(Core_getIpuId() == 1){\r
83 if(myCoreNum == CORE_ID_C0)\r
84 regionNo = 4;\r
85 else if (myCoreNum == CORE_ID_C1)\r
86 regionNo = 5;\r
87 }\r
88 if(Core_getIpuId() == 2){\r
89 if(myCoreNum == CORE_ID_C0)\r
90 regionNo = 6;\r
91 else if (myCoreNum == CORE_ID_C1)\r
92 regionNo = 7;\r
93 }\r
94 #elif defined BUILD_TDA2XX_DSP\r
95 \r
96 myCoreNum = DNUM;\r
97 if(myCoreNum == 0)\r
98 regionNo = 2;\r
99 else\r
100 regionNo = 3;\r
101 #endif\r
102 return regionNo;\r
103 }\r
104 \r
105 signed char* getGlobalAddr(signed char* addr)\r
106 {\r
107 return (addr); /* The address is already a global address */\r
108 }\r
109 unsigned short isGblConfigRequired(unsigned int dspNum)\r
110 {\r
111 (void) dspNum;\r
112 return 1;\r
113 }\r
114 \r
115 /* Semaphore handles */\r
116 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
117 \r
118 /** Number of PaRAM Sets available */\r
119 #define EDMA3_NUM_PARAMSET (512u)\r
120 \r
121 /** Number of TCCS available */\r
122 #define EDMA3_NUM_TCC (64u)\r
123 \r
124 /** Number of DMA Channels available */\r
125 #define EDMA3_NUM_DMA_CHANNELS (64u)\r
126 \r
127 /** Number of QDMA Channels available */\r
128 #define EDMA3_NUM_QDMA_CHANNELS (8u)\r
129 \r
130 /** Number of Event Queues available */\r
131 #define EDMA3_NUM_EVTQUE (4u)\r
132 \r
133 /** Number of Transfer Controllers available */\r
134 #define EDMA3_NUM_TC (2u)\r
135 \r
136 /** Number of Regions */\r
137 #define EDMA3_NUM_REGIONS (8u)\r
138 \r
139 /** Interrupt no. for Transfer Completion */\r
140 #define EDMA3_CC_XFER_COMPLETION_INT_A15 (66u)\r
141 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u)\r
142 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u)\r
143 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u)\r
144 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
145 #define COMPLETION_INT_A15_XBAR_INST_NO (29u)\r
146 #define COMPLETION_INT_DSP_XBAR_INST_NO (7u)\r
147 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u)\r
148 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u)\r
149 \r
150 /** Interrupt no. for CC Error */\r
151 #define EDMA3_CC_ERROR_INT_A15 (67u)\r
152 #define EDMA3_CC_ERROR_INT_DSP (39u)\r
153 #define EDMA3_CC_ERROR_INT_IPU (35u)\r
154 \r
155 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
156 #define CC_ERROR_INT_A15_XBAR_INST_NO (30u)\r
157 #define CC_ERROR_INT_DSP_XBAR_INST_NO (8u)\r
158 #define CC_ERROR_INT_IPU_XBAR_INST_NO (13u)\r
159 \r
160 /** Interrupt no. for TCs Error */\r
161 #define EDMA3_TC0_ERROR_INT_A15 (68u)\r
162 #define EDMA3_TC0_ERROR_INT_DSP (40u)\r
163 #define EDMA3_TC0_ERROR_INT_IPU (36u)\r
164 #define EDMA3_TC1_ERROR_INT_A15 (69u)\r
165 #define EDMA3_TC1_ERROR_INT_DSP (41u)\r
166 #define EDMA3_TC1_ERROR_INT_IPU (37u)\r
167 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
168 #define TC0_ERROR_INT_A15_XBAR_INST_NO (31u)\r
169 #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u)\r
170 #define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u)\r
171 #define TC1_ERROR_INT_A15_XBAR_INST_NO (32u)\r
172 #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u)\r
173 #define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)\r
174 \r
175 #ifdef BUILD_TDA2XX_MPU\r
176 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15\r
177 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A15\r
178 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_A15_XBAR_INST_NO\r
179 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A15\r
180 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A15\r
181 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
182 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
183 \r
184 #elif defined BUILD_TDA2XX_DSP\r
185 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP\r
186 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP\r
187 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_DSP_XBAR_INST_NO\r
188 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP\r
189 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP\r
190 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_DSP_XBAR_INST_NO\r
191 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_DSP_XBAR_INST_NO\r
192 \r
193 #elif defined BUILD_TDA2XX_IPU\r
194 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU_C0\r
195 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU\r
196 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU_XBAR_INST_NO\r
197 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU\r
198 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU\r
199 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU_XBAR_INST_NO\r
200 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU_XBAR_INST_NO\r
201 \r
202 #else\r
203 #define EDMA3_CC_XFER_COMPLETION_INT (0u)\r
204 #define EDMA3_CC_ERROR_INT (0u)\r
205 #define CC_ERROR_INT_XBAR_INST_NO (0u)\r
206 #define EDMA3_TC0_ERROR_INT (0u)\r
207 #define EDMA3_TC1_ERROR_INT (0u)\r
208 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
209 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
210 #endif\r
211 \r
212 #define EDMA3_TC2_ERROR_INT (0u)\r
213 #define EDMA3_TC3_ERROR_INT (0u)\r
214 #define EDMA3_TC4_ERROR_INT (0u)\r
215 #define EDMA3_TC5_ERROR_INT (0u)\r
216 #define EDMA3_TC6_ERROR_INT (0u)\r
217 #define EDMA3_TC7_ERROR_INT (0u)\r
218 \r
219 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19u)\r
220 #define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20u)\r
221 #define DSP1_EDMA3_CC_ERROR_INT (27u)\r
222 #define DSP1_EDMA3_TC0_ERROR_INT (28u)\r
223 #define DSP1_EDMA3_TC1_ERROR_INT (29u)\r
224 \r
225 /** XBAR interrupt source index numbers for EDMA interrupts */\r
226 #define XBAR_EDMA_TPCC_IRQ_REGION0 (361u)\r
227 #define XBAR_EDMA_TPCC_IRQ_REGION1 (362u)\r
228 #define XBAR_EDMA_TPCC_IRQ_REGION2 (363u)\r
229 #define XBAR_EDMA_TPCC_IRQ_REGION3 (364u)\r
230 #define XBAR_EDMA_TPCC_IRQ_REGION4 (365u)\r
231 #define XBAR_EDMA_TPCC_IRQ_REGION5 (366u)\r
232 #define XBAR_EDMA_TPCC_IRQ_REGION6 (367u)\r
233 #define XBAR_EDMA_TPCC_IRQ_REGION7 (368u)\r
234 \r
235 #define XBAR_EDMA_TPCC_IRQ_ERR (359u)\r
236 #define XBAR_EDMA_TC0_IRQ_ERR (370u)\r
237 #define XBAR_EDMA_TC1_IRQ_ERR (371u)\r
238 \r
239 /**\r
240 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
241 * ECM events (SoC specific). These ECM events come\r
242 * under ECM block XXX (handling those specific ECM events). Normally, block\r
243 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
244 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
245 * is mapped to a specific HWI_INT YYY in the tcf file.\r
246 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
247 * to transfer completion interrupt.\r
248 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
249 * to CC error interrupts.\r
250 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
251 * to TC error interrupts.\r
252 */\r
253 /* EDMA 0 */\r
254 \r
255 #define EDMA3_HWI_INT_XFER_COMP (7u)\r
256 #define EDMA3_HWI_INT_CC_ERR (7u)\r
257 #define EDMA3_HWI_INT_TC0_ERR (10u)\r
258 #define EDMA3_HWI_INT_TC1_ERR (10u)\r
259 #define EDMA3_HWI_INT_TC2_ERR (10u)\r
260 #define EDMA3_HWI_INT_TC3_ERR (10u)\r
261 \r
262 /**\r
263 * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
264 * various peripherals, which use EDMA for data transfer.\r
265 * All channels need not be mapped, some can be free also.\r
266 * 1: Mapped\r
267 * 0: Not mapped\r
268 *\r
269 * This mapping will be used to allocate DMA channels when user passes\r
270 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
271 * copy). The same mapping is used to allocate the TCC when user passes\r
272 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
273 * \r
274 * For Vayu Since the xbar can be used to map event to any EDMA channel,\r
275 * If the application is assigning events to other channel this variable \r
276 * should be modified\r
277 *\r
278 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
279 */\r
280 /* 31 0 */\r
281 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA (0x3FC0C06Eu) /* TBD */\r
282 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFu) /* TBD */\r
283 \r
284 \r
285 /**\r
286 * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
287 * various peripherals, which use EDMA for data transfer.\r
288 * All channels need not be mapped, some can be free also.\r
289 * 1: Mapped\r
290 * 0: Not mapped\r
291 *\r
292 * This mapping will be used to allocate DMA channels when user passes\r
293 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
294 * copy). The same mapping is used to allocate the TCC when user passes\r
295 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
296 *\r
297 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
298 */\r
299 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA (0xF3FFFFF8u) /* TBD */\r
300 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000u) /* TBD */\r
301 \r
302 \r
303 /* Variable which will be used internally for referring number of Event Queues*/\r
304 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {\r
305 EDMA3_NUM_EVTQUE,\r
306 };\r
307 \r
308 /* Variable which will be used internally for referring number of TCs. */\r
309 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
310 EDMA3_NUM_TC,\r
311 };\r
312 \r
313 /**\r
314 * Variable which will be used internally for referring transfer completion\r
315 * interrupt.\r
316 */\r
317 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
318 {\r
319 {\r
320 EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_A15,\r
321 EDMA3_CC_XFER_COMPLETION_INT_DSP, EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
322 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
323 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
324 },\r
325 {\r
326 0u, 0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
327 0u, 0u, 0u, 0u,\r
328 },\r
329 };\r
330 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
331 unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
332 {\r
333 {\r
334 COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_A15_XBAR_INST_NO,\r
335 COMPLETION_INT_DSP_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO,\r
336 COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
337 COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
338 },\r
339 };\r
340 \r
341 /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
342 unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
343 {\r
344 {\r
345 XBAR_EDMA_TPCC_IRQ_REGION0, XBAR_EDMA_TPCC_IRQ_REGION1, XBAR_EDMA_TPCC_IRQ_REGION2, XBAR_EDMA_TPCC_IRQ_REGION3,\r
346 XBAR_EDMA_TPCC_IRQ_REGION4, XBAR_EDMA_TPCC_IRQ_REGION5, XBAR_EDMA_TPCC_IRQ_REGION6, XBAR_EDMA_TPCC_IRQ_REGION7,\r
347 }\r
348 };\r
349 \r
350 /**\r
351 * Variable which will be used internally for referring channel controller's\r
352 * error interrupt.\r
353 */\r
354 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
355 EDMA3_CC_ERROR_INT,DSP1_EDMA3_CC_ERROR_INT,\r
356 };\r
357 unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] = {\r
358 CC_ERROR_INT_XBAR_INST_NO,\r
359 };\r
360 unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
361 {\r
362 XBAR_EDMA_TPCC_IRQ_ERR,\r
363 };\r
364 \r
365 /**\r
366 * Variable which will be used internally for referring transfer controllers'\r
367 * error interrupts.\r
368 */\r
369 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
370 {\r
371 {\r
372 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
373 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
374 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
375 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
376 },\r
377 {\r
378 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
379 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
380 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
381 DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
382 }\r
383 };\r
384 unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =\r
385 {\r
386 {\r
387 TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
388 0u, 0u,\r
389 0u, 0u,\r
390 0u, 0u,\r
391 }\r
392 };\r
393 \r
394 unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][8] =\r
395 {\r
396 {\r
397 XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
398 0u, 0u,\r
399 0u, 0u, 0u, 0u,\r
400 }\r
401 };\r
402 \r
403 \r
404 /**\r
405 * Variables which will be used internally for referring the hardware interrupt\r
406 * for various EDMA3 interrupts.\r
407 */\r
408 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
409 EDMA3_HWI_INT_XFER_COMP, EDMA3_HWI_INT_XFER_COMP,\r
410 };\r
411 \r
412 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
413 EDMA3_HWI_INT_CC_ERR, EDMA3_HWI_INT_CC_ERR,\r
414 };\r
415 \r
416 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
417 {\r
418 EDMA3_HWI_INT_TC0_ERR,\r
419 EDMA3_HWI_INT_TC1_ERR,\r
420 EDMA3_HWI_INT_TC2_ERR,\r
421 EDMA3_HWI_INT_TC3_ERR\r
422 },\r
423 {\r
424 EDMA3_HWI_INT_TC0_ERR,\r
425 EDMA3_HWI_INT_TC1_ERR,\r
426 EDMA3_HWI_INT_TC2_ERR,\r
427 EDMA3_HWI_INT_TC3_ERR\r
428 }\r
429 };\r
430 \r
431 /**\r
432 * \brief Base address as seen from the different cores may be different\r
433 * And is defined based on the core\r
434 */\r
435 #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
436 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))\r
437 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))\r
438 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))\r
439 #elif (defined BUILD_TDA2XX_IPU)\r
440 #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))\r
441 #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))\r
442 #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))\r
443 #else\r
444 #define EDMA3_CC_BASE_ADDR ((void *)(0x0))\r
445 #define EDMA3_TC0_BASE_ADDR ((void *)(0x0))\r
446 #define EDMA3_TC1_BASE_ADDR ((void *)(0x0))\r
447 #endif\r
448 \r
449 #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000))\r
450 #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000))\r
451 #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000))\r
452 \r
453 /* Driver Object Initialization Configuration */\r
454 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
455 {\r
456 {\r
457 /* EDMA3 INSTANCE# 0 */\r
458 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
459 EDMA3_NUM_DMA_CHANNELS,\r
460 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
461 EDMA3_NUM_QDMA_CHANNELS,\r
462 /** Total number of TCCs supported by the EDMA3 Controller */\r
463 EDMA3_NUM_TCC,\r
464 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
465 EDMA3_NUM_PARAMSET,\r
466 /** Total number of Event Queues in the EDMA3 Controller */\r
467 EDMA3_NUM_EVTQUE,\r
468 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
469 EDMA3_NUM_TC,\r
470 /** Number of Regions on this EDMA3 controller */\r
471 EDMA3_NUM_REGIONS,\r
472 \r
473 /**\r
474 * \brief Channel mapping existence\r
475 * A value of 0 (No channel mapping) implies that there is fixed association\r
476 * for a channel number to a parameter entry number or, in other words,\r
477 * PaRAM entry n corresponds to channel n.\r
478 */\r
479 1u,\r
480 \r
481 /** Existence of memory protection feature */\r
482 0u,\r
483 \r
484 /** Global Register Region of CC Registers */\r
485 EDMA3_CC_BASE_ADDR,\r
486 /** Transfer Controller (TC) Registers */\r
487 {\r
488 EDMA3_TC0_BASE_ADDR,\r
489 EDMA3_TC1_BASE_ADDR,\r
490 (void *)NULL,\r
491 (void *)NULL,\r
492 (void *)NULL,\r
493 (void *)NULL,\r
494 (void *)NULL,\r
495 (void *)NULL\r
496 },\r
497 /** Interrupt no. for Transfer Completion */\r
498 EDMA3_CC_XFER_COMPLETION_INT,\r
499 /** Interrupt no. for CC Error */\r
500 EDMA3_CC_ERROR_INT,\r
501 /** Interrupt no. for TCs Error */\r
502 {\r
503 EDMA3_TC0_ERROR_INT,\r
504 EDMA3_TC1_ERROR_INT,\r
505 EDMA3_TC2_ERROR_INT,\r
506 EDMA3_TC3_ERROR_INT,\r
507 EDMA3_TC4_ERROR_INT,\r
508 EDMA3_TC5_ERROR_INT,\r
509 EDMA3_TC6_ERROR_INT,\r
510 EDMA3_TC7_ERROR_INT\r
511 },\r
512 \r
513 /**\r
514 * \brief EDMA3 TC priority setting\r
515 *\r
516 * User can program the priority of the Event Queues\r
517 * at a system-wide level. This means that the user can set the\r
518 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
519 * relative to IO initiated by the other bus masters on the\r
520 * device (ARM, DSP, USB, etc)\r
521 */\r
522 {\r
523 0u,\r
524 1u,\r
525 0u,\r
526 0u,\r
527 0u,\r
528 0u,\r
529 0u,\r
530 0u\r
531 },\r
532 /**\r
533 * \brief To Configure the Threshold level of number of events\r
534 * that can be queued up in the Event queues. EDMA3CC error register\r
535 * (CCERR) will indicate whether or not at any instant of time the\r
536 * number of events queued up in any of the event queues exceeds\r
537 * or equals the threshold/watermark value that is set\r
538 * in the queue watermark threshold register (QWMTHRA).\r
539 */\r
540 {\r
541 16u,\r
542 16u,\r
543 0u,\r
544 0u,\r
545 0u,\r
546 0u,\r
547 0u,\r
548 0u\r
549 },\r
550 \r
551 /**\r
552 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
553 * An optimally-sized command is defined by the transfer controller\r
554 * default burst size (DBS). Different TCs can have different\r
555 * DBS values. It is defined in Bytes.\r
556 */\r
557 {\r
558 16u,\r
559 16u,\r
560 0u,\r
561 0u,\r
562 0u,\r
563 0u,\r
564 0u,\r
565 0u\r
566 },\r
567 \r
568 /**\r
569 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
570 * if it exists, otherwise of no use.\r
571 */\r
572 {\r
573 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
574 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
575 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
576 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
577 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
578 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
579 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
580 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
581 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
582 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
583 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
584 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
585 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
586 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
587 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
588 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
589 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
590 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
591 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
592 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
593 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
594 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
595 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
596 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
597 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
598 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
599 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
600 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
601 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
602 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
603 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
604 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
605 },\r
606 \r
607 /**\r
608 * \brief Mapping from each DMA channel to a TCC. This specific\r
609 * TCC code will be returned when the transfer is completed\r
610 * on the mapped channel.\r
611 */\r
612 {\r
613 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
614 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
615 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
616 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
617 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
618 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
619 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
620 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
621 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
622 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
623 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
624 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
625 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
626 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
627 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
628 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
629 },\r
630 \r
631 /**\r
632 * \brief Mapping of DMA channels to Hardware Events from\r
633 * various peripherals, which use EDMA for data transfer.\r
634 * All channels need not be mapped, some can be free also.\r
635 */\r
636 {\r
637 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,\r
638 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA\r
639 }\r
640 },\r
641 {\r
642 /* EDMA3 INSTANCE# 1 */\r
643 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
644 EDMA3_NUM_DMA_CHANNELS,\r
645 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
646 EDMA3_NUM_QDMA_CHANNELS,\r
647 /** Total number of TCCs supported by the EDMA3 Controller */\r
648 EDMA3_NUM_TCC,\r
649 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
650 EDMA3_NUM_PARAMSET,\r
651 /** Total number of Event Queues in the EDMA3 Controller */\r
652 EDMA3_NUM_EVTQUE,\r
653 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
654 EDMA3_NUM_TC,\r
655 /** Number of Regions on this EDMA3 controller */\r
656 EDMA3_NUM_REGIONS,\r
657 \r
658 /**\r
659 * \brief Channel mapping existence\r
660 * A value of 0 (No channel mapping) implies that there is fixed association\r
661 * for a channel number to a parameter entry number or, in other words,\r
662 * PaRAM entry n corresponds to channel n.\r
663 */\r
664 1u,\r
665 \r
666 /** Existence of memory protection feature */\r
667 0u,\r
668 \r
669 /** Global Register Region of CC Registers */\r
670 DSP1_EDMA3_CC_BASE_ADDR,\r
671 /** Transfer Controller (TC) Registers */\r
672 {\r
673 DSP1_EDMA3_TC0_BASE_ADDR,\r
674 DSP1_EDMA3_TC1_BASE_ADDR,\r
675 (void *)NULL,\r
676 (void *)NULL,\r
677 (void *)NULL,\r
678 (void *)NULL,\r
679 (void *)NULL,\r
680 (void *)NULL\r
681 },\r
682 /** Interrupt no. for Transfer Completion */\r
683 DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
684 /** Interrupt no. for CC Error */\r
685 DSP1_EDMA3_CC_ERROR_INT,\r
686 /** Interrupt no. for TCs Error */\r
687 {\r
688 DSP1_EDMA3_TC0_ERROR_INT,\r
689 DSP1_EDMA3_TC1_ERROR_INT,\r
690 EDMA3_TC2_ERROR_INT,\r
691 EDMA3_TC3_ERROR_INT,\r
692 EDMA3_TC4_ERROR_INT,\r
693 EDMA3_TC5_ERROR_INT,\r
694 EDMA3_TC6_ERROR_INT,\r
695 EDMA3_TC7_ERROR_INT\r
696 },\r
697 \r
698 /**\r
699 * \brief EDMA3 TC priority setting\r
700 *\r
701 * User can program the priority of the Event Queues\r
702 * at a system-wide level. This means that the user can set the\r
703 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
704 * relative to IO initiated by the other bus masters on the\r
705 * device (ARM, DSP, USB, etc)\r
706 */\r
707 {\r
708 0u,\r
709 1u,\r
710 0u,\r
711 0u,\r
712 0u,\r
713 0u,\r
714 0u,\r
715 0u\r
716 },\r
717 /**\r
718 * \brief To Configure the Threshold level of number of events\r
719 * that can be queued up in the Event queues. EDMA3CC error register\r
720 * (CCERR) will indicate whether or not at any instant of time the\r
721 * number of events queued up in any of the event queues exceeds\r
722 * or equals the threshold/watermark value that is set\r
723 * in the queue watermark threshold register (QWMTHRA).\r
724 */\r
725 {\r
726 16u,\r
727 16u,\r
728 0u,\r
729 0u,\r
730 0u,\r
731 0u,\r
732 0u,\r
733 0u\r
734 },\r
735 \r
736 /**\r
737 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
738 * An optimally-sized command is defined by the transfer controller\r
739 * default burst size (DBS). Different TCs can have different\r
740 * DBS values. It is defined in Bytes.\r
741 */\r
742 {\r
743 16u,\r
744 16u,\r
745 0u,\r
746 0u,\r
747 0u,\r
748 0u,\r
749 0u,\r
750 0u\r
751 },\r
752 \r
753 /**\r
754 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
755 * if it exists, otherwise of no use.\r
756 */\r
757 {\r
758 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
759 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
760 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
761 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
762 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
763 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
764 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
765 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
766 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
767 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
768 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
769 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
770 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
771 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
772 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
773 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
774 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
775 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
776 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
777 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
778 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
779 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
780 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
781 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
782 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
783 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
784 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
785 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
786 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
787 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
788 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
789 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
790 },\r
791 \r
792 /**\r
793 * \brief Mapping from each DMA channel to a TCC. This specific\r
794 * TCC code will be returned when the transfer is completed\r
795 * on the mapped channel.\r
796 */\r
797 {\r
798 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
799 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
800 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
801 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
802 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
803 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
804 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
805 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
806 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
807 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
808 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
809 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
810 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
811 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
812 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
813 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
814 },\r
815 \r
816 /**\r
817 * \brief Mapping of DMA channels to Hardware Events from\r
818 * various peripherals, which use EDMA for data transfer.\r
819 * All channels need not be mapped, some can be free also.\r
820 */\r
821 {\r
822 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
823 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
824 }\r
825 },\r
826 };\r
827 \r
828 /**\r
829 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
830 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
831 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
832 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
833 *\r
834 * Only Resources owned by a perticular core are allocated by Driver\r
835 * Reserved resources are not allocated if requested for any available resource\r
836 */\r
837 \r
838 /* Driver Instance Initialization Configuration */\r
839 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
840 {\r
841 /* EDMA3 INSTANCE# 0 */\r
842 {\r
843 /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
844 {\r
845 /* ownPaRAMSets */\r
846 /* 31 0 63 32 95 64 127 96 */\r
847 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
848 /* 159 128 191 160 223 192 255 224 */\r
849 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
850 /* 287 256 319 288 351 320 383 352 */\r
851 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
852 /* 415 384 447 416 479 448 511 480 */\r
853 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
854 \r
855 /* ownDmaChannels */\r
856 /* 31 0 63 32 */\r
857 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
858 \r
859 /* ownQdmaChannels */\r
860 /* 31 0 */\r
861 {0x000000FFu},\r
862 \r
863 /* ownTccs */\r
864 /* 31 0 63 32 */\r
865 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
866 \r
867 /* resvdPaRAMSets */\r
868 /* 31 0 63 32 95 64 127 96 */\r
869 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
870 /* 159 128 191 160 223 192 255 224 */\r
871 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
872 /* 287 256 319 288 351 320 383 352 */\r
873 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
874 /* 415 384 447 416 479 448 511 480 */\r
875 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
876 \r
877 /* resvdDmaChannels */\r
878 /* 31 0 63 32 */\r
879 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
880 \r
881 /* resvdQdmaChannels */\r
882 /* 31 0 */\r
883 {0x00u},\r
884 \r
885 /* resvdTccs */\r
886 /* 31 0 63 32 */\r
887 {0x00u, 0x00u},\r
888 },\r
889 \r
890 /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
891 {\r
892 /* ownPaRAMSets */\r
893 /* 31 0 63 32 95 64 127 96 */\r
894 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
895 /* 159 128 191 160 223 192 255 224 */\r
896 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
897 /* 287 256 319 288 351 320 383 352 */\r
898 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
899 /* 415 384 447 416 479 448 511 480 */\r
900 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
901 \r
902 /* ownDmaChannels */\r
903 /* 31 0 63 32 */\r
904 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
905 \r
906 /* ownQdmaChannels */\r
907 /* 31 0 */\r
908 {0x000000FFu},\r
909 \r
910 /* ownTccs */\r
911 /* 31 0 63 32 */\r
912 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
913 \r
914 /* resvdPaRAMSets */\r
915 /* 31 0 63 32 95 64 127 96 */\r
916 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
917 /* 159 128 191 160 223 192 255 224 */\r
918 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
919 /* 287 256 319 288 351 320 383 352 */\r
920 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
921 /* 415 384 447 416 479 448 511 480 */\r
922 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
923 \r
924 /* resvdDmaChannels */\r
925 /* 31 0 63 32 */\r
926 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
927 \r
928 /* resvdQdmaChannels */\r
929 /* 31 0 */\r
930 {0x00u},\r
931 \r
932 /* resvdTccs */\r
933 /* 31 0 63 32 */\r
934 {0x00u, 0x00u},\r
935 },\r
936 \r
937 /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
938 {\r
939 /* ownPaRAMSets */\r
940 /* 31 0 63 32 95 64 127 96 */\r
941 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
942 /* 159 128 191 160 223 192 255 224 */\r
943 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
944 /* 287 256 319 288 351 320 383 352 */\r
945 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
946 /* 415 384 447 416 479 448 511 480 */\r
947 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
948 \r
949 /* ownDmaChannels */\r
950 /* 31 0 63 32 */\r
951 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
952 \r
953 /* ownQdmaChannels */\r
954 /* 31 0 */\r
955 {0x000000FFu},\r
956 \r
957 /* ownTccs */\r
958 /* 31 0 63 32 */\r
959 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
960 \r
961 /* resvdPaRAMSets */\r
962 /* 31 0 63 32 95 64 127 96 */\r
963 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
964 /* 159 128 191 160 223 192 255 224 */\r
965 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
966 /* 287 256 319 288 351 320 383 352 */\r
967 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
968 /* 415 384 447 416 479 448 511 480 */\r
969 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
970 \r
971 /* resvdDmaChannels */\r
972 /* 31 0 63 32 */\r
973 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
974 \r
975 /* resvdQdmaChannels */\r
976 /* 31 0 */\r
977 {0x00u},\r
978 \r
979 /* resvdTccs */\r
980 /* 31 0 63 32 */\r
981 {0x00u, 0x00u},\r
982 },\r
983 \r
984 /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
985 {\r
986 /* ownPaRAMSets */\r
987 /* 31 0 63 32 95 64 127 96 */\r
988 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
989 /* 159 128 191 160 223 192 255 224 */\r
990 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
991 /* 287 256 319 288 351 320 383 352 */\r
992 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
993 /* 415 384 447 416 479 448 511 480 */\r
994 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
995 \r
996 /* ownDmaChannels */\r
997 /* 31 0 63 32 */\r
998 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
999 \r
1000 /* ownQdmaChannels */\r
1001 /* 31 0 */\r
1002 {0x000000FFu},\r
1003 \r
1004 /* ownTccs */\r
1005 /* 31 0 63 32 */\r
1006 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1007 \r
1008 /* resvdPaRAMSets */\r
1009 /* 31 0 63 32 95 64 127 96 */\r
1010 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1011 /* 159 128 191 160 223 192 255 224 */\r
1012 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1013 /* 287 256 319 288 351 320 383 352 */\r
1014 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1015 /* 415 384 447 416 479 448 511 480 */\r
1016 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1017 \r
1018 /* resvdDmaChannels */\r
1019 /* 31 0 63 32 */\r
1020 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1021 \r
1022 /* resvdQdmaChannels */\r
1023 /* 31 0 */\r
1024 {0x00u},\r
1025 \r
1026 /* resvdTccs */\r
1027 /* 31 0 63 32 */\r
1028 {0x00u, 0x00u},\r
1029 },\r
1030 \r
1031 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
1032 {\r
1033 /* ownPaRAMSets */\r
1034 /* 31 0 63 32 95 64 127 96 */\r
1035 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1036 /* 159 128 191 160 223 192 255 224 */\r
1037 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1038 /* 287 256 319 288 351 320 383 352 */\r
1039 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1040 /* 415 384 447 416 479 448 511 480 */\r
1041 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1042 \r
1043 /* ownDmaChannels */\r
1044 /* 31 0 63 32 */\r
1045 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1046 \r
1047 /* ownQdmaChannels */\r
1048 /* 31 0 */\r
1049 {0x000000FFu},\r
1050 \r
1051 /* ownTccs */\r
1052 /* 31 0 63 32 */\r
1053 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1054 \r
1055 /* resvdPaRAMSets */\r
1056 /* 31 0 63 32 95 64 127 96 */\r
1057 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1058 /* 159 128 191 160 223 192 255 224 */\r
1059 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1060 /* 287 256 319 288 351 320 383 352 */\r
1061 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1062 /* 415 384 447 416 479 448 511 480 */\r
1063 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1064 \r
1065 /* resvdDmaChannels */\r
1066 /* 31 0 63 32 */\r
1067 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1068 \r
1069 /* resvdQdmaChannels */\r
1070 /* 31 0 */\r
1071 {0x00u},\r
1072 \r
1073 /* resvdTccs */\r
1074 /* 31 0 63 32 */\r
1075 {0x00u, 0x00u},\r
1076 },\r
1077 \r
1078 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
1079 {\r
1080 /* ownPaRAMSets */\r
1081 /* 31 0 63 32 95 64 127 96 */\r
1082 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1083 /* 159 128 191 160 223 192 255 224 */\r
1084 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1085 /* 287 256 319 288 351 320 383 352 */\r
1086 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1087 /* 415 384 447 416 479 448 511 480 */\r
1088 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1089 \r
1090 /* ownDmaChannels */\r
1091 /* 31 0 63 32 */\r
1092 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1093 \r
1094 /* ownQdmaChannels */\r
1095 /* 31 0 */\r
1096 {0x000000FFu},\r
1097 \r
1098 /* ownTccs */\r
1099 /* 31 0 63 32 */\r
1100 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1101 \r
1102 /* resvdPaRAMSets */\r
1103 /* 31 0 63 32 95 64 127 96 */\r
1104 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1105 /* 159 128 191 160 223 192 255 224 */\r
1106 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1107 /* 287 256 319 288 351 320 383 352 */\r
1108 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1109 /* 415 384 447 416 479 448 511 480 */\r
1110 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1111 \r
1112 /* resvdDmaChannels */\r
1113 /* 31 0 63 32 */\r
1114 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1115 \r
1116 /* resvdQdmaChannels */\r
1117 /* 31 0 */\r
1118 {0x00u},\r
1119 \r
1120 /* resvdTccs */\r
1121 /* 31 0 63 32 */\r
1122 {0x00u, 0x00u},\r
1123 },\r
1124 \r
1125 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
1126 {\r
1127 /* ownPaRAMSets */\r
1128 /* 31 0 63 32 95 64 127 96 */\r
1129 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1130 /* 159 128 191 160 223 192 255 224 */\r
1131 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1132 /* 287 256 319 288 351 320 383 352 */\r
1133 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1134 /* 415 384 447 416 479 448 511 480 */\r
1135 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1136 \r
1137 /* ownDmaChannels */\r
1138 /* 31 0 63 32 */\r
1139 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1140 \r
1141 /* ownQdmaChannels */\r
1142 /* 31 0 */\r
1143 {0x000000FFu},\r
1144 \r
1145 /* ownTccs */\r
1146 /* 31 0 63 32 */\r
1147 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1148 \r
1149 /* resvdPaRAMSets */\r
1150 /* 31 0 63 32 95 64 127 96 */\r
1151 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1152 /* 159 128 191 160 223 192 255 224 */\r
1153 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1154 /* 287 256 319 288 351 320 383 352 */\r
1155 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1156 /* 415 384 447 416 479 448 511 480 */\r
1157 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1158 \r
1159 /* resvdDmaChannels */\r
1160 /* 31 0 63 32 */\r
1161 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1162 \r
1163 /* resvdQdmaChannels */\r
1164 /* 31 0 */\r
1165 {0x00u},\r
1166 \r
1167 /* resvdTccs */\r
1168 /* 31 0 63 32 */\r
1169 {0x00u, 0x00u},\r
1170 },\r
1171 \r
1172 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
1173 {\r
1174 /* ownPaRAMSets */\r
1175 /* 31 0 63 32 95 64 127 96 */\r
1176 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1177 /* 159 128 191 160 223 192 255 224 */\r
1178 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1179 /* 287 256 319 288 351 320 383 352 */\r
1180 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1181 /* 415 384 447 416 479 448 511 480 */\r
1182 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1183 \r
1184 /* ownDmaChannels */\r
1185 /* 31 0 63 32 */\r
1186 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1187 \r
1188 /* ownQdmaChannels */\r
1189 /* 31 0 */\r
1190 {0x000000FFu},\r
1191 \r
1192 /* ownTccs */\r
1193 /* 31 0 63 32 */\r
1194 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1195 \r
1196 /* resvdPaRAMSets */\r
1197 /* 31 0 63 32 95 64 127 96 */\r
1198 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1199 /* 159 128 191 160 223 192 255 224 */\r
1200 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1201 /* 287 256 319 288 351 320 383 352 */\r
1202 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1203 /* 415 384 447 416 479 448 511 480 */\r
1204 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1205 \r
1206 /* resvdDmaChannels */\r
1207 /* 31 0 63 32 */\r
1208 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1209 \r
1210 /* resvdQdmaChannels */\r
1211 /* 31 0 */\r
1212 {0x00u},\r
1213 \r
1214 /* resvdTccs */\r
1215 /* 31 0 63 32 */\r
1216 {0x00u, 0x00u},\r
1217 },\r
1218 },\r
1219 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
1220 {\r
1221 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1222 {\r
1223 /* ownPaRAMSets */\r
1224 /* 31 0 63 32 95 64 127 96 */\r
1225 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1226 /* 159 128 191 160 223 192 255 224 */\r
1227 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1228 /* 287 256 319 288 351 320 383 352 */\r
1229 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1230 /* 415 384 447 416 479 448 511 480 */\r
1231 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1232 \r
1233 /* ownDmaChannels */\r
1234 /* 31 0 63 32 */\r
1235 {0x00000000u, 0x00000000u},\r
1236 \r
1237 /* ownQdmaChannels */\r
1238 /* 31 0 */\r
1239 {0x00000000u},\r
1240 \r
1241 /* ownTccs */\r
1242 /* 31 0 63 32 */\r
1243 {0x00000000u, 0x00000000u},\r
1244 \r
1245 /* resvdPaRAMSets */\r
1246 /* 31 0 63 32 95 64 127 96 */\r
1247 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1248 /* 159 128 191 160 223 192 255 224 */\r
1249 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1250 /* 287 256 319 288 351 320 383 352 */\r
1251 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1252 /* 415 384 447 416 479 448 511 480 */\r
1253 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1254 \r
1255 /* resvdDmaChannels */\r
1256 /* 31 0 63 32 */\r
1257 {0x00000000u, 0x00000000u},\r
1258 \r
1259 /* resvdQdmaChannels */\r
1260 /* 31 0 */\r
1261 {0x00000000u},\r
1262 \r
1263 /* resvdTccs */\r
1264 /* 31 0 63 32 */\r
1265 {0x00000000u, 0x00000000u},\r
1266 },\r
1267 \r
1268 /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
1269 {\r
1270 /* ownPaRAMSets */\r
1271 /* 31 0 63 32 95 64 127 96 */\r
1272 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1273 /* 159 128 191 160 223 192 255 224 */\r
1274 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1275 /* 287 256 319 288 351 320 383 352 */\r
1276 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1277 /* 415 384 447 416 479 448 511 480 */\r
1278 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1279 \r
1280 /* ownDmaChannels */\r
1281 /* 31 0 63 32 */\r
1282 {0x00000000u, 0x00000000u},\r
1283 \r
1284 /* ownQdmaChannels */\r
1285 /* 31 0 */\r
1286 {0x00000000u},\r
1287 \r
1288 /* ownTccs */\r
1289 /* 31 0 63 32 */\r
1290 {0x00000000u, 0x00000000u},\r
1291 \r
1292 /* resvdPaRAMSets */\r
1293 /* 31 0 63 32 95 64 127 96 */\r
1294 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1295 /* 159 128 191 160 223 192 255 224 */\r
1296 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1297 /* 287 256 319 288 351 320 383 352 */\r
1298 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1299 /* 415 384 447 416 479 448 511 480 */\r
1300 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1301 \r
1302 /* resvdDmaChannels */\r
1303 /* 31 0 63 32 */\r
1304 {0x00000000u, 0x00000000u},\r
1305 \r
1306 /* resvdQdmaChannels */\r
1307 /* 31 0 */\r
1308 {0x00000000u},\r
1309 \r
1310 /* resvdTccs */\r
1311 /* 31 0 63 32 */\r
1312 {0x00000000u, 0x00000000u},\r
1313 },\r
1314 \r
1315 /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
1316 {\r
1317 /* ownPaRAMSets */\r
1318 /* 31 0 63 32 95 64 127 96 */\r
1319 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1320 /* 159 128 191 160 223 192 255 224 */\r
1321 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1322 /* 287 256 319 288 351 320 383 352 */\r
1323 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1324 /* 415 384 447 416 479 448 511 480 */\r
1325 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1326 \r
1327 /* ownDmaChannels */\r
1328 /* 31 0 63 32 */\r
1329 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1330 \r
1331 /* ownQdmaChannels */\r
1332 /* 31 0 */\r
1333 {0x000000FFu},\r
1334 \r
1335 /* ownTccs */\r
1336 /* 31 0 63 32 */\r
1337 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1338 \r
1339 /* resvdPaRAMSets */\r
1340 /* 31 0 63 32 95 64 127 96 */\r
1341 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1342 /* 159 128 191 160 223 192 255 224 */\r
1343 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1344 /* 287 256 319 288 351 320 383 352 */\r
1345 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1346 /* 415 384 447 416 479 448 511 480 */\r
1347 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1348 \r
1349 /* resvdDmaChannels */\r
1350 /* 31 0 63 32 */\r
1351 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1352 \r
1353 /* resvdQdmaChannels */\r
1354 /* 31 0 */\r
1355 {0x00u},\r
1356 \r
1357 /* resvdTccs */\r
1358 /* 31 0 63 32 */\r
1359 {0x00u, 0x00u},\r
1360 },\r
1361 \r
1362 /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
1363 {\r
1364 /* ownPaRAMSets */\r
1365 /* 31 0 63 32 95 64 127 96 */\r
1366 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1367 /* 159 128 191 160 223 192 255 224 */\r
1368 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1369 /* 287 256 319 288 351 320 383 352 */\r
1370 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1371 /* 415 384 447 416 479 448 511 480 */\r
1372 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1373 \r
1374 /* ownDmaChannels */\r
1375 /* 31 0 63 32 */\r
1376 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1377 \r
1378 /* ownQdmaChannels */\r
1379 /* 31 0 */\r
1380 {0x000000FFu},\r
1381 \r
1382 /* ownTccs */\r
1383 /* 31 0 63 32 */\r
1384 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1385 \r
1386 /* resvdPaRAMSets */\r
1387 /* 31 0 63 32 95 64 127 96 */\r
1388 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1389 /* 159 128 191 160 223 192 255 224 */\r
1390 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1391 /* 287 256 319 288 351 320 383 352 */\r
1392 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1393 /* 415 384 447 416 479 448 511 480 */\r
1394 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1395 \r
1396 /* resvdDmaChannels */\r
1397 /* 31 0 63 32 */\r
1398 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1399 \r
1400 /* resvdQdmaChannels */\r
1401 /* 31 0 */\r
1402 {0x00u},\r
1403 \r
1404 /* resvdTccs */\r
1405 /* 31 0 63 32 */\r
1406 {0x00u, 0x00u},\r
1407 },\r
1408 \r
1409 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1410 {\r
1411 /* ownPaRAMSets */\r
1412 /* 31 0 63 32 95 64 127 96 */\r
1413 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1414 /* 159 128 191 160 223 192 255 224 */\r
1415 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1416 /* 287 256 319 288 351 320 383 352 */\r
1417 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1418 /* 415 384 447 416 479 448 511 480 */\r
1419 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1420 \r
1421 /* ownDmaChannels */\r
1422 /* 31 0 63 32 */\r
1423 {0x00000000u, 0x00000000u},\r
1424 \r
1425 /* ownQdmaChannels */\r
1426 /* 31 0 */\r
1427 {0x00000000u},\r
1428 \r
1429 /* ownTccs */\r
1430 /* 31 0 63 32 */\r
1431 {0x00000000u, 0x00000000u},\r
1432 \r
1433 /* resvdPaRAMSets */\r
1434 /* 31 0 63 32 95 64 127 96 */\r
1435 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1436 /* 159 128 191 160 223 192 255 224 */\r
1437 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1438 /* 287 256 319 288 351 320 383 352 */\r
1439 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1440 /* 415 384 447 416 479 448 511 480 */\r
1441 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1442 \r
1443 /* resvdDmaChannels */\r
1444 /* 31 0 63 32 */\r
1445 {0x00000000u, 0x00000000u},\r
1446 \r
1447 /* resvdQdmaChannels */\r
1448 /* 31 0 */\r
1449 {0x00000000u},\r
1450 \r
1451 /* resvdTccs */\r
1452 /* 31 0 63 32 */\r
1453 {0x00000000u, 0x00000000u},\r
1454 },\r
1455 \r
1456 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1457 {\r
1458 /* ownPaRAMSets */\r
1459 /* 31 0 63 32 95 64 127 96 */\r
1460 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1461 /* 159 128 191 160 223 192 255 224 */\r
1462 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1463 /* 287 256 319 288 351 320 383 352 */\r
1464 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1465 /* 415 384 447 416 479 448 511 480 */\r
1466 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1467 \r
1468 /* ownDmaChannels */\r
1469 /* 31 0 63 32 */\r
1470 {0x00000000u, 0x00000000u},\r
1471 \r
1472 /* ownQdmaChannels */\r
1473 /* 31 0 */\r
1474 {0x00000000u},\r
1475 \r
1476 /* ownTccs */\r
1477 /* 31 0 63 32 */\r
1478 {0x00000000u, 0x00000000u},\r
1479 \r
1480 /* resvdPaRAMSets */\r
1481 /* 31 0 63 32 95 64 127 96 */\r
1482 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1483 /* 159 128 191 160 223 192 255 224 */\r
1484 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1485 /* 287 256 319 288 351 320 383 352 */\r
1486 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1487 /* 415 384 447 416 479 448 511 480 */\r
1488 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1489 \r
1490 /* resvdDmaChannels */\r
1491 /* 31 0 63 32 */\r
1492 {0x00000000u, 0x00000000u},\r
1493 \r
1494 /* resvdQdmaChannels */\r
1495 /* 31 0 */\r
1496 {0x00000000u},\r
1497 \r
1498 /* resvdTccs */\r
1499 /* 31 0 63 32 */\r
1500 {0x00000000u, 0x00000000u},\r
1501 },\r
1502 \r
1503 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1504 {\r
1505 /* ownPaRAMSets */\r
1506 /* 31 0 63 32 95 64 127 96 */\r
1507 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1508 /* 159 128 191 160 223 192 255 224 */\r
1509 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1510 /* 287 256 319 288 351 320 383 352 */\r
1511 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1512 /* 415 384 447 416 479 448 511 480 */\r
1513 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1514 \r
1515 /* ownDmaChannels */\r
1516 /* 31 0 63 32 */\r
1517 {0x00000000u, 0x00000000u},\r
1518 \r
1519 /* ownQdmaChannels */\r
1520 /* 31 0 */\r
1521 {0x00000000u},\r
1522 \r
1523 /* ownTccs */\r
1524 /* 31 0 63 32 */\r
1525 {0x00000000u, 0x00000000u},\r
1526 \r
1527 /* resvdPaRAMSets */\r
1528 /* 31 0 63 32 95 64 127 96 */\r
1529 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1530 /* 159 128 191 160 223 192 255 224 */\r
1531 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1532 /* 287 256 319 288 351 320 383 352 */\r
1533 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1534 /* 415 384 447 416 479 448 511 480 */\r
1535 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1536 \r
1537 /* resvdDmaChannels */\r
1538 /* 31 0 63 32 */\r
1539 {0x00000000u, 0x00000000u},\r
1540 \r
1541 /* resvdQdmaChannels */\r
1542 /* 31 0 */\r
1543 {0x00000000u},\r
1544 \r
1545 /* resvdTccs */\r
1546 /* 31 0 63 32 */\r
1547 {0x00000000u, 0x00000000u},\r
1548 },\r
1549 \r
1550 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1551 {\r
1552 /* ownPaRAMSets */\r
1553 /* 31 0 63 32 95 64 127 96 */\r
1554 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1555 /* 159 128 191 160 223 192 255 224 */\r
1556 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1557 /* 287 256 319 288 351 320 383 352 */\r
1558 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1559 /* 415 384 447 416 479 448 511 480 */\r
1560 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1561 \r
1562 /* ownDmaChannels */\r
1563 /* 31 0 63 32 */\r
1564 {0x00000000u, 0x00000000u},\r
1565 \r
1566 /* ownQdmaChannels */\r
1567 /* 31 0 */\r
1568 {0x00000000u},\r
1569 \r
1570 /* ownTccs */\r
1571 /* 31 0 63 32 */\r
1572 {0x00000000u, 0x00000000u},\r
1573 \r
1574 /* resvdPaRAMSets */\r
1575 /* 31 0 63 32 95 64 127 96 */\r
1576 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1577 /* 159 128 191 160 223 192 255 224 */\r
1578 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1579 /* 287 256 319 288 351 320 383 352 */\r
1580 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1581 /* 415 384 447 416 479 448 511 480 */\r
1582 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1583 \r
1584 /* resvdDmaChannels */\r
1585 /* 31 0 63 32 */\r
1586 {0x00000000u, 0x00000000u},\r
1587 \r
1588 /* resvdQdmaChannels */\r
1589 /* 31 0 */\r
1590 {0x00000000u},\r
1591 \r
1592 /* resvdTccs */\r
1593 /* 31 0 63 32 */\r
1594 {0x00000000u, 0x00000000u},\r
1595 },\r
1596 },\r
1597 };\r
1598 \r
1599 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
1600 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
1601 {\r
1602 /* EDMA3 INSTANCE# 0 */\r
1603 {\r
1604 /* Event to channel map for region 0 */\r
1605 {\r
1606 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1607 -1, -1, -1, -1, -1, -1, -1, -1,\r
1608 -1, -1, -1, -1, -1, -1, -1, -1,\r
1609 -1, -1, -1, -1, -1, -1, -1, -1,\r
1610 -1, -1, -1, -1, -1, -1, -1, -1,\r
1611 -1, -1, -1, -1, -1, -1, -1, -1,\r
1612 -1, -1, -1, -1, -1, -1, -1, -1,\r
1613 -1, -1, -1, -1, -1, -1, -1}\r
1614 },\r
1615 /* Event to channel map for region 1 */\r
1616 {\r
1617 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1618 -1, -1, -1, -1, -1, -1, -1, -1,\r
1619 -1, -1, -1, -1, -1, -1, -1, -1,\r
1620 -1, -1, -1, -1, -1, -1, -1, -1,\r
1621 -1, -1, -1, -1, -1, -1, -1, -1,\r
1622 -1, -1, -1, -1, -1, -1, -1, -1,\r
1623 -1, -1, -1, -1, -1, -1, -1, -1,\r
1624 -1, -1, -1, -1, -1, -1, -1}\r
1625 },\r
1626 /* Event to channel map for region 2 */\r
1627 {\r
1628 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1629 -1, -1, -1, -1, -1, -1, -1, -1,\r
1630 -1, -1, -1, -1, -1, -1, -1, -1,\r
1631 -1, -1, -1, -1, -1, -1, -1, -1,\r
1632 -1, -1, -1, -1, -1, -1, -1, -1,\r
1633 -1, -1, -1, -1, -1, -1, -1, -1,\r
1634 -1, -1, -1, -1, -1, -1, -1, -1,\r
1635 -1, -1, -1, -1, -1, -1, -1}\r
1636 },\r
1637 /* Event to channel map for region 3 */\r
1638 {\r
1639 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1640 -1, -1, -1, -1, -1, -1, -1, -1,\r
1641 -1, -1, -1, -1, -1, -1, -1, -1,\r
1642 -1, -1, -1, -1, -1, -1, -1, -1,\r
1643 -1, -1, -1, -1, -1, -1, -1, -1,\r
1644 -1, -1, -1, -1, -1, -1, -1, -1,\r
1645 -1, -1, -1, -1, -1, -1, -1, -1,\r
1646 -1, -1, -1, -1, -1, -1, -1}\r
1647 },\r
1648 /* Event to channel map for region 4 */\r
1649 {\r
1650 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1651 -1, -1, -1, -1, -1, -1, -1, -1,\r
1652 -1, -1, -1, -1, -1, -1, -1, -1,\r
1653 -1, -1, -1, -1, -1, -1, -1, -1,\r
1654 -1, -1, -1, -1, -1, -1, -1, -1,\r
1655 -1, -1, -1, -1, -1, -1, -1, -1,\r
1656 -1, -1, -1, -1, -1, -1, -1, -1,\r
1657 -1, -1, -1, -1, -1, -1, -1}\r
1658 },\r
1659 /* Event to channel map for region 5 */\r
1660 {\r
1661 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1662 -1, -1, -1, -1, -1, -1, -1, -1,\r
1663 -1, -1, -1, -1, -1, -1, -1, -1,\r
1664 -1, -1, -1, -1, -1, -1, -1, -1,\r
1665 -1, -1, -1, -1, -1, -1, -1, -1,\r
1666 -1, -1, -1, -1, -1, -1, -1, -1,\r
1667 -1, -1, -1, -1, -1, -1, -1, -1,\r
1668 -1, -1, -1, -1, -1, -1, -1}\r
1669 },\r
1670 /* Event to channel map for region 6 */\r
1671 {\r
1672 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1673 -1, -1, -1, -1, -1, -1, -1, -1,\r
1674 -1, -1, -1, -1, -1, -1, -1, -1,\r
1675 -1, -1, -1, -1, -1, -1, -1, -1,\r
1676 -1, -1, -1, -1, -1, -1, -1, -1,\r
1677 -1, -1, -1, -1, -1, -1, -1, -1,\r
1678 -1, -1, -1, -1, -1, -1, -1, -1,\r
1679 -1, -1, -1, -1, -1, -1, -1}\r
1680 },\r
1681 /* Event to channel map for region 7 */\r
1682 {\r
1683 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1684 -1, -1, -1, -1, -1, -1, -1, -1,\r
1685 -1, -1, -1, -1, -1, -1, -1, -1,\r
1686 -1, -1, -1, -1, -1, -1, -1, -1,\r
1687 -1, -1, -1, -1, -1, -1, -1, -1,\r
1688 -1, -1, -1, -1, -1, -1, -1, -1,\r
1689 -1, -1, -1, -1, -1, -1, -1, -1,\r
1690 -1, -1, -1, -1, -1, -1, -1}\r
1691 },\r
1692 }\r
1693 };\r
1694 \r
1695 /* End of File */\r
1696 \r