[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2 * sample_tda2xx_cfg.c\r
3 *\r
4 * SoC specific EDMA3 hardware related information like number of transfer\r
5 * controllers, various interrupt ids etc. It is used while interrupts\r
6 * enabling / disabling. It needs to be ported for different SoCs.\r
7 *\r
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9 *\r
10 *\r
11 * Redistribution and use in source and binary forms, with or without\r
12 * modification, are permitted provided that the following conditions\r
13 * are met:\r
14 *\r
15 * Redistributions of source code must retain the above copyright\r
16 * notice, this list of conditions and the following disclaimer.\r
17 *\r
18 * Redistributions in binary form must reproduce the above copyright\r
19 * notice, this list of conditions and the following disclaimer in the\r
20 * documentation and/or other materials provided with the\r
21 * distribution.\r
22 *\r
23 * Neither the name of Texas Instruments Incorporated nor the names of\r
24 * its contributors may be used to endorse or promote products derived\r
25 * from this software without specific prior written permission.\r
26 *\r
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38 *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
42 #ifdef BUILD_TDA2XX_IPU\r
43 #include <ti/sysbios/family/arm/ducati/Core.h> \r
44 \r
45 #endif\r
46 \r
47 /* Number of EDMA3 controllers present in the system */\r
48 #define NUM_EDMA3_INSTANCES 3u\r
49 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
50 \r
51 /* Number of DSPs present in the system */\r
52 #define NUM_DSPS 1u\r
53 const unsigned int numDsps = NUM_DSPS;\r
54 \r
55 /* Determine the processor id by reading DNUM register. */\r
56 /* Statically allocate the region numbers with cores. */\r
57 int myCoreNum;\r
58 #define PID0_ADDRESS 0xE00FFFE0\r
59 #define CORE_ID_C0 0x0\r
60 #define CORE_ID_C1 0x1\r
61 \r
62 unsigned short determineProcId()\r
63 {\r
64 unsigned short regionNo = numEdma3Instances;\r
65 #ifdef BUILD_TDA2XX_DSP\r
66 extern __cregister volatile unsigned int DNUM;\r
67 #endif\r
68 \r
69 myCoreNum = numDsps;\r
70 \r
71 #ifdef BUILD_TDA2XX_MPU\r
72 asm (" push {r0-r2} \n\t"\r
73 " MRC p15, 0, r0, c0, c0, 5\n\t"\r
74 " LDR r1, =myCoreNum\n\t"\r
75 " STR r0, [r1]\n\t"\r
76 " pop {r0-r2}\n\t");\r
77 if((myCoreNum & 0x03) == 1)\r
78 regionNo = 1;\r
79 else\r
80 regionNo = 0;\r
81 #elif defined(BUILD_TDA2XX_IPU)\r
82 myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
83 if(Core_getIpuId() == 1){\r
84 if(myCoreNum == CORE_ID_C0)\r
85 regionNo = 4;\r
86 else if (myCoreNum == CORE_ID_C1)\r
87 regionNo = 5;\r
88 }\r
89 if(Core_getIpuId() == 2){\r
90 if(myCoreNum == CORE_ID_C0)\r
91 regionNo = 6;\r
92 else if (myCoreNum == CORE_ID_C1)\r
93 regionNo = 7;\r
94 }\r
95 #elif defined(BUILD_TDA2XX_DSP)\r
96 \r
97 myCoreNum = DNUM;\r
98 if(myCoreNum == 0)\r
99 regionNo = 2;\r
100 else\r
101 regionNo = 3;\r
102 #elif defined(BUILD_TDA2XX_EVE)\r
103 regionNo = 1;\r
104 #endif\r
105 return regionNo;\r
106 }\r
107 \r
108 signed char* getGlobalAddr(signed char* addr)\r
109 {\r
110 return (addr); /* The address is already a global address */\r
111 }\r
112 unsigned short isGblConfigRequired(unsigned int dspNum)\r
113 {\r
114 (void) dspNum;\r
115 return 1;\r
116 }\r
117 \r
118 /* Semaphore handles */\r
119 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
120 \r
121 /** Number of PaRAM Sets available */\r
122 #define EDMA3_NUM_PARAMSET (512u)\r
123 \r
124 /** Number of TCCS available */\r
125 #define EDMA3_NUM_TCC (64u)\r
126 \r
127 /** Number of DMA Channels available */\r
128 #define EDMA3_NUM_DMA_CHANNELS (64u)\r
129 \r
130 /** Number of QDMA Channels available */\r
131 #define EDMA3_NUM_QDMA_CHANNELS (8u)\r
132 \r
133 /** Number of Event Queues available */\r
134 #define EDMA3_NUM_EVTQUE (4u)\r
135 \r
136 /** Number of Transfer Controllers available */\r
137 #define EDMA3_NUM_TC (2u)\r
138 \r
139 /** Number of Regions */\r
140 #define EDMA3_NUM_REGIONS (8u)\r
141 \r
142 /** Interrupt no. for Transfer Completion */\r
143 #define EDMA3_CC_XFER_COMPLETION_INT_A15 (66u)\r
144 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u)\r
145 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u)\r
146 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u)\r
147 #define EDMA3_CC_XFER_COMPLETION_INT_EVE (8u)\r
148 \r
149 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
150 #define COMPLETION_INT_A15_XBAR_INST_NO (29u)\r
151 #define COMPLETION_INT_DSP_XBAR_INST_NO (7u)\r
152 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u)\r
153 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u)\r
154 \r
155 /** Interrupt no. for CC Error */\r
156 #define EDMA3_CC_ERROR_INT_A15 (67u)\r
157 #define EDMA3_CC_ERROR_INT_DSP (39u)\r
158 #define EDMA3_CC_ERROR_INT_IPU (35u)\r
159 #define EDMA3_CC_ERROR_INT_EVE (23u)\r
160 \r
161 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
162 #define CC_ERROR_INT_A15_XBAR_INST_NO (30u)\r
163 #define CC_ERROR_INT_DSP_XBAR_INST_NO (8u)\r
164 #define CC_ERROR_INT_IPU_XBAR_INST_NO (13u)\r
165 \r
166 /** Interrupt no. for TCs Error */\r
167 #define EDMA3_TC0_ERROR_INT_A15 (68u)\r
168 #define EDMA3_TC0_ERROR_INT_DSP (40u)\r
169 #define EDMA3_TC0_ERROR_INT_IPU (36u)\r
170 #define EDMA3_TC0_ERROR_INT_EVE (24u)\r
171 #define EDMA3_TC1_ERROR_INT_A15 (69u)\r
172 #define EDMA3_TC1_ERROR_INT_DSP (41u)\r
173 #define EDMA3_TC1_ERROR_INT_IPU (37u)\r
174 #define EDMA3_TC1_ERROR_INT_EVE (25u)\r
175 \r
176 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
177 #define TC0_ERROR_INT_A15_XBAR_INST_NO (31u)\r
178 #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u) \r
179 #define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u)\r
180 #define TC1_ERROR_INT_A15_XBAR_INST_NO (32u)\r
181 #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u)\r
182 #define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)\r
183 \r
184 #ifdef BUILD_TDA2XX_MPU\r
185 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15\r
186 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A15\r
187 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_A15_XBAR_INST_NO\r
188 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A15\r
189 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A15\r
190 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
191 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
192 \r
193 #elif defined BUILD_TDA2XX_DSP\r
194 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP\r
195 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP\r
196 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_DSP_XBAR_INST_NO\r
197 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP\r
198 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP\r
199 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_DSP_XBAR_INST_NO\r
200 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_DSP_XBAR_INST_NO\r
201 \r
202 #elif defined BUILD_TDA2XX_IPU\r
203 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU_C0\r
204 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU\r
205 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU_XBAR_INST_NO\r
206 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU\r
207 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU\r
208 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU_XBAR_INST_NO\r
209 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU_XBAR_INST_NO\r
210 \r
211 #elif defined BUILD_TDA2XX_EVE\r
212 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_EVE\r
213 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_EVE\r
214 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_EVE\r
215 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_EVE\r
216 /* For accessing EVE internal edma, there is no need to configure Xbar */\r
217 #define CC_ERROR_INT_XBAR_INST_NO 0u\r
218 #define TC0_ERROR_INT_XBAR_INST_NO 0u\r
219 #define TC1_ERROR_INT_XBAR_INST_NO 0u\r
220 \r
221 #else\r
222 #define EDMA3_CC_XFER_COMPLETION_INT (0u)\r
223 #define EDMA3_CC_ERROR_INT (0u)\r
224 #define CC_ERROR_INT_XBAR_INST_NO (0u)\r
225 #define EDMA3_TC0_ERROR_INT (0u)\r
226 #define EDMA3_TC1_ERROR_INT (0u)\r
227 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
228 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
229 #endif\r
230 \r
231 #define EDMA3_TC2_ERROR_INT (0u)\r
232 #define EDMA3_TC3_ERROR_INT (0u)\r
233 #define EDMA3_TC4_ERROR_INT (0u)\r
234 #define EDMA3_TC5_ERROR_INT (0u)\r
235 #define EDMA3_TC6_ERROR_INT (0u)\r
236 #define EDMA3_TC7_ERROR_INT (0u)\r
237 \r
238 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19u)\r
239 #define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20u)\r
240 #define DSP1_EDMA3_CC_ERROR_INT (27u)\r
241 #define DSP1_EDMA3_TC0_ERROR_INT (28u)\r
242 #define DSP1_EDMA3_TC1_ERROR_INT (29u)\r
243 \r
244 /** XBAR interrupt source index numbers for EDMA interrupts */\r
245 #define XBAR_EDMA_TPCC_IRQ_REGION0 (361u)\r
246 #define XBAR_EDMA_TPCC_IRQ_REGION1 (362u)\r
247 #define XBAR_EDMA_TPCC_IRQ_REGION2 (363u)\r
248 #define XBAR_EDMA_TPCC_IRQ_REGION3 (364u)\r
249 #define XBAR_EDMA_TPCC_IRQ_REGION4 (365u)\r
250 #define XBAR_EDMA_TPCC_IRQ_REGION5 (366u)\r
251 #define XBAR_EDMA_TPCC_IRQ_REGION6 (367u)\r
252 #define XBAR_EDMA_TPCC_IRQ_REGION7 (368u)\r
253 \r
254 #define XBAR_EDMA_TPCC_IRQ_ERR (359u)\r
255 #define XBAR_EDMA_TC0_IRQ_ERR (370u)\r
256 #define XBAR_EDMA_TC1_IRQ_ERR (371u)\r
257 \r
258 /**\r
259 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
260 * ECM events (SoC specific). These ECM events come\r
261 * under ECM block XXX (handling those specific ECM events). Normally, block\r
262 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
263 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
264 * is mapped to a specific HWI_INT YYY in the tcf file.\r
265 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
266 * to transfer completion interrupt.\r
267 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
268 * to CC error interrupts.\r
269 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
270 * to TC error interrupts.\r
271 */\r
272 /* EDMA 0 */\r
273 \r
274 #define EDMA3_HWI_INT_XFER_COMP (7u)\r
275 #define EDMA3_HWI_INT_CC_ERR (7u)\r
276 #define EDMA3_HWI_INT_TC0_ERR (10u)\r
277 #define EDMA3_HWI_INT_TC1_ERR (10u)\r
278 #define EDMA3_HWI_INT_TC2_ERR (10u)\r
279 #define EDMA3_HWI_INT_TC3_ERR (10u)\r
280 \r
281 /**\r
282 * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
283 * various peripherals, which use EDMA for data transfer.\r
284 * All channels need not be mapped, some can be free also.\r
285 * 1: Mapped\r
286 * 0: Not mapped (channel available)\r
287 *\r
288 * This mapping will be used to allocate DMA channels when user passes\r
289 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
290 * copy). The same mapping is used to allocate the TCC when user passes\r
291 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
292 * \r
293 * For Vayu Since the xbar can be used to map event to any EDMA channel,\r
294 * If the application is assigning events to other channel this variable \r
295 * should be modified\r
296 *\r
297 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
298 */\r
299 /* 31 0 */\r
300 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA (0x3FC0C06Eu) /* TBD */\r
301 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFu) /* TBD */\r
302 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA (0x00000000u) /* TBD */\r
303 \r
304 /**\r
305 * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
306 * various peripherals, which use EDMA for data transfer.\r
307 * All channels need not be mapped, some can be free also.\r
308 * 1: Mapped\r
309 * 0: Not mapped (channel available)\r
310 *\r
311 * This mapping will be used to allocate DMA channels when user passes\r
312 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
313 * copy). The same mapping is used to allocate the TCC when user passes\r
314 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
315 *\r
316 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
317 */\r
318 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA (0xF3FFFFFCu) /* TBD */\r
319 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000u) /* TBD */\r
320 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA (0x00000000u) /* TBD */\r
321 \r
322 \r
323 /* Variable which will be used internally for referring number of Event Queues*/\r
324 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {\r
325 EDMA3_NUM_EVTQUE,\r
326 };\r
327 \r
328 /* Variable which will be used internally for referring number of TCs. */\r
329 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
330 EDMA3_NUM_TC,\r
331 EDMA3_NUM_TC,\r
332 EDMA3_NUM_TC\r
333 };\r
334 \r
335 /**\r
336 * Variable which will be used internally for referring transfer completion\r
337 * interrupt.\r
338 */\r
339 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
340 {\r
341 /* EDMA3 INSTANCE# 0 */\r
342 {\r
343 EDMA3_CC_XFER_COMPLETION_INT_A15,\r
344 EDMA3_CC_XFER_COMPLETION_INT_A15,\r
345 EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
346 EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
347 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
348 EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
349 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
350 EDMA3_CC_XFER_COMPLETION_INT_IPU_C1\r
351 },\r
352 /* EDMA3 INSTANCE# 1 */\r
353 {\r
354 0u,\r
355 0u,\r
356 DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
357 DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
358 0u,\r
359 0u,\r
360 0u,\r
361 0u\r
362 },\r
363 /* EDMA3 INSTANCE# 2 */\r
364 {\r
365 0u,\r
366 /* Region 1 (Associated to EVE core)*/\r
367 EDMA3_CC_XFER_COMPLETION_INT_EVE,\r
368 0u,\r
369 0u,\r
370 0u,\r
371 0u,\r
372 0u,\r
373 0u,\r
374 }\r
375 };\r
376 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
377 unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
378 {\r
379 /* EDMA3 INSTANCE# 0 */\r
380 {\r
381 COMPLETION_INT_A15_XBAR_INST_NO,\r
382 COMPLETION_INT_A15_XBAR_INST_NO,\r
383 COMPLETION_INT_DSP_XBAR_INST_NO,\r
384 COMPLETION_INT_DSP_XBAR_INST_NO,\r
385 COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
386 COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
387 COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
388 COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
389 },\r
390 /* EDMA3 INSTANCE# 1 */\r
391 {\r
392 0u,\r
393 0u,\r
394 0u,\r
395 0u,\r
396 0u,\r
397 0u,\r
398 0u,\r
399 0u\r
400 },\r
401 /* EDMA3 INSTANCE# 2 */\r
402 {\r
403 /* \r
404 * For accessing EVE internal edma,\r
405 * there is no need to configure Xbar.\r
406 * So getting to zero.\r
407 */\r
408 0u,\r
409 0u,\r
410 0u,\r
411 0u,\r
412 0u,\r
413 0u,\r
414 0u,\r
415 0u\r
416 }\r
417 };\r
418 \r
419 /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
420 unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
421 {\r
422 /* EDMA3 INSTANCE# 0 */\r
423 {\r
424 XBAR_EDMA_TPCC_IRQ_REGION0,\r
425 XBAR_EDMA_TPCC_IRQ_REGION1,\r
426 XBAR_EDMA_TPCC_IRQ_REGION2,\r
427 XBAR_EDMA_TPCC_IRQ_REGION3,\r
428 XBAR_EDMA_TPCC_IRQ_REGION4,\r
429 XBAR_EDMA_TPCC_IRQ_REGION5,\r
430 XBAR_EDMA_TPCC_IRQ_REGION6,\r
431 XBAR_EDMA_TPCC_IRQ_REGION7\r
432 },\r
433 /* EDMA3 INSTANCE# 1 */\r
434 {\r
435 XBAR_EDMA_TPCC_IRQ_REGION0,\r
436 XBAR_EDMA_TPCC_IRQ_REGION1,\r
437 XBAR_EDMA_TPCC_IRQ_REGION2,\r
438 XBAR_EDMA_TPCC_IRQ_REGION3,\r
439 XBAR_EDMA_TPCC_IRQ_REGION4,\r
440 XBAR_EDMA_TPCC_IRQ_REGION5,\r
441 XBAR_EDMA_TPCC_IRQ_REGION6,\r
442 XBAR_EDMA_TPCC_IRQ_REGION7\r
443 },\r
444 /* EDMA3 INSTANCE# 2 */\r
445 {\r
446 /* \r
447 * For accessing EVE internal edma,\r
448 * there is no need to configure Xbar.\r
449 * So getting to zero.\r
450 */\r
451 0u,\r
452 0u,\r
453 0u,\r
454 0u,\r
455 0u,\r
456 0u,\r
457 0u,\r
458 0u\r
459 }\r
460 };\r
461 \r
462 /**\r
463 * Variable which will be used internally for referring channel controller's\r
464 * error interrupt.\r
465 */\r
466 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = \r
467 {\r
468 EDMA3_CC_ERROR_INT,\r
469 DSP1_EDMA3_CC_ERROR_INT,\r
470 EDMA3_CC_ERROR_INT\r
471 };\r
472 unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =\r
473 {\r
474 CC_ERROR_INT_XBAR_INST_NO,\r
475 CC_ERROR_INT_XBAR_INST_NO,\r
476 CC_ERROR_INT_XBAR_INST_NO\r
477 };\r
478 unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
479 {\r
480 XBAR_EDMA_TPCC_IRQ_ERR,\r
481 XBAR_EDMA_TPCC_IRQ_ERR,\r
482 XBAR_EDMA_TPCC_IRQ_ERR\r
483 };\r
484 \r
485 /**\r
486 * Variable which will be used internally for referring transfer controllers'\r
487 * error interrupts.\r
488 */\r
489 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
490 {\r
491 /* EDMA3 INSTANCE# 0 */\r
492 {\r
493 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
494 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
495 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
496 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
497 },\r
498 /* EDMA3 INSTANCE# 1 */\r
499 {\r
500 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
501 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
502 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
503 DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
504 },\r
505 /* EDMA3 INSTANCE# 2 */\r
506 {\r
507 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
508 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
509 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
510 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
511 }\r
512 };\r
513 unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
514 {\r
515 /* EDMA3 INSTANCE# 0 */\r
516 {\r
517 TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
518 0u, 0u,\r
519 0u, 0u,\r
520 0u, 0u,\r
521 },\r
522 /* EDMA3 INSTANCE# 1 */\r
523 {\r
524 TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
525 0u, 0u,\r
526 0u, 0u,\r
527 0u, 0u,\r
528 },\r
529 /* EDMA3 INSTANCE# 2 */\r
530 {\r
531 TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
532 0u, 0u,\r
533 0u, 0u,\r
534 0u, 0u,\r
535 }\r
536 };\r
537 \r
538 unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
539 {\r
540 /* EDMA3 INSTANCE# 0 */\r
541 {\r
542 XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
543 0u, 0u,\r
544 0u, 0u, 0u, 0u,\r
545 },\r
546 /* EDMA3 INSTANCE# 1 */\r
547 {\r
548 XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
549 0u, 0u,\r
550 0u, 0u, 0u, 0u,\r
551 },\r
552 /* EDMA3 INSTANCE# 2 */\r
553 {\r
554 XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
555 0u, 0u,\r
556 0u, 0u, 0u, 0u,\r
557 }\r
558 };\r
559 \r
560 \r
561 /**\r
562 * Variables which will be used internally for referring the hardware interrupt\r
563 * for various EDMA3 interrupts.\r
564 */\r
565 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
566 {\r
567 EDMA3_HWI_INT_XFER_COMP,\r
568 EDMA3_HWI_INT_XFER_COMP,\r
569 EDMA3_CC_XFER_COMPLETION_INT\r
570 };\r
571 \r
572 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
573 {\r
574 EDMA3_HWI_INT_CC_ERR,\r
575 EDMA3_HWI_INT_CC_ERR,\r
576 EDMA3_CC_ERROR_INT\r
577 };\r
578 \r
579 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
580 {\r
581 /* EDMA3 INSTANCE# 0 */\r
582 {\r
583 EDMA3_HWI_INT_TC0_ERR,\r
584 EDMA3_HWI_INT_TC1_ERR,\r
585 EDMA3_HWI_INT_TC2_ERR,\r
586 EDMA3_HWI_INT_TC3_ERR\r
587 },\r
588 /* EDMA3 INSTANCE# 1 */\r
589 {\r
590 EDMA3_HWI_INT_TC0_ERR,\r
591 EDMA3_HWI_INT_TC1_ERR,\r
592 EDMA3_HWI_INT_TC2_ERR,\r
593 EDMA3_HWI_INT_TC3_ERR\r
594 },\r
595 /* EDMA3 INSTANCE# 2 */\r
596 {\r
597 EDMA3_TC0_ERROR_INT,\r
598 EDMA3_TC1_ERROR_INT,\r
599 EDMA3_TC2_ERROR_INT,\r
600 EDMA3_TC3_ERROR_INT\r
601 }\r
602 };\r
603 \r
604 /**\r
605 * \brief Base address as seen from the different cores may be different\r
606 * And is defined based on the core\r
607 */\r
608 #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
609 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))\r
610 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))\r
611 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))\r
612 #elif (defined BUILD_TDA2XX_IPU)\r
613 #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))\r
614 #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))\r
615 #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))\r
616 #elif (defined BUILD_TDA2XX_EVE)\r
617 #define EDMA3_CC_BASE_ADDR ((void *)(0x400A0000))\r
618 #define EDMA3_TC0_BASE_ADDR ((void *)(0x40086000))\r
619 #define EDMA3_TC1_BASE_ADDR ((void *)(0x40087000))\r
620 #else\r
621 #define EDMA3_CC_BASE_ADDR ((void *)(0x0))\r
622 #define EDMA3_TC0_BASE_ADDR ((void *)(0x0))\r
623 #define EDMA3_TC1_BASE_ADDR ((void *)(0x0))\r
624 #endif\r
625 \r
626 #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000))\r
627 #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000))\r
628 #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000))\r
629 \r
630 /* Driver Object Initialization Configuration */\r
631 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
632 {\r
633 {\r
634 /* EDMA3 INSTANCE# 0 */\r
635 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
636 EDMA3_NUM_DMA_CHANNELS,\r
637 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
638 EDMA3_NUM_QDMA_CHANNELS,\r
639 /** Total number of TCCs supported by the EDMA3 Controller */\r
640 EDMA3_NUM_TCC,\r
641 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
642 EDMA3_NUM_PARAMSET,\r
643 /** Total number of Event Queues in the EDMA3 Controller */\r
644 EDMA3_NUM_EVTQUE,\r
645 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
646 EDMA3_NUM_TC,\r
647 /** Number of Regions on this EDMA3 controller */\r
648 EDMA3_NUM_REGIONS,\r
649 \r
650 /**\r
651 * \brief Channel mapping existence\r
652 * A value of 0 (No channel mapping) implies that there is fixed association\r
653 * for a channel number to a parameter entry number or, in other words,\r
654 * PaRAM entry n corresponds to channel n.\r
655 */\r
656 1u,\r
657 \r
658 /** Existence of memory protection feature */\r
659 0u,\r
660 \r
661 /** Global Register Region of CC Registers */\r
662 EDMA3_CC_BASE_ADDR,\r
663 /** Transfer Controller (TC) Registers */\r
664 {\r
665 EDMA3_TC0_BASE_ADDR,\r
666 EDMA3_TC1_BASE_ADDR,\r
667 (void *)NULL,\r
668 (void *)NULL,\r
669 (void *)NULL,\r
670 (void *)NULL,\r
671 (void *)NULL,\r
672 (void *)NULL\r
673 },\r
674 /** Interrupt no. for Transfer Completion */\r
675 EDMA3_CC_XFER_COMPLETION_INT,\r
676 /** Interrupt no. for CC Error */\r
677 EDMA3_CC_ERROR_INT,\r
678 /** Interrupt no. for TCs Error */\r
679 {\r
680 EDMA3_TC0_ERROR_INT,\r
681 EDMA3_TC1_ERROR_INT,\r
682 EDMA3_TC2_ERROR_INT,\r
683 EDMA3_TC3_ERROR_INT,\r
684 EDMA3_TC4_ERROR_INT,\r
685 EDMA3_TC5_ERROR_INT,\r
686 EDMA3_TC6_ERROR_INT,\r
687 EDMA3_TC7_ERROR_INT\r
688 },\r
689 \r
690 /**\r
691 * \brief EDMA3 TC priority setting\r
692 *\r
693 * User can program the priority of the Event Queues\r
694 * at a system-wide level. This means that the user can set the\r
695 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
696 * relative to IO initiated by the other bus masters on the\r
697 * device (ARM, DSP, USB, etc)\r
698 */\r
699 {\r
700 0u,\r
701 1u,\r
702 0u,\r
703 0u,\r
704 0u,\r
705 0u,\r
706 0u,\r
707 0u\r
708 },\r
709 /**\r
710 * \brief To Configure the Threshold level of number of events\r
711 * that can be queued up in the Event queues. EDMA3CC error register\r
712 * (CCERR) will indicate whether or not at any instant of time the\r
713 * number of events queued up in any of the event queues exceeds\r
714 * or equals the threshold/watermark value that is set\r
715 * in the queue watermark threshold register (QWMTHRA).\r
716 */\r
717 {\r
718 16u,\r
719 16u,\r
720 0u,\r
721 0u,\r
722 0u,\r
723 0u,\r
724 0u,\r
725 0u\r
726 },\r
727 \r
728 /**\r
729 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
730 * An optimally-sized command is defined by the transfer controller\r
731 * default burst size (DBS). Different TCs can have different\r
732 * DBS values. It is defined in Bytes.\r
733 */\r
734 {\r
735 16u,\r
736 16u,\r
737 0u,\r
738 0u,\r
739 0u,\r
740 0u,\r
741 0u,\r
742 0u\r
743 },\r
744 \r
745 /**\r
746 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
747 * if it exists, otherwise of no use.\r
748 */\r
749 {\r
750 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
751 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
752 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
753 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
754 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
755 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
756 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
757 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
758 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
759 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
760 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
761 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
762 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
763 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
764 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
765 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
766 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
767 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
768 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
769 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
770 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
771 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
772 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
773 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
774 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
775 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
776 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
777 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
778 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
779 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
780 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
781 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
782 },\r
783 \r
784 /**\r
785 * \brief Mapping from each DMA channel to a TCC. This specific\r
786 * TCC code will be returned when the transfer is completed\r
787 * on the mapped channel.\r
788 */\r
789 {\r
790 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
791 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
792 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
793 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
794 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
795 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
796 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
797 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
798 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
799 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
800 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
801 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
802 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
803 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
804 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
805 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
806 },\r
807 \r
808 /**\r
809 * \brief Mapping of DMA channels to Hardware Events from\r
810 * various peripherals, which use EDMA for data transfer.\r
811 * All channels need not be mapped, some can be free also.\r
812 */\r
813 {\r
814 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,\r
815 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA\r
816 }\r
817 },\r
818 {\r
819 /* EDMA3 INSTANCE# 1 */\r
820 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
821 EDMA3_NUM_DMA_CHANNELS,\r
822 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
823 EDMA3_NUM_QDMA_CHANNELS,\r
824 /** Total number of TCCs supported by the EDMA3 Controller */\r
825 EDMA3_NUM_TCC,\r
826 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
827 EDMA3_NUM_PARAMSET,\r
828 /** Total number of Event Queues in the EDMA3 Controller */\r
829 EDMA3_NUM_EVTQUE,\r
830 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
831 EDMA3_NUM_TC,\r
832 /** Number of Regions on this EDMA3 controller */\r
833 EDMA3_NUM_REGIONS,\r
834 \r
835 /**\r
836 * \brief Channel mapping existence\r
837 * A value of 0 (No channel mapping) implies that there is fixed association\r
838 * for a channel number to a parameter entry number or, in other words,\r
839 * PaRAM entry n corresponds to channel n.\r
840 */\r
841 1u,\r
842 \r
843 /** Existence of memory protection feature */\r
844 0u,\r
845 \r
846 /** Global Register Region of CC Registers */\r
847 DSP1_EDMA3_CC_BASE_ADDR,\r
848 /** Transfer Controller (TC) Registers */\r
849 {\r
850 DSP1_EDMA3_TC0_BASE_ADDR,\r
851 DSP1_EDMA3_TC1_BASE_ADDR,\r
852 (void *)NULL,\r
853 (void *)NULL,\r
854 (void *)NULL,\r
855 (void *)NULL,\r
856 (void *)NULL,\r
857 (void *)NULL\r
858 },\r
859 /** Interrupt no. for Transfer Completion */\r
860 DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
861 /** Interrupt no. for CC Error */\r
862 DSP1_EDMA3_CC_ERROR_INT,\r
863 /** Interrupt no. for TCs Error */\r
864 {\r
865 DSP1_EDMA3_TC0_ERROR_INT,\r
866 DSP1_EDMA3_TC1_ERROR_INT,\r
867 EDMA3_TC2_ERROR_INT,\r
868 EDMA3_TC3_ERROR_INT,\r
869 EDMA3_TC4_ERROR_INT,\r
870 EDMA3_TC5_ERROR_INT,\r
871 EDMA3_TC6_ERROR_INT,\r
872 EDMA3_TC7_ERROR_INT\r
873 },\r
874 \r
875 /**\r
876 * \brief EDMA3 TC priority setting\r
877 *\r
878 * User can program the priority of the Event Queues\r
879 * at a system-wide level. This means that the user can set the\r
880 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
881 * relative to IO initiated by the other bus masters on the\r
882 * device (ARM, DSP, USB, etc)\r
883 */\r
884 {\r
885 0u,\r
886 1u,\r
887 0u,\r
888 0u,\r
889 0u,\r
890 0u,\r
891 0u,\r
892 0u\r
893 },\r
894 /**\r
895 * \brief To Configure the Threshold level of number of events\r
896 * that can be queued up in the Event queues. EDMA3CC error register\r
897 * (CCERR) will indicate whether or not at any instant of time the\r
898 * number of events queued up in any of the event queues exceeds\r
899 * or equals the threshold/watermark value that is set\r
900 * in the queue watermark threshold register (QWMTHRA).\r
901 */\r
902 {\r
903 16u,\r
904 16u,\r
905 0u,\r
906 0u,\r
907 0u,\r
908 0u,\r
909 0u,\r
910 0u\r
911 },\r
912 \r
913 /**\r
914 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
915 * An optimally-sized command is defined by the transfer controller\r
916 * default burst size (DBS). Different TCs can have different\r
917 * DBS values. It is defined in Bytes.\r
918 */\r
919 {\r
920 16u,\r
921 16u,\r
922 0u,\r
923 0u,\r
924 0u,\r
925 0u,\r
926 0u,\r
927 0u\r
928 },\r
929 \r
930 /**\r
931 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
932 * if it exists, otherwise of no use.\r
933 */\r
934 {\r
935 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
936 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
937 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
938 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
939 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
940 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
941 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
942 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
943 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
944 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
945 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
946 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
947 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
948 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
949 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
950 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
951 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
952 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
953 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
954 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
955 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
956 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
957 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
958 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
959 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
960 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
961 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
962 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
963 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
964 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
965 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
966 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
967 },\r
968 \r
969 /**\r
970 * \brief Mapping from each DMA channel to a TCC. This specific\r
971 * TCC code will be returned when the transfer is completed\r
972 * on the mapped channel.\r
973 */\r
974 {\r
975 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
976 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
977 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
978 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
979 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
980 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
981 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
982 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
983 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
984 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
985 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
986 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
987 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
988 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
989 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
990 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
991 },\r
992 \r
993 /**\r
994 * \brief Mapping of DMA channels to Hardware Events from\r
995 * various peripherals, which use EDMA for data transfer.\r
996 * All channels need not be mapped, some can be free also.\r
997 */\r
998 {\r
999 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
1000 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
1001 }\r
1002 },\r
1003 {\r
1004 /* EDMA3 INSTANCE# 2 */\r
1005 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
1006 EDMA3_NUM_DMA_CHANNELS,\r
1007 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
1008 EDMA3_NUM_QDMA_CHANNELS,\r
1009 /** Total number of TCCs supported by the EDMA3 Controller */\r
1010 EDMA3_NUM_TCC,\r
1011 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
1012 EDMA3_NUM_PARAMSET,\r
1013 /** Total number of Event Queues in the EDMA3 Controller */\r
1014 EDMA3_NUM_EVTQUE,\r
1015 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
1016 EDMA3_NUM_TC,\r
1017 /** Number of Regions on this EDMA3 controller */\r
1018 EDMA3_NUM_REGIONS,\r
1019 \r
1020 /**\r
1021 * \brief Channel mapping existence\r
1022 * A value of 0 (No channel mapping) implies that there is fixed association\r
1023 * for a channel number to a parameter entry number or, in other words,\r
1024 * PaRAM entry n corresponds to channel n.\r
1025 */\r
1026 1u,\r
1027 \r
1028 /** Existence of memory protection feature */\r
1029 0u,\r
1030 \r
1031 /** Global Register Region of CC Registers */\r
1032 EDMA3_CC_BASE_ADDR,\r
1033 /** Transfer Controller (TC) Registers */\r
1034 {\r
1035 EDMA3_TC0_BASE_ADDR,\r
1036 EDMA3_TC1_BASE_ADDR,\r
1037 (void *)NULL,\r
1038 (void *)NULL,\r
1039 (void *)NULL,\r
1040 (void *)NULL,\r
1041 (void *)NULL,\r
1042 (void *)NULL\r
1043 },\r
1044 /** Interrupt no. for Transfer Completion */\r
1045 EDMA3_CC_XFER_COMPLETION_INT,\r
1046 /** Interrupt no. for CC Error */\r
1047 EDMA3_CC_ERROR_INT,\r
1048 /** Interrupt no. for TCs Error */\r
1049 {\r
1050 EDMA3_TC0_ERROR_INT,\r
1051 EDMA3_TC1_ERROR_INT,\r
1052 EDMA3_TC2_ERROR_INT,\r
1053 EDMA3_TC3_ERROR_INT,\r
1054 EDMA3_TC4_ERROR_INT,\r
1055 EDMA3_TC5_ERROR_INT,\r
1056 EDMA3_TC6_ERROR_INT,\r
1057 EDMA3_TC7_ERROR_INT\r
1058 },\r
1059 \r
1060 /**\r
1061 * \brief EDMA3 TC priority setting\r
1062 *\r
1063 * User can program the priority of the Event Queues\r
1064 * at a system-wide level. This means that the user can set the\r
1065 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
1066 * relative to IO initiated by the other bus masters on the\r
1067 * device (ARM, DSP, USB, etc)\r
1068 */\r
1069 {\r
1070 0u,\r
1071 1u,\r
1072 0u,\r
1073 0u,\r
1074 0u,\r
1075 0u,\r
1076 0u,\r
1077 0u\r
1078 },\r
1079 /**\r
1080 * \brief To Configure the Threshold level of number of events\r
1081 * that can be queued up in the Event queues. EDMA3CC error register\r
1082 * (CCERR) will indicate whether or not at any instant of time the\r
1083 * number of events queued up in any of the event queues exceeds\r
1084 * or equals the threshold/watermark value that is set\r
1085 * in the queue watermark threshold register (QWMTHRA).\r
1086 */\r
1087 {\r
1088 16u,\r
1089 16u,\r
1090 0u,\r
1091 0u,\r
1092 0u,\r
1093 0u,\r
1094 0u,\r
1095 0u\r
1096 },\r
1097 \r
1098 /**\r
1099 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
1100 * An optimally-sized command is defined by the transfer controller\r
1101 * default burst size (DBS). Different TCs can have different\r
1102 * DBS values. It is defined in Bytes.\r
1103 */\r
1104 {\r
1105 16u,\r
1106 16u,\r
1107 0u,\r
1108 0u,\r
1109 0u,\r
1110 0u,\r
1111 0u,\r
1112 0u\r
1113 },\r
1114 \r
1115 /**\r
1116 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
1117 * if it exists, otherwise of no use.\r
1118 */\r
1119 {\r
1120 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1121 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1122 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1123 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1124 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1125 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1126 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1127 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1128 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1129 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1130 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1131 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1132 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1133 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1134 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1135 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1136 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1137 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1138 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1139 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1140 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1141 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1142 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1143 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1144 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1145 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1146 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1147 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1148 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1149 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1150 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1151 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
1152 },\r
1153 \r
1154 /**\r
1155 * \brief Mapping from each DMA channel to a TCC. This specific\r
1156 * TCC code will be returned when the transfer is completed\r
1157 * on the mapped channel.\r
1158 */\r
1159 {\r
1160 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1161 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1162 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1163 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1164 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1165 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1166 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1167 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1168 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1169 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1170 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1171 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1172 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1173 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1174 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1175 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1176 },\r
1177 \r
1178 /**\r
1179 * \brief Mapping of DMA channels to Hardware Events from\r
1180 * various peripherals, which use EDMA for data transfer.\r
1181 * All channels need not be mapped, some can be free also.\r
1182 */\r
1183 {\r
1184 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,\r
1185 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA\r
1186 }\r
1187 },\r
1188 \r
1189 };\r
1190 \r
1191 /**\r
1192 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
1193 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
1194 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
1195 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
1196 *\r
1197 * Only Resources owned by a perticular core are allocated by Driver\r
1198 * Reserved resources are not allocated if requested for any available resource\r
1199 */\r
1200 \r
1201 /* Driver Instance Initialization Configuration */\r
1202 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
1203 {\r
1204 /* EDMA3 INSTANCE# 0 */\r
1205 {\r
1206 /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
1207 {\r
1208 /* ownPaRAMSets */\r
1209 /* 31 0 63 32 95 64 127 96 */\r
1210 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1211 /* 159 128 191 160 223 192 255 224 */\r
1212 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1213 /* 287 256 319 288 351 320 383 352 */\r
1214 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1215 /* 415 384 447 416 479 448 511 480 */\r
1216 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1217 \r
1218 /* ownDmaChannels */\r
1219 /* 31 0 63 32 */\r
1220 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1221 \r
1222 /* ownQdmaChannels */\r
1223 /* 31 0 */\r
1224 {0x000000FFu},\r
1225 \r
1226 /* ownTccs */\r
1227 /* 31 0 63 32 */\r
1228 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1229 \r
1230 /* resvdPaRAMSets */\r
1231 /* 31 0 63 32 95 64 127 96 */\r
1232 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1233 /* 159 128 191 160 223 192 255 224 */\r
1234 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1235 /* 287 256 319 288 351 320 383 352 */\r
1236 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1237 /* 415 384 447 416 479 448 511 480 */\r
1238 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1239 \r
1240 /* resvdDmaChannels */\r
1241 /* 31 0 63 32 */\r
1242 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1243 \r
1244 /* resvdQdmaChannels */\r
1245 /* 31 0 */\r
1246 {0x00u},\r
1247 \r
1248 /* resvdTccs */\r
1249 /* 31 0 63 32 */\r
1250 {0x00u, 0x00u},\r
1251 },\r
1252 \r
1253 /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
1254 {\r
1255 /* ownPaRAMSets */\r
1256 /* 31 0 63 32 95 64 127 96 */\r
1257 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1258 /* 159 128 191 160 223 192 255 224 */\r
1259 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1260 /* 287 256 319 288 351 320 383 352 */\r
1261 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1262 /* 415 384 447 416 479 448 511 480 */\r
1263 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1264 /* \r
1265 * This instance 0 and region 1 is only accessible to MPU core 1.\r
1266 * So other cores should not be access.\r
1267 */\r
1268 #ifdef BUILD_TDA2XX_MPU\r
1269 /* ownDmaChannels */\r
1270 /* 31 0 63 32 */\r
1271 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1272 #else\r
1273 /* ownDmaChannels */\r
1274 /* 31 0 63 32 */\r
1275 {0x00000000u, 0x00000000u},\r
1276 #endif\r
1277 /* ownQdmaChannels */\r
1278 /* 31 0 */\r
1279 {0x000000FFu},\r
1280 \r
1281 /* ownTccs */\r
1282 /* 31 0 63 32 */\r
1283 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1284 \r
1285 /* resvdPaRAMSets */\r
1286 /* 31 0 63 32 95 64 127 96 */\r
1287 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1288 /* 159 128 191 160 223 192 255 224 */\r
1289 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1290 /* 287 256 319 288 351 320 383 352 */\r
1291 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1292 /* 415 384 447 416 479 448 511 480 */\r
1293 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1294 \r
1295 /* resvdDmaChannels */\r
1296 /* 31 0 63 32 */\r
1297 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1298 \r
1299 /* resvdQdmaChannels */\r
1300 /* 31 0 */\r
1301 {0x00u},\r
1302 \r
1303 /* resvdTccs */\r
1304 /* 31 0 63 32 */\r
1305 {0x00u, 0x00u},\r
1306 },\r
1307 \r
1308 /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
1309 {\r
1310 /* ownPaRAMSets */\r
1311 /* 31 0 63 32 95 64 127 96 */\r
1312 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1313 /* 159 128 191 160 223 192 255 224 */\r
1314 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1315 /* 287 256 319 288 351 320 383 352 */\r
1316 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1317 /* 415 384 447 416 479 448 511 480 */\r
1318 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1319 \r
1320 /* ownDmaChannels */\r
1321 /* 31 0 63 32 */\r
1322 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1323 \r
1324 /* ownQdmaChannels */\r
1325 /* 31 0 */\r
1326 {0x000000FFu},\r
1327 \r
1328 /* ownTccs */\r
1329 /* 31 0 63 32 */\r
1330 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1331 \r
1332 /* resvdPaRAMSets */\r
1333 /* 31 0 63 32 95 64 127 96 */\r
1334 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1335 /* 159 128 191 160 223 192 255 224 */\r
1336 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1337 /* 287 256 319 288 351 320 383 352 */\r
1338 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1339 /* 415 384 447 416 479 448 511 480 */\r
1340 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1341 \r
1342 /* resvdDmaChannels */\r
1343 /* 31 0 63 32 */\r
1344 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1345 \r
1346 /* resvdQdmaChannels */\r
1347 /* 31 0 */\r
1348 {0x00u},\r
1349 \r
1350 /* resvdTccs */\r
1351 /* 31 0 63 32 */\r
1352 {0x00u, 0x00u},\r
1353 },\r
1354 \r
1355 /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
1356 {\r
1357 /* ownPaRAMSets */\r
1358 /* 31 0 63 32 95 64 127 96 */\r
1359 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1360 /* 159 128 191 160 223 192 255 224 */\r
1361 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1362 /* 287 256 319 288 351 320 383 352 */\r
1363 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1364 /* 415 384 447 416 479 448 511 480 */\r
1365 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1366 \r
1367 /* ownDmaChannels */\r
1368 /* 31 0 63 32 */\r
1369 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1370 \r
1371 /* ownQdmaChannels */\r
1372 /* 31 0 */\r
1373 {0x000000FFu},\r
1374 \r
1375 /* ownTccs */\r
1376 /* 31 0 63 32 */\r
1377 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1378 \r
1379 /* resvdPaRAMSets */\r
1380 /* 31 0 63 32 95 64 127 96 */\r
1381 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1382 /* 159 128 191 160 223 192 255 224 */\r
1383 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1384 /* 287 256 319 288 351 320 383 352 */\r
1385 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1386 /* 415 384 447 416 479 448 511 480 */\r
1387 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1388 \r
1389 /* resvdDmaChannels */\r
1390 /* 31 0 63 32 */\r
1391 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1392 \r
1393 /* resvdQdmaChannels */\r
1394 /* 31 0 */\r
1395 {0x00u},\r
1396 \r
1397 /* resvdTccs */\r
1398 /* 31 0 63 32 */\r
1399 {0x00u, 0x00u},\r
1400 },\r
1401 \r
1402 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
1403 {\r
1404 /* ownPaRAMSets */\r
1405 /* 31 0 63 32 95 64 127 96 */\r
1406 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1407 /* 159 128 191 160 223 192 255 224 */\r
1408 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1409 /* 287 256 319 288 351 320 383 352 */\r
1410 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1411 /* 415 384 447 416 479 448 511 480 */\r
1412 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1413 \r
1414 /* ownDmaChannels */\r
1415 /* 31 0 63 32 */\r
1416 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1417 \r
1418 /* ownQdmaChannels */\r
1419 /* 31 0 */\r
1420 {0x000000FFu},\r
1421 \r
1422 /* ownTccs */\r
1423 /* 31 0 63 32 */\r
1424 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1425 \r
1426 /* resvdPaRAMSets */\r
1427 /* 31 0 63 32 95 64 127 96 */\r
1428 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1429 /* 159 128 191 160 223 192 255 224 */\r
1430 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1431 /* 287 256 319 288 351 320 383 352 */\r
1432 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1433 /* 415 384 447 416 479 448 511 480 */\r
1434 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1435 \r
1436 /* resvdDmaChannels */\r
1437 /* 31 0 63 32 */\r
1438 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1439 \r
1440 /* resvdQdmaChannels */\r
1441 /* 31 0 */\r
1442 {0x00u},\r
1443 \r
1444 /* resvdTccs */\r
1445 /* 31 0 63 32 */\r
1446 {0x00u, 0x00u},\r
1447 },\r
1448 \r
1449 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
1450 {\r
1451 /* ownPaRAMSets */\r
1452 /* 31 0 63 32 95 64 127 96 */\r
1453 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1454 /* 159 128 191 160 223 192 255 224 */\r
1455 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1456 /* 287 256 319 288 351 320 383 352 */\r
1457 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1458 /* 415 384 447 416 479 448 511 480 */\r
1459 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1460 \r
1461 /* ownDmaChannels */\r
1462 /* 31 0 63 32 */\r
1463 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1464 \r
1465 /* ownQdmaChannels */\r
1466 /* 31 0 */\r
1467 {0x000000FFu},\r
1468 \r
1469 /* ownTccs */\r
1470 /* 31 0 63 32 */\r
1471 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1472 \r
1473 /* resvdPaRAMSets */\r
1474 /* 31 0 63 32 95 64 127 96 */\r
1475 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1476 /* 159 128 191 160 223 192 255 224 */\r
1477 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1478 /* 287 256 319 288 351 320 383 352 */\r
1479 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1480 /* 415 384 447 416 479 448 511 480 */\r
1481 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1482 \r
1483 /* resvdDmaChannels */\r
1484 /* 31 0 63 32 */\r
1485 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1486 \r
1487 /* resvdQdmaChannels */\r
1488 /* 31 0 */\r
1489 {0x00u},\r
1490 \r
1491 /* resvdTccs */\r
1492 /* 31 0 63 32 */\r
1493 {0x00u, 0x00u},\r
1494 },\r
1495 \r
1496 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
1497 {\r
1498 /* ownPaRAMSets */\r
1499 /* 31 0 63 32 95 64 127 96 */\r
1500 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1501 /* 159 128 191 160 223 192 255 224 */\r
1502 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1503 /* 287 256 319 288 351 320 383 352 */\r
1504 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1505 /* 415 384 447 416 479 448 511 480 */\r
1506 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1507 \r
1508 /* ownDmaChannels */\r
1509 /* 31 0 63 32 */\r
1510 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1511 \r
1512 /* ownQdmaChannels */\r
1513 /* 31 0 */\r
1514 {0x000000FFu},\r
1515 \r
1516 /* ownTccs */\r
1517 /* 31 0 63 32 */\r
1518 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1519 \r
1520 /* resvdPaRAMSets */\r
1521 /* 31 0 63 32 95 64 127 96 */\r
1522 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1523 /* 159 128 191 160 223 192 255 224 */\r
1524 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1525 /* 287 256 319 288 351 320 383 352 */\r
1526 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1527 /* 415 384 447 416 479 448 511 480 */\r
1528 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1529 \r
1530 /* resvdDmaChannels */\r
1531 /* 31 0 63 32 */\r
1532 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1533 \r
1534 /* resvdQdmaChannels */\r
1535 /* 31 0 */\r
1536 {0x00u},\r
1537 \r
1538 /* resvdTccs */\r
1539 /* 31 0 63 32 */\r
1540 {0x00u, 0x00u},\r
1541 },\r
1542 \r
1543 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
1544 {\r
1545 /* ownPaRAMSets */\r
1546 /* 31 0 63 32 95 64 127 96 */\r
1547 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1548 /* 159 128 191 160 223 192 255 224 */\r
1549 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1550 /* 287 256 319 288 351 320 383 352 */\r
1551 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1552 /* 415 384 447 416 479 448 511 480 */\r
1553 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1554 \r
1555 /* ownDmaChannels */\r
1556 /* 31 0 63 32 */\r
1557 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1558 \r
1559 /* ownQdmaChannels */\r
1560 /* 31 0 */\r
1561 {0x000000FFu},\r
1562 \r
1563 /* ownTccs */\r
1564 /* 31 0 63 32 */\r
1565 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1566 \r
1567 /* resvdPaRAMSets */\r
1568 /* 31 0 63 32 95 64 127 96 */\r
1569 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1570 /* 159 128 191 160 223 192 255 224 */\r
1571 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1572 /* 287 256 319 288 351 320 383 352 */\r
1573 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1574 /* 415 384 447 416 479 448 511 480 */\r
1575 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1576 \r
1577 /* resvdDmaChannels */\r
1578 /* 31 0 63 32 */\r
1579 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1580 \r
1581 /* resvdQdmaChannels */\r
1582 /* 31 0 */\r
1583 {0x00u},\r
1584 \r
1585 /* resvdTccs */\r
1586 /* 31 0 63 32 */\r
1587 {0x00u, 0x00u},\r
1588 },\r
1589 },\r
1590 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
1591 {\r
1592 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1593 {\r
1594 /* ownPaRAMSets */\r
1595 /* 31 0 63 32 95 64 127 96 */\r
1596 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1597 /* 159 128 191 160 223 192 255 224 */\r
1598 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1599 /* 287 256 319 288 351 320 383 352 */\r
1600 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1601 /* 415 384 447 416 479 448 511 480 */\r
1602 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1603 \r
1604 /* ownDmaChannels */\r
1605 /* 31 0 63 32 */\r
1606 {0x00000000u, 0x00000000u},\r
1607 \r
1608 /* ownQdmaChannels */\r
1609 /* 31 0 */\r
1610 {0x00000000u},\r
1611 \r
1612 /* ownTccs */\r
1613 /* 31 0 63 32 */\r
1614 {0x00000000u, 0x00000000u},\r
1615 \r
1616 /* resvdPaRAMSets */\r
1617 /* 31 0 63 32 95 64 127 96 */\r
1618 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1619 /* 159 128 191 160 223 192 255 224 */\r
1620 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1621 /* 287 256 319 288 351 320 383 352 */\r
1622 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1623 /* 415 384 447 416 479 448 511 480 */\r
1624 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1625 \r
1626 /* resvdDmaChannels */\r
1627 /* 31 0 63 32 */\r
1628 {0x00000000u, 0x00000000u},\r
1629 \r
1630 /* resvdQdmaChannels */\r
1631 /* 31 0 */\r
1632 {0x00000000u},\r
1633 \r
1634 /* resvdTccs */\r
1635 /* 31 0 63 32 */\r
1636 {0x00000000u, 0x00000000u},\r
1637 },\r
1638 \r
1639 /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
1640 {\r
1641 /* ownPaRAMSets */\r
1642 /* 31 0 63 32 95 64 127 96 */\r
1643 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1644 /* 159 128 191 160 223 192 255 224 */\r
1645 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1646 /* 287 256 319 288 351 320 383 352 */\r
1647 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1648 /* 415 384 447 416 479 448 511 480 */\r
1649 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1650 \r
1651 /* ownDmaChannels */\r
1652 /* 31 0 63 32 */\r
1653 {0x00000000u, 0x00000000u},\r
1654 \r
1655 /* ownQdmaChannels */\r
1656 /* 31 0 */\r
1657 {0x00000000u},\r
1658 \r
1659 /* ownTccs */\r
1660 /* 31 0 63 32 */\r
1661 {0x00000000u, 0x00000000u},\r
1662 \r
1663 /* resvdPaRAMSets */\r
1664 /* 31 0 63 32 95 64 127 96 */\r
1665 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1666 /* 159 128 191 160 223 192 255 224 */\r
1667 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1668 /* 287 256 319 288 351 320 383 352 */\r
1669 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1670 /* 415 384 447 416 479 448 511 480 */\r
1671 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1672 \r
1673 /* resvdDmaChannels */\r
1674 /* 31 0 63 32 */\r
1675 {0x00000000u, 0x00000000u},\r
1676 \r
1677 /* resvdQdmaChannels */\r
1678 /* 31 0 */\r
1679 {0x00000000u},\r
1680 \r
1681 /* resvdTccs */\r
1682 /* 31 0 63 32 */\r
1683 {0x00000000u, 0x00000000u},\r
1684 },\r
1685 \r
1686 /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
1687 {\r
1688 /* ownPaRAMSets */\r
1689 /* 31 0 63 32 95 64 127 96 */\r
1690 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1691 /* 159 128 191 160 223 192 255 224 */\r
1692 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1693 /* 287 256 319 288 351 320 383 352 */\r
1694 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1695 /* 415 384 447 416 479 448 511 480 */\r
1696 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1697 \r
1698 /* ownDmaChannels */\r
1699 /* 31 0 63 32 */\r
1700 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1701 \r
1702 /* ownQdmaChannels */\r
1703 /* 31 0 */\r
1704 {0x000000FFu},\r
1705 \r
1706 /* ownTccs */\r
1707 /* 31 0 63 32 */\r
1708 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1709 \r
1710 /* resvdPaRAMSets */\r
1711 /* 31 0 63 32 95 64 127 96 */\r
1712 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1713 /* 159 128 191 160 223 192 255 224 */\r
1714 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1715 /* 287 256 319 288 351 320 383 352 */\r
1716 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1717 /* 415 384 447 416 479 448 511 480 */\r
1718 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1719 \r
1720 /* resvdDmaChannels */\r
1721 /* 31 0 63 32 */\r
1722 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1723 \r
1724 /* resvdQdmaChannels */\r
1725 /* 31 0 */\r
1726 {0x00u},\r
1727 \r
1728 /* resvdTccs */\r
1729 /* 31 0 63 32 */\r
1730 {0x00u, 0x00u},\r
1731 },\r
1732 \r
1733 /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
1734 {\r
1735 /* ownPaRAMSets */\r
1736 /* 31 0 63 32 95 64 127 96 */\r
1737 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1738 /* 159 128 191 160 223 192 255 224 */\r
1739 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1740 /* 287 256 319 288 351 320 383 352 */\r
1741 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1742 /* 415 384 447 416 479 448 511 480 */\r
1743 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1744 \r
1745 /* ownDmaChannels */\r
1746 /* 31 0 63 32 */\r
1747 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1748 \r
1749 /* ownQdmaChannels */\r
1750 /* 31 0 */\r
1751 {0x000000FFu},\r
1752 \r
1753 /* ownTccs */\r
1754 /* 31 0 63 32 */\r
1755 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1756 \r
1757 /* resvdPaRAMSets */\r
1758 /* 31 0 63 32 95 64 127 96 */\r
1759 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1760 /* 159 128 191 160 223 192 255 224 */\r
1761 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1762 /* 287 256 319 288 351 320 383 352 */\r
1763 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1764 /* 415 384 447 416 479 448 511 480 */\r
1765 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1766 \r
1767 /* resvdDmaChannels */\r
1768 /* 31 0 63 32 */\r
1769 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1770 \r
1771 /* resvdQdmaChannels */\r
1772 /* 31 0 */\r
1773 {0x00u},\r
1774 \r
1775 /* resvdTccs */\r
1776 /* 31 0 63 32 */\r
1777 {0x00u, 0x00u},\r
1778 },\r
1779 \r
1780 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1781 {\r
1782 /* ownPaRAMSets */\r
1783 /* 31 0 63 32 95 64 127 96 */\r
1784 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1785 /* 159 128 191 160 223 192 255 224 */\r
1786 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1787 /* 287 256 319 288 351 320 383 352 */\r
1788 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1789 /* 415 384 447 416 479 448 511 480 */\r
1790 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1791 \r
1792 /* ownDmaChannels */\r
1793 /* 31 0 63 32 */\r
1794 {0x00000000u, 0x00000000u},\r
1795 \r
1796 /* ownQdmaChannels */\r
1797 /* 31 0 */\r
1798 {0x00000000u},\r
1799 \r
1800 /* ownTccs */\r
1801 /* 31 0 63 32 */\r
1802 {0x00000000u, 0x00000000u},\r
1803 \r
1804 /* resvdPaRAMSets */\r
1805 /* 31 0 63 32 95 64 127 96 */\r
1806 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1807 /* 159 128 191 160 223 192 255 224 */\r
1808 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1809 /* 287 256 319 288 351 320 383 352 */\r
1810 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1811 /* 415 384 447 416 479 448 511 480 */\r
1812 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1813 \r
1814 /* resvdDmaChannels */\r
1815 /* 31 0 63 32 */\r
1816 {0x00000000u, 0x00000000u},\r
1817 \r
1818 /* resvdQdmaChannels */\r
1819 /* 31 0 */\r
1820 {0x00000000u},\r
1821 \r
1822 /* resvdTccs */\r
1823 /* 31 0 63 32 */\r
1824 {0x00000000u, 0x00000000u},\r
1825 },\r
1826 \r
1827 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1828 {\r
1829 /* ownPaRAMSets */\r
1830 /* 31 0 63 32 95 64 127 96 */\r
1831 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1832 /* 159 128 191 160 223 192 255 224 */\r
1833 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1834 /* 287 256 319 288 351 320 383 352 */\r
1835 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1836 /* 415 384 447 416 479 448 511 480 */\r
1837 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1838 \r
1839 /* ownDmaChannels */\r
1840 /* 31 0 63 32 */\r
1841 {0x00000000u, 0x00000000u},\r
1842 \r
1843 /* ownQdmaChannels */\r
1844 /* 31 0 */\r
1845 {0x00000000u},\r
1846 \r
1847 /* ownTccs */\r
1848 /* 31 0 63 32 */\r
1849 {0x00000000u, 0x00000000u},\r
1850 \r
1851 /* resvdPaRAMSets */\r
1852 /* 31 0 63 32 95 64 127 96 */\r
1853 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1854 /* 159 128 191 160 223 192 255 224 */\r
1855 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1856 /* 287 256 319 288 351 320 383 352 */\r
1857 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1858 /* 415 384 447 416 479 448 511 480 */\r
1859 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1860 \r
1861 /* resvdDmaChannels */\r
1862 /* 31 0 63 32 */\r
1863 {0x00000000u, 0x00000000u},\r
1864 \r
1865 /* resvdQdmaChannels */\r
1866 /* 31 0 */\r
1867 {0x00000000u},\r
1868 \r
1869 /* resvdTccs */\r
1870 /* 31 0 63 32 */\r
1871 {0x00000000u, 0x00000000u},\r
1872 },\r
1873 \r
1874 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1875 {\r
1876 /* ownPaRAMSets */\r
1877 /* 31 0 63 32 95 64 127 96 */\r
1878 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1879 /* 159 128 191 160 223 192 255 224 */\r
1880 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1881 /* 287 256 319 288 351 320 383 352 */\r
1882 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1883 /* 415 384 447 416 479 448 511 480 */\r
1884 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1885 \r
1886 /* ownDmaChannels */\r
1887 /* 31 0 63 32 */\r
1888 {0x00000000u, 0x00000000u},\r
1889 \r
1890 /* ownQdmaChannels */\r
1891 /* 31 0 */\r
1892 {0x00000000u},\r
1893 \r
1894 /* ownTccs */\r
1895 /* 31 0 63 32 */\r
1896 {0x00000000u, 0x00000000u},\r
1897 \r
1898 /* resvdPaRAMSets */\r
1899 /* 31 0 63 32 95 64 127 96 */\r
1900 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1901 /* 159 128 191 160 223 192 255 224 */\r
1902 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1903 /* 287 256 319 288 351 320 383 352 */\r
1904 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1905 /* 415 384 447 416 479 448 511 480 */\r
1906 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1907 \r
1908 /* resvdDmaChannels */\r
1909 /* 31 0 63 32 */\r
1910 {0x00000000u, 0x00000000u},\r
1911 \r
1912 /* resvdQdmaChannels */\r
1913 /* 31 0 */\r
1914 {0x00000000u},\r
1915 \r
1916 /* resvdTccs */\r
1917 /* 31 0 63 32 */\r
1918 {0x00000000u, 0x00000000u},\r
1919 },\r
1920 \r
1921 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1922 {\r
1923 /* ownPaRAMSets */\r
1924 /* 31 0 63 32 95 64 127 96 */\r
1925 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1926 /* 159 128 191 160 223 192 255 224 */\r
1927 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1928 /* 287 256 319 288 351 320 383 352 */\r
1929 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1930 /* 415 384 447 416 479 448 511 480 */\r
1931 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1932 \r
1933 /* ownDmaChannels */\r
1934 /* 31 0 63 32 */\r
1935 {0x00000000u, 0x00000000u},\r
1936 \r
1937 /* ownQdmaChannels */\r
1938 /* 31 0 */\r
1939 {0x00000000u},\r
1940 \r
1941 /* ownTccs */\r
1942 /* 31 0 63 32 */\r
1943 {0x00000000u, 0x00000000u},\r
1944 \r
1945 /* resvdPaRAMSets */\r
1946 /* 31 0 63 32 95 64 127 96 */\r
1947 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1948 /* 159 128 191 160 223 192 255 224 */\r
1949 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1950 /* 287 256 319 288 351 320 383 352 */\r
1951 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1952 /* 415 384 447 416 479 448 511 480 */\r
1953 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1954 \r
1955 /* resvdDmaChannels */\r
1956 /* 31 0 63 32 */\r
1957 {0x00000000u, 0x00000000u},\r
1958 \r
1959 /* resvdQdmaChannels */\r
1960 /* 31 0 */\r
1961 {0x00000000u},\r
1962 \r
1963 /* resvdTccs */\r
1964 /* 31 0 63 32 */\r
1965 {0x00000000u, 0x00000000u},\r
1966 },\r
1967 },\r
1968 /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
1969 {\r
1970 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1971 {\r
1972 /* ownPaRAMSets */\r
1973 /* 31 0 63 32 95 64 127 96 */\r
1974 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1975 /* 159 128 191 160 223 192 255 224 */\r
1976 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1977 /* 287 256 319 288 351 320 383 352 */\r
1978 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1979 /* 415 384 447 416 479 448 511 480 */\r
1980 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1981 \r
1982 /* ownDmaChannels */\r
1983 /* 31 0 63 32 */\r
1984 {0x00000000u, 0x00000000u},\r
1985 \r
1986 /* ownQdmaChannels */\r
1987 /* 31 0 */\r
1988 {0x00000000u},\r
1989 \r
1990 /* ownTccs */\r
1991 /* 31 0 63 32 */\r
1992 {0x00000000u, 0x00000000u},\r
1993 \r
1994 /* resvdPaRAMSets */\r
1995 /* 31 0 63 32 95 64 127 96 */\r
1996 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1997 /* 159 128 191 160 223 192 255 224 */\r
1998 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1999 /* 287 256 319 288 351 320 383 352 */\r
2000 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2001 /* 415 384 447 416 479 448 511 480 */\r
2002 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2003 \r
2004 /* resvdDmaChannels */\r
2005 /* 31 0 63 32 */\r
2006 {0x00000000u, 0x00000000u},\r
2007 \r
2008 /* resvdQdmaChannels */\r
2009 /* 31 0 */\r
2010 {0x00000000u},\r
2011 \r
2012 /* resvdTccs */\r
2013 /* 31 0 63 32 */\r
2014 {0x00000000u, 0x00000000u},\r
2015 },\r
2016 \r
2017 /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
2018 {\r
2019 /* ownPaRAMSets */\r
2020 /* 31 0 63 32 95 64 127 96 */\r
2021 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
2022 /* 159 128 191 160 223 192 255 224 */\r
2023 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2024 /* 287 256 319 288 351 320 383 352 */\r
2025 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2026 /* 415 384 447 416 479 448 511 480 */\r
2027 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
2028 \r
2029 /* ownDmaChannels */\r
2030 /* 31 0 63 32 */\r
2031 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
2032 \r
2033 /* ownQdmaChannels */\r
2034 /* 31 0 */\r
2035 {0x000000FFu},\r
2036 \r
2037 /* ownTccs */\r
2038 /* 31 0 63 32 */\r
2039 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
2040 \r
2041 /* resvdPaRAMSets */\r
2042 /* 31 0 63 32 95 64 127 96 */\r
2043 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
2044 /* 159 128 191 160 223 192 255 224 */\r
2045 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2046 /* 287 256 319 288 351 320 383 352 */\r
2047 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2048 /* 415 384 447 416 479 448 511 480 */\r
2049 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2050 \r
2051 /* resvdDmaChannels */\r
2052 /* 31 0 63 32 */\r
2053 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},\r
2054 \r
2055 /* resvdQdmaChannels */\r
2056 /* 31 0 */\r
2057 {0x00u},\r
2058 \r
2059 /* resvdTccs */\r
2060 /* 31 0 63 32 */\r
2061 {0x00u, 0x00u},\r
2062 },\r
2063 \r
2064 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
2065 {\r
2066 /* ownPaRAMSets */\r
2067 /* 31 0 63 32 95 64 127 96 */\r
2068 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2069 /* 159 128 191 160 223 192 255 224 */\r
2070 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2071 /* 287 256 319 288 351 320 383 352 */\r
2072 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2073 /* 415 384 447 416 479 448 511 480 */\r
2074 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2075 \r
2076 /* ownDmaChannels */\r
2077 /* 31 0 63 32 */\r
2078 {0x00000000u, 0x00000000u},\r
2079 \r
2080 /* ownQdmaChannels */\r
2081 /* 31 0 */\r
2082 {0x00000000u},\r
2083 \r
2084 /* ownTccs */\r
2085 /* 31 0 63 32 */\r
2086 {0x00000000u, 0x00000000u},\r
2087 \r
2088 /* resvdPaRAMSets */\r
2089 /* 31 0 63 32 95 64 127 96 */\r
2090 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2091 /* 159 128 191 160 223 192 255 224 */\r
2092 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2093 /* 287 256 319 288 351 320 383 352 */\r
2094 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2095 /* 415 384 447 416 479 448 511 480 */\r
2096 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2097 \r
2098 /* resvdDmaChannels */\r
2099 /* 31 0 63 32 */\r
2100 {0x00000000u, 0x00000000u},\r
2101 \r
2102 /* resvdQdmaChannels */\r
2103 /* 31 0 */\r
2104 {0x00000000u},\r
2105 \r
2106 /* resvdTccs */\r
2107 /* 31 0 63 32 */\r
2108 {0x00000000u, 0x00000000u},\r
2109 },\r
2110 \r
2111 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
2112 {\r
2113 /* ownPaRAMSets */\r
2114 /* 31 0 63 32 95 64 127 96 */\r
2115 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2116 /* 159 128 191 160 223 192 255 224 */\r
2117 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2118 /* 287 256 319 288 351 320 383 352 */\r
2119 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2120 /* 415 384 447 416 479 448 511 480 */\r
2121 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2122 \r
2123 /* ownDmaChannels */\r
2124 /* 31 0 63 32 */\r
2125 {0x00000000u, 0x00000000u},\r
2126 \r
2127 /* ownQdmaChannels */\r
2128 /* 31 0 */\r
2129 {0x00000000u},\r
2130 \r
2131 /* ownTccs */\r
2132 /* 31 0 63 32 */\r
2133 {0x00000000u, 0x00000000u},\r
2134 \r
2135 /* resvdPaRAMSets */\r
2136 /* 31 0 63 32 95 64 127 96 */\r
2137 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2138 /* 159 128 191 160 223 192 255 224 */\r
2139 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2140 /* 287 256 319 288 351 320 383 352 */\r
2141 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2142 /* 415 384 447 416 479 448 511 480 */\r
2143 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2144 \r
2145 /* resvdDmaChannels */\r
2146 /* 31 0 63 32 */\r
2147 {0x00000000u, 0x00000000u},\r
2148 \r
2149 /* resvdQdmaChannels */\r
2150 /* 31 0 */\r
2151 {0x00000000u},\r
2152 \r
2153 /* resvdTccs */\r
2154 /* 31 0 63 32 */\r
2155 {0x00000000u, 0x00000000u},\r
2156 },\r
2157 \r
2158 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
2159 {\r
2160 /* ownPaRAMSets */\r
2161 /* 31 0 63 32 95 64 127 96 */\r
2162 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2163 /* 159 128 191 160 223 192 255 224 */\r
2164 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2165 /* 287 256 319 288 351 320 383 352 */\r
2166 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2167 /* 415 384 447 416 479 448 511 480 */\r
2168 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2169 \r
2170 /* ownDmaChannels */\r
2171 /* 31 0 63 32 */\r
2172 {0x00000000u, 0x00000000u},\r
2173 \r
2174 /* ownQdmaChannels */\r
2175 /* 31 0 */\r
2176 {0x00000000u},\r
2177 \r
2178 /* ownTccs */\r
2179 /* 31 0 63 32 */\r
2180 {0x00000000u, 0x00000000u},\r
2181 \r
2182 /* resvdPaRAMSets */\r
2183 /* 31 0 63 32 95 64 127 96 */\r
2184 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2185 /* 159 128 191 160 223 192 255 224 */\r
2186 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2187 /* 287 256 319 288 351 320 383 352 */\r
2188 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2189 /* 415 384 447 416 479 448 511 480 */\r
2190 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2191 \r
2192 /* resvdDmaChannels */\r
2193 /* 31 0 63 32 */\r
2194 {0x00000000u, 0x00000000u},\r
2195 \r
2196 /* resvdQdmaChannels */\r
2197 /* 31 0 */\r
2198 {0x00000000u},\r
2199 \r
2200 /* resvdTccs */\r
2201 /* 31 0 63 32 */\r
2202 {0x00000000u, 0x00000000u},\r
2203 },\r
2204 \r
2205 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
2206 {\r
2207 /* ownPaRAMSets */\r
2208 /* 31 0 63 32 95 64 127 96 */\r
2209 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2210 /* 159 128 191 160 223 192 255 224 */\r
2211 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2212 /* 287 256 319 288 351 320 383 352 */\r
2213 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2214 /* 415 384 447 416 479 448 511 480 */\r
2215 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2216 \r
2217 /* ownDmaChannels */\r
2218 /* 31 0 63 32 */\r
2219 {0x00000000u, 0x00000000u},\r
2220 \r
2221 /* ownQdmaChannels */\r
2222 /* 31 0 */\r
2223 {0x00000000u},\r
2224 \r
2225 /* ownTccs */\r
2226 /* 31 0 63 32 */\r
2227 {0x00000000u, 0x00000000u},\r
2228 \r
2229 /* resvdPaRAMSets */\r
2230 /* 31 0 63 32 95 64 127 96 */\r
2231 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2232 /* 159 128 191 160 223 192 255 224 */\r
2233 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2234 /* 287 256 319 288 351 320 383 352 */\r
2235 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2236 /* 415 384 447 416 479 448 511 480 */\r
2237 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2238 \r
2239 /* resvdDmaChannels */\r
2240 /* 31 0 63 32 */\r
2241 {0x00000000u, 0x00000000u},\r
2242 \r
2243 /* resvdQdmaChannels */\r
2244 /* 31 0 */\r
2245 {0x00000000u},\r
2246 \r
2247 /* resvdTccs */\r
2248 /* 31 0 63 32 */\r
2249 {0x00000000u, 0x00000000u},\r
2250 },\r
2251 \r
2252 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
2253 {\r
2254 /* ownPaRAMSets */\r
2255 /* 31 0 63 32 95 64 127 96 */\r
2256 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2257 /* 159 128 191 160 223 192 255 224 */\r
2258 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2259 /* 287 256 319 288 351 320 383 352 */\r
2260 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2261 /* 415 384 447 416 479 448 511 480 */\r
2262 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2263 \r
2264 /* ownDmaChannels */\r
2265 /* 31 0 63 32 */\r
2266 {0x00000000u, 0x00000000u},\r
2267 \r
2268 /* ownQdmaChannels */\r
2269 /* 31 0 */\r
2270 {0x00000000u},\r
2271 \r
2272 /* ownTccs */\r
2273 /* 31 0 63 32 */\r
2274 {0x00000000u, 0x00000000u},\r
2275 \r
2276 /* resvdPaRAMSets */\r
2277 /* 31 0 63 32 95 64 127 96 */\r
2278 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2279 /* 159 128 191 160 223 192 255 224 */\r
2280 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2281 /* 287 256 319 288 351 320 383 352 */\r
2282 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2283 /* 415 384 447 416 479 448 511 480 */\r
2284 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2285 \r
2286 /* resvdDmaChannels */\r
2287 /* 31 0 63 32 */\r
2288 {0x00000000u, 0x00000000u},\r
2289 \r
2290 /* resvdQdmaChannels */\r
2291 /* 31 0 */\r
2292 {0x00000000u},\r
2293 \r
2294 /* resvdTccs */\r
2295 /* 31 0 63 32 */\r
2296 {0x00000000u, 0x00000000u},\r
2297 },\r
2298 \r
2299 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
2300 {\r
2301 /* ownPaRAMSets */\r
2302 /* 31 0 63 32 95 64 127 96 */\r
2303 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2304 /* 159 128 191 160 223 192 255 224 */\r
2305 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2306 /* 287 256 319 288 351 320 383 352 */\r
2307 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2308 /* 415 384 447 416 479 448 511 480 */\r
2309 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2310 \r
2311 /* ownDmaChannels */\r
2312 /* 31 0 63 32 */\r
2313 {0x00000000u, 0x00000000u},\r
2314 \r
2315 /* ownQdmaChannels */\r
2316 /* 31 0 */\r
2317 {0x00000000u},\r
2318 \r
2319 /* ownTccs */\r
2320 /* 31 0 63 32 */\r
2321 {0x00000000u, 0x00000000u},\r
2322 \r
2323 /* resvdPaRAMSets */\r
2324 /* 31 0 63 32 95 64 127 96 */\r
2325 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2326 /* 159 128 191 160 223 192 255 224 */\r
2327 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2328 /* 287 256 319 288 351 320 383 352 */\r
2329 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
2330 /* 415 384 447 416 479 448 511 480 */\r
2331 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
2332 \r
2333 /* resvdDmaChannels */\r
2334 /* 31 0 63 32 */\r
2335 {0x00000000u, 0x00000000u},\r
2336 \r
2337 /* resvdQdmaChannels */\r
2338 /* 31 0 */\r
2339 {0x00000000u},\r
2340 \r
2341 /* resvdTccs */\r
2342 /* 31 0 63 32 */\r
2343 {0x00000000u, 0x00000000u},\r
2344 },\r
2345 },\r
2346 };\r
2347 \r
2348 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
2349 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
2350 {\r
2351 /* EDMA3 INSTANCE# 0 */\r
2352 {\r
2353 /* Event to channel map for region 0 */\r
2354 {\r
2355 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2356 -1, -1, -1, -1, -1, -1, -1, -1,\r
2357 -1, -1, -1, -1, -1, -1, -1, -1,\r
2358 -1, -1, -1, -1, -1, -1, -1, -1,\r
2359 -1, -1, -1, -1, -1, -1, -1, -1,\r
2360 -1, -1, -1, -1, -1, -1, -1, -1,\r
2361 -1, -1, -1, -1, -1, -1, -1, -1,\r
2362 -1, -1, -1, -1, -1, -1, -1}\r
2363 },\r
2364 /* Event to channel map for region 1 */\r
2365 {\r
2366 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2367 -1, -1, -1, -1, -1, -1, -1, -1,\r
2368 -1, -1, -1, -1, -1, -1, -1, -1,\r
2369 -1, -1, -1, -1, -1, -1, -1, -1,\r
2370 -1, -1, -1, -1, -1, -1, -1, -1,\r
2371 -1, -1, -1, -1, -1, -1, -1, -1,\r
2372 -1, -1, -1, -1, -1, -1, -1, -1,\r
2373 -1, -1, -1, -1, -1, -1, -1}\r
2374 },\r
2375 /* Event to channel map for region 2 */\r
2376 {\r
2377 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2378 -1, -1, -1, -1, -1, -1, -1, -1,\r
2379 -1, -1, -1, -1, -1, -1, -1, -1,\r
2380 -1, -1, -1, -1, -1, -1, -1, -1,\r
2381 -1, -1, -1, -1, -1, -1, -1, -1,\r
2382 -1, -1, -1, -1, -1, -1, -1, -1,\r
2383 -1, -1, -1, -1, -1, -1, -1, -1,\r
2384 -1, -1, -1, -1, -1, -1, -1}\r
2385 },\r
2386 /* Event to channel map for region 3 */\r
2387 {\r
2388 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2389 -1, -1, -1, -1, -1, -1, -1, -1,\r
2390 -1, -1, -1, -1, -1, -1, -1, -1,\r
2391 -1, -1, -1, -1, -1, -1, -1, -1,\r
2392 -1, -1, -1, -1, -1, -1, -1, -1,\r
2393 -1, -1, -1, -1, -1, -1, -1, -1,\r
2394 -1, -1, -1, -1, -1, -1, -1, -1,\r
2395 -1, -1, -1, -1, -1, -1, -1}\r
2396 },\r
2397 /* Event to channel map for region 4 */\r
2398 {\r
2399 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2400 -1, -1, -1, -1, -1, -1, -1, -1,\r
2401 -1, -1, -1, -1, -1, -1, -1, -1,\r
2402 -1, -1, -1, -1, -1, -1, -1, -1,\r
2403 -1, -1, -1, -1, -1, -1, -1, -1,\r
2404 -1, -1, -1, -1, -1, -1, -1, -1,\r
2405 -1, -1, -1, -1, -1, -1, -1, -1,\r
2406 -1, -1, -1, -1, -1, -1, -1}\r
2407 },\r
2408 /* Event to channel map for region 5 */\r
2409 {\r
2410 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2411 -1, -1, -1, -1, -1, -1, -1, -1,\r
2412 -1, -1, -1, -1, -1, -1, -1, -1,\r
2413 -1, -1, -1, -1, -1, -1, -1, -1,\r
2414 -1, -1, -1, -1, -1, -1, -1, -1,\r
2415 -1, -1, -1, -1, -1, -1, -1, -1,\r
2416 -1, -1, -1, -1, -1, -1, -1, -1,\r
2417 -1, -1, -1, -1, -1, -1, -1}\r
2418 },\r
2419 /* Event to channel map for region 6 */\r
2420 {\r
2421 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2422 -1, -1, -1, -1, -1, -1, -1, -1,\r
2423 -1, -1, -1, -1, -1, -1, -1, -1,\r
2424 -1, -1, -1, -1, -1, -1, -1, -1,\r
2425 -1, -1, -1, -1, -1, -1, -1, -1,\r
2426 -1, -1, -1, -1, -1, -1, -1, -1,\r
2427 -1, -1, -1, -1, -1, -1, -1, -1,\r
2428 -1, -1, -1, -1, -1, -1, -1}\r
2429 },\r
2430 /* Event to channel map for region 7 */\r
2431 {\r
2432 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2433 -1, -1, -1, -1, -1, -1, -1, -1,\r
2434 -1, -1, -1, -1, -1, -1, -1, -1,\r
2435 -1, -1, -1, -1, -1, -1, -1, -1,\r
2436 -1, -1, -1, -1, -1, -1, -1, -1,\r
2437 -1, -1, -1, -1, -1, -1, -1, -1,\r
2438 -1, -1, -1, -1, -1, -1, -1, -1,\r
2439 -1, -1, -1, -1, -1, -1, -1}\r
2440 },\r
2441 }\r
2442 };\r
2443 \r
2444 /* End of File */\r
2445 \r