Misra C fixes:
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2  * sample_tda2xx_cfg.c\r
3  *\r
4  * SoC specific EDMA3 hardware related information like number of transfer\r
5  * controllers, various interrupt ids etc. It is used while interrupts\r
6  * enabling / disabling. It needs to be ported for different SoCs.\r
7  *\r
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9  *\r
10  *\r
11  *  Redistribution and use in source and binary forms, with or without\r
12  *  modification, are permitted provided that the following conditions\r
13  *  are met:\r
14  *\r
15  *    Redistributions of source code must retain the above copyright\r
16  *    notice, this list of conditions and the following disclaimer.\r
17  *\r
18  *    Redistributions in binary form must reproduce the above copyright\r
19  *    notice, this list of conditions and the following disclaimer in the\r
20  *    documentation and/or other materials provided with the\r
21  *    distribution.\r
22  *\r
23  *    Neither the name of Texas Instruments Incorporated nor the names of\r
24  *    its contributors may be used to endorse or promote products derived\r
25  *    from this software without specific prior written permission.\r
26  *\r
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38  *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
42 #ifdef BUILD_TDA2XX_IPU\r
43 #include <ti/sysbios/family/arm/ducati/Core.h> \r
44 \r
45 #endif\r
46 \r
47 /* Number of EDMA3 controllers present in the system */\r
48 #define NUM_EDMA3_INSTANCES         3U\r
49 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;\r
50 \r
51 /* Number of DSPs present in the system */\r
52 #define NUM_DSPS                    1U\r
53 const uint32_t numDsps = NUM_DSPS;\r
54 \r
55 /* Determine the processor id by reading DNUM register. */\r
56 /* Statically allocate the region numbers with cores. */\r
57 int32_t myCoreNum;\r
58 #define PID0_ADDRESS 0xE00FFFE0U\r
59 #define CORE_ID_C0 0x0U\r
60 #define CORE_ID_C1 0x1U\r
61 \r
62 #ifdef BUILD_TDA2XX_MPU\r
63 void __inline readProcFeatureReg(void);\r
64 void __inline readProcFeatureReg(void)\r
65 {\r
66     asm ("    push    {r0-r2} \n\t"\r
67              "    MRC p15, 0, r0, c0, c0, 5\n\t"\r
68                  "    LDR      r1, =myCoreNum\n\t"\r
69                  "    STR      r0, [r1]\n\t"\r
70                  "    pop    {r0-r2}\n\t");\r
71 }\r
72 #endif\r
73 \r
74 uint16_t determineProcId(void);\r
75 \r
76 int8_t*  getGlobalAddr(int8_t* addr);\r
77 \r
78 uint16_t isGblConfigRequired(uint32_t dspNum);\r
79 \r
80 uint16_t determineProcId(void)\r
81 {\r
82     uint16_t regionNo = (uint16_t)numEdma3Instances;\r
83 #ifdef BUILD_TDA2XX_DSP\r
84     extern __cregister volatile uint32_t DNUM;\r
85 #endif\r
86 \r
87     myCoreNum = (int32_t)numDsps;\r
88 \r
89 #ifdef BUILD_TDA2XX_MPU\r
90     readProcFeatureReg();\r
91 /* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */\r
92         regionNo = 0U;\r
93     if(((uint32_t)myCoreNum & 0x03U) == 1U)\r
94     {\r
95         regionNo = 1U;\r
96     }\r
97 #elif defined(BUILD_TDA2XX_IPU)\r
98     myCoreNum = (*(uint32_t *)(PID0_ADDRESS));\r
99     if(Core_getIpuId() == 1U){\r
100         if(myCoreNum == (int32_t)CORE_ID_C0)\r
101         {\r
102             regionNo = 4U;\r
103         }\r
104         else if (myCoreNum == (int32_t)CORE_ID_C1)\r
105         {\r
106             regionNo = 5U;\r
107         }\r
108         else\r
109         {\r
110             /* Nothing to be done here*/\r
111         }\r
112     }\r
113     if(Core_getIpuId() == 2U){\r
114         if(myCoreNum == (int32_t)CORE_ID_C0)\r
115         {\r
116             regionNo = 6U;\r
117         }\r
118         else if (myCoreNum == (int32_t)CORE_ID_C1)\r
119         {\r
120             regionNo = 7U;\r
121         }\r
122         else\r
123         {\r
124             /* Nothing to be done here*/\r
125         }\r
126     }\r
127 #elif defined(BUILD_TDA2XX_DSP)\r
128 \r
129         myCoreNum = (int32_t)DNUM;\r
130         if(myCoreNum == 0)\r
131     {\r
132                 regionNo = 2U;\r
133     }\r
134         else\r
135     {\r
136                 regionNo = 3U;\r
137     }\r
138 #elif defined(BUILD_TDA2XX_EVE)\r
139     regionNo = 1U;\r
140 #endif\r
141         return regionNo;\r
142 }\r
143 \r
144 int8_t*  getGlobalAddr(int8_t* addr)\r
145 {\r
146      return (addr); /* The address is already a global address */\r
147 }\r
148 uint16_t isGblConfigRequired(uint32_t dspNum)\r
149 {\r
150     (void) dspNum;\r
151         return 1U;\r
152 }\r
153 \r
154 /* Semaphore handles */\r
155 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
156 \r
157 /** Number of PaRAM Sets available                                            */\r
158 #define EDMA3_NUM_PARAMSET                              (512U)\r
159 \r
160 /** Number of TCCS available                                                  */\r
161 #define EDMA3_NUM_TCC                                   (64U)\r
162 \r
163 /** Number of DMA Channels available                                          */\r
164 #define EDMA3_NUM_DMA_CHANNELS                          (64U)\r
165 \r
166 /** Number of QDMA Channels available                                         */\r
167 #define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
168 \r
169 /** Number of Event Queues available                                          */\r
170 #define EDMA3_NUM_EVTQUE                                (4U)\r
171 \r
172 /** Number of Transfer Controllers available                                  */\r
173 #define EDMA3_NUM_TC                                    (2U)\r
174 \r
175 /** Number of Regions                                                         */\r
176 #define EDMA3_NUM_REGIONS                               (8U)\r
177 \r
178 /** Interrupt no. for Transfer Completion */\r
179 #define EDMA3_CC_XFER_COMPLETION_INT_A15                (66U)\r
180 #define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38U)\r
181 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34U)\r
182 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33U)\r
183 #define EDMA3_CC_XFER_COMPLETION_INT_EVE                (8U)\r
184 \r
185 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
186 #define COMPLETION_INT_A15_XBAR_INST_NO                 (29U)\r
187 #define COMPLETION_INT_DSP_XBAR_INST_NO                 (7U)\r
188 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12U)\r
189 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11U)\r
190 \r
191 /** Interrupt no. for CC Error */\r
192 #define EDMA3_CC_ERROR_INT_A15                          (67U)\r
193 #define EDMA3_CC_ERROR_INT_DSP                          (39U)\r
194 #define EDMA3_CC_ERROR_INT_IPU                          (35U)\r
195 #define EDMA3_CC_ERROR_INT_EVE                          (23U)\r
196 \r
197 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
198 #define CC_ERROR_INT_A15_XBAR_INST_NO                   (30U)\r
199 #define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8U)\r
200 #define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13U)\r
201 \r
202 /** Interrupt no. for TCs Error */\r
203 #define EDMA3_TC0_ERROR_INT_A15                         (68U)\r
204 #define EDMA3_TC0_ERROR_INT_DSP                         (40U)\r
205 #define EDMA3_TC0_ERROR_INT_IPU                         (36U)\r
206 #define EDMA3_TC0_ERROR_INT_EVE                         (24U)\r
207 #define EDMA3_TC1_ERROR_INT_A15                         (69U)\r
208 #define EDMA3_TC1_ERROR_INT_DSP                         (41U)\r
209 #define EDMA3_TC1_ERROR_INT_IPU                         (37U)\r
210 #define EDMA3_TC1_ERROR_INT_EVE                         (25U)\r
211 \r
212 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
213 #define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31U)\r
214 #define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9U) \r
215 #define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14U)\r
216 #define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32U)\r
217 #define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10U)\r
218 #define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)\r
219 \r
220 #ifdef BUILD_TDA2XX_MPU\r
221 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A15)\r
222 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_A15)\r
223 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_A15_XBAR_INST_NO)\r
224 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_A15)\r
225 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_A15)\r
226 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
227 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
228 \r
229 #elif defined BUILD_TDA2XX_DSP\r
230 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_DSP)\r
231 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_DSP)\r
232 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_DSP_XBAR_INST_NO)\r
233 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_DSP)\r
234 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_DSP)\r
235 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_DSP_XBAR_INST_NO)\r
236 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_DSP_XBAR_INST_NO)\r
237 \r
238 #elif defined BUILD_TDA2XX_IPU\r
239 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)\r
240 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_IPU)\r
241 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_IPU_XBAR_INST_NO)\r
242 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_IPU)\r
243 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_IPU)\r
244 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_IPU_XBAR_INST_NO)\r
245 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_IPU_XBAR_INST_NO)\r
246 \r
247 #elif defined BUILD_TDA2XX_EVE\r
248 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_EVE)\r
249 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_EVE)\r
250 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_EVE)\r
251 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_EVE)\r
252 /* For accessing EVE internal edma, there is no need to configure Xbar */\r
253 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
254 #define TC0_ERROR_INT_XBAR_INST_NO                      (0U)\r
255 #define TC1_ERROR_INT_XBAR_INST_NO                      (0U)\r
256 \r
257 #else\r
258 #define EDMA3_CC_XFER_COMPLETION_INT                    (0U)\r
259 #define EDMA3_CC_ERROR_INT                              (0U)\r
260 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
261 #define EDMA3_TC0_ERROR_INT                             (0U)\r
262 #define EDMA3_TC1_ERROR_INT                             (0U)\r
263 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
264 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
265 #endif\r
266 \r
267 #define EDMA3_TC2_ERROR_INT                             (0U)\r
268 #define EDMA3_TC3_ERROR_INT                             (0U)\r
269 #define EDMA3_TC4_ERROR_INT                             (0U)\r
270 #define EDMA3_TC5_ERROR_INT                             (0U)\r
271 #define EDMA3_TC6_ERROR_INT                             (0U)\r
272 #define EDMA3_TC7_ERROR_INT                             (0U)\r
273 \r
274 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19U)\r
275 #define DSP2_EDMA3_CC_XFER_COMPLETION_INT               (20U)\r
276 #define DSP1_EDMA3_CC_ERROR_INT                         (27U)\r
277 #define DSP1_EDMA3_TC0_ERROR_INT                        (28U)\r
278 #define DSP1_EDMA3_TC1_ERROR_INT                        (29U)\r
279 \r
280 /** XBAR interrupt source index numbers for EDMA interrupts */\r
281 #define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)\r
282 #define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)\r
283 #define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)\r
284 #define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)\r
285 #define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)\r
286 #define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)\r
287 #define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)\r
288 #define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)\r
289 \r
290 #define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)\r
291 #define XBAR_EDMA_TC0_IRQ_ERR                           (370U)\r
292 #define XBAR_EDMA_TC1_IRQ_ERR                           (371U)\r
293 \r
294 /**\r
295  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
296  * ECM events (SoC specific). These ECM events come\r
297  * under ECM block XXX (handling those specific ECM events). Normally, block\r
298  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
299  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
300  * is mapped to a specific HWI_INT YYY in the tcf file.\r
301  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
302  * to transfer completion interrupt.\r
303  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
304  * to CC error interrupts.\r
305  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
306  * to TC error interrupts.\r
307  */\r
308 /* EDMA 0 */\r
309 \r
310 #define EDMA3_HWI_INT_XFER_COMP                           (7U)\r
311 #define EDMA3_HWI_INT_CC_ERR                              (7U)\r
312 #define EDMA3_HWI_INT_TC0_ERR                             (10U)\r
313 #define EDMA3_HWI_INT_TC1_ERR                             (10U)\r
314 #define EDMA3_HWI_INT_TC2_ERR                             (10U)\r
315 #define EDMA3_HWI_INT_TC3_ERR                             (10U)\r
316 \r
317 /**\r
318  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
319  * various peripherals, which use EDMA for data transfer.\r
320  * All channels need not be mapped, some can be free also.\r
321  * 1: Mapped\r
322  * 0: Not mapped (channel available)\r
323  *\r
324  * This mapping will be used to allocate DMA channels when user passes\r
325  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
326  * copy). The same mapping is used to allocate the TCC when user passes\r
327  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
328  * \r
329  * For Vayu Since the xbar can be used to map event to any EDMA channel,\r
330  * If the application is assigning events to other channel this variable \r
331  * should be modified\r
332  *\r
333  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
334  */\r
335                                                       /* 31     0 */\r
336 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA       (0x3FC0C06EU)  /* TBD */\r
337 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */\r
338 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA        (0x00000000U)  /* TBD */\r
339 \r
340 /**\r
341  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
342  * various peripherals, which use EDMA for data transfer.\r
343  * All channels need not be mapped, some can be free also.\r
344  * 1: Mapped\r
345  * 0: Not mapped (channel available)\r
346  *\r
347  * This mapping will be used to allocate DMA channels when user passes\r
348  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
349  * copy). The same mapping is used to allocate the TCC when user passes\r
350  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
351  *\r
352  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
353  */\r
354 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA       (0xF3FFFFFCU) /* TBD */\r
355 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */\r
356 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA        (0x00000000U) /* TBD */\r
357 \r
358 \r
359 /* Variable which will be used internally for referring number of Event Queues*/\r
360 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
361                                                         EDMA3_NUM_EVTQUE,\r
362                                                         EDMA3_NUM_EVTQUE,\r
363                                                         EDMA3_NUM_EVTQUE\r
364                                                     };\r
365 \r
366 /* Variable which will be used internally for referring number of TCs.        */\r
367 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
368                                                     EDMA3_NUM_TC,\r
369                                                     EDMA3_NUM_TC,\r
370                                                     EDMA3_NUM_TC\r
371                                                 };\r
372 \r
373 /**\r
374  * Variable which will be used internally for referring transfer completion\r
375  * interrupt.\r
376  */\r
377 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
378 {\r
379     /* EDMA3 INSTANCE# 0 */\r
380     {\r
381         EDMA3_CC_XFER_COMPLETION_INT_A15,\r
382         EDMA3_CC_XFER_COMPLETION_INT_A15,\r
383                 EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
384         EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
385                 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
386         EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
387         EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
388         EDMA3_CC_XFER_COMPLETION_INT_IPU_C1\r
389     },\r
390     /* EDMA3 INSTANCE# 1 */\r
391     {\r
392         0U,\r
393         0U,\r
394         DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
395         DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
396         0U,\r
397         0U,\r
398         0U,\r
399         0U\r
400     },\r
401     /* EDMA3 INSTANCE# 2 */\r
402     {\r
403         0U,\r
404         /* Region 1 (Associated to EVE core)*/\r
405         EDMA3_CC_XFER_COMPLETION_INT_EVE,\r
406         0U,\r
407         0U,\r
408         0U,\r
409         0U,\r
410         0U,\r
411         0U,\r
412     }\r
413 };\r
414 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
415 uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
416 {\r
417     /* EDMA3 INSTANCE# 0 */\r
418     {\r
419         COMPLETION_INT_A15_XBAR_INST_NO,\r
420         COMPLETION_INT_A15_XBAR_INST_NO,\r
421                 COMPLETION_INT_DSP_XBAR_INST_NO,\r
422         COMPLETION_INT_DSP_XBAR_INST_NO,\r
423                 COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
424         COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
425         COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
426         COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
427     },\r
428     /* EDMA3 INSTANCE# 1 */\r
429     {\r
430         0U,\r
431         0U,\r
432         0U,\r
433         0U,\r
434         0U,\r
435         0U,\r
436         0U,\r
437         0U\r
438     },\r
439     /* EDMA3 INSTANCE# 2 */\r
440     {\r
441      /* \r
442       * For accessing EVE internal edma,\r
443       * there is no need to configure Xbar.\r
444       * So getting to zero.\r
445       */\r
446         0U,\r
447         0U,\r
448         0U,\r
449         0U,\r
450         0U,\r
451         0U,\r
452         0U,\r
453         0U\r
454     }\r
455 };\r
456 \r
457 /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
458 uint32_t ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
459 {\r
460     /* EDMA3 INSTANCE# 0 */\r
461         {\r
462                 XBAR_EDMA_TPCC_IRQ_REGION0,\r
463         XBAR_EDMA_TPCC_IRQ_REGION1,\r
464         XBAR_EDMA_TPCC_IRQ_REGION2,\r
465         XBAR_EDMA_TPCC_IRQ_REGION3,\r
466                 XBAR_EDMA_TPCC_IRQ_REGION4,\r
467         XBAR_EDMA_TPCC_IRQ_REGION5,\r
468         XBAR_EDMA_TPCC_IRQ_REGION6,\r
469         XBAR_EDMA_TPCC_IRQ_REGION7\r
470         },\r
471     /* EDMA3 INSTANCE# 1 */\r
472     {\r
473                 XBAR_EDMA_TPCC_IRQ_REGION0,\r
474         XBAR_EDMA_TPCC_IRQ_REGION1,\r
475         XBAR_EDMA_TPCC_IRQ_REGION2,\r
476         XBAR_EDMA_TPCC_IRQ_REGION3,\r
477                 XBAR_EDMA_TPCC_IRQ_REGION4,\r
478         XBAR_EDMA_TPCC_IRQ_REGION5,\r
479         XBAR_EDMA_TPCC_IRQ_REGION6,\r
480         XBAR_EDMA_TPCC_IRQ_REGION7\r
481         },\r
482     /* EDMA3 INSTANCE# 2 */\r
483     {\r
484      /* \r
485       * For accessing EVE internal edma,\r
486       * there is no need to configure Xbar.\r
487       * So getting to zero.\r
488       */\r
489                 0U,\r
490         0U,\r
491         0U,\r
492         0U,\r
493                 0U,\r
494         0U,\r
495         0U,\r
496         0U\r
497         }\r
498 };\r
499 \r
500 /**\r
501  * Variable which will be used internally for referring channel controller's\r
502  * error interrupt.\r
503  */\r
504 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = \r
505 {\r
506     EDMA3_CC_ERROR_INT,\r
507     DSP1_EDMA3_CC_ERROR_INT,\r
508     EDMA3_CC_ERROR_INT\r
509 };\r
510 uint32_t ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =\r
511 {\r
512     CC_ERROR_INT_XBAR_INST_NO,\r
513     CC_ERROR_INT_XBAR_INST_NO,\r
514     CC_ERROR_INT_XBAR_INST_NO\r
515 };\r
516 uint32_t ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
517 {\r
518         XBAR_EDMA_TPCC_IRQ_ERR,\r
519     XBAR_EDMA_TPCC_IRQ_ERR,\r
520     XBAR_EDMA_TPCC_IRQ_ERR\r
521 };\r
522 \r
523 /**\r
524  * Variable which will be used internally for referring transfer controllers'\r
525  * error interrupts.\r
526  */\r
527 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
528 {\r
529     /* EDMA3 INSTANCE# 0 */\r
530     {\r
531         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
532         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
533         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
534         EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
535     },\r
536     /* EDMA3 INSTANCE# 1 */\r
537     {\r
538         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
539         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
540         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
541         DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
542     },\r
543     /* EDMA3 INSTANCE# 2 */\r
544     {\r
545         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
546         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
547         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
548         EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
549     }\r
550 };\r
551 uint32_t tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
552 {\r
553     /* EDMA3 INSTANCE# 0 */\r
554     {\r
555        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
556        0U, 0U,\r
557        0U, 0U,\r
558        0U, 0U,\r
559     },\r
560     /* EDMA3 INSTANCE# 1 */\r
561     {\r
562        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
563        0U, 0U,\r
564        0U, 0U,\r
565        0U, 0U,\r
566     },\r
567     /* EDMA3 INSTANCE# 2 */\r
568     {\r
569        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
570        0U, 0U,\r
571        0U, 0U,\r
572        0U, 0U,\r
573     }\r
574 };\r
575 \r
576 uint32_t tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
577 {\r
578     /* EDMA3 INSTANCE# 0 */\r
579     {\r
580        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
581        0U, 0U,\r
582        0U, 0U, 0U, 0U,\r
583     },\r
584     /* EDMA3 INSTANCE# 1 */\r
585     {\r
586        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
587        0U, 0U,\r
588        0U, 0U, 0U, 0U,\r
589     },\r
590     /* EDMA3 INSTANCE# 2 */\r
591     {\r
592        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
593        0U, 0U,\r
594        0U, 0U, 0U, 0U,\r
595     }\r
596 };\r
597 \r
598 \r
599 /**\r
600  * Variables which will be used internally for referring the hardware interrupt\r
601  * for various EDMA3 interrupts.\r
602  */\r
603 uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
604 {\r
605     EDMA3_HWI_INT_XFER_COMP,\r
606     EDMA3_HWI_INT_XFER_COMP,\r
607     EDMA3_CC_XFER_COMPLETION_INT\r
608 };\r
609 \r
610 uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
611 {\r
612     EDMA3_HWI_INT_CC_ERR,\r
613     EDMA3_HWI_INT_CC_ERR,\r
614     EDMA3_CC_ERROR_INT\r
615 };\r
616 \r
617 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
618 {\r
619     /* EDMA3 INSTANCE# 0 */\r
620     {\r
621          EDMA3_HWI_INT_TC0_ERR ,\r
622          EDMA3_HWI_INT_TC1_ERR ,\r
623          EDMA3_HWI_INT_TC2_ERR ,\r
624          EDMA3_HWI_INT_TC3_ERR ,\r
625          0U ,\r
626          0U ,\r
627          0U ,\r
628          0U \r
629     },\r
630     /* EDMA3 INSTANCE# 1 */\r
631     {\r
632          EDMA3_HWI_INT_TC0_ERR ,\r
633          EDMA3_HWI_INT_TC1_ERR ,\r
634          EDMA3_HWI_INT_TC2_ERR ,\r
635          EDMA3_HWI_INT_TC3_ERR ,\r
636          0U ,\r
637          0U ,\r
638          0U ,\r
639          0U \r
640     },\r
641     /* EDMA3 INSTANCE# 2 */\r
642     {\r
643          EDMA3_TC0_ERROR_INT ,\r
644          EDMA3_TC1_ERROR_INT ,\r
645          EDMA3_TC2_ERROR_INT ,\r
646          EDMA3_TC3_ERROR_INT ,\r
647          0U ,\r
648          0U ,\r
649          0U ,\r
650          0U \r
651     }\r
652 };\r
653 \r
654 /**\r
655  * \brief Base address as seen from the different cores may be different\r
656  * And is defined based on the core\r
657  */\r
658 #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
659 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
660 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
661 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
662 #elif (defined BUILD_TDA2XX_IPU)\r
663 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))\r
664 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))\r
665 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))\r
666 #elif (defined BUILD_TDA2XX_EVE)\r
667 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x400A0000))\r
668 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x40086000))\r
669 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x40087000))\r
670 #else\r
671 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))\r
672 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))\r
673 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))\r
674 #endif\r
675 \r
676 #define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))\r
677 #define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))\r
678 #define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))\r
679 \r
680 /* Driver Object Initialization Configuration */\r
681 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
682 {\r
683     {\r
684         /* EDMA3 INSTANCE# 0 */\r
685         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
686         EDMA3_NUM_DMA_CHANNELS,\r
687         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
688         EDMA3_NUM_QDMA_CHANNELS,\r
689         /** Total number of TCCs supported by the EDMA3 Controller            */\r
690         EDMA3_NUM_TCC,\r
691         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
692         EDMA3_NUM_PARAMSET,\r
693         /** Total number of Event Queues in the EDMA3 Controller              */\r
694         EDMA3_NUM_EVTQUE,\r
695         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
696         EDMA3_NUM_TC,\r
697         /** Number of Regions on this EDMA3 controller                        */\r
698         EDMA3_NUM_REGIONS,\r
699 \r
700         /**\r
701          * \brief Channel mapping existence\r
702          * A value of 0 (No channel mapping) implies that there is fixed association\r
703          * for a channel number to a parameter entry number or, in other words,\r
704          * PaRAM entry n corresponds to channel n.\r
705          */\r
706         1U,\r
707 \r
708         /** Existence of memory protection feature */\r
709         0U,\r
710 \r
711         /** Global Register Region of CC Registers */\r
712         EDMA3_CC_BASE_ADDR,\r
713         /** Transfer Controller (TC) Registers */\r
714         {\r
715                 EDMA3_TC0_BASE_ADDR,\r
716                 EDMA3_TC1_BASE_ADDR,\r
717                 (void *)NULL,\r
718                 (void *)NULL,\r
719             (void *)NULL,\r
720             (void *)NULL,\r
721             (void *)NULL,\r
722             (void *)NULL\r
723         },\r
724         /** Interrupt no. for Transfer Completion */\r
725         EDMA3_CC_XFER_COMPLETION_INT,\r
726         /** Interrupt no. for CC Error */\r
727         EDMA3_CC_ERROR_INT,\r
728         /** Interrupt no. for TCs Error */\r
729         {\r
730             EDMA3_TC0_ERROR_INT,\r
731             EDMA3_TC1_ERROR_INT,\r
732             EDMA3_TC2_ERROR_INT,\r
733             EDMA3_TC3_ERROR_INT,\r
734             EDMA3_TC4_ERROR_INT,\r
735             EDMA3_TC5_ERROR_INT,\r
736             EDMA3_TC6_ERROR_INT,\r
737             EDMA3_TC7_ERROR_INT\r
738         },\r
739 \r
740         /**\r
741          * \brief EDMA3 TC priority setting\r
742          *\r
743          * User can program the priority of the Event Queues\r
744          * at a system-wide level.  This means that the user can set the\r
745          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
746          * relative to IO initiated by the other bus masters on the\r
747          * device (ARM, DSP, USB, etc)\r
748          */\r
749         {\r
750             0U,\r
751             1U,\r
752             0U,\r
753             0U,\r
754             0U,\r
755             0U,\r
756             0U,\r
757             0U\r
758         },\r
759         /**\r
760          * \brief To Configure the Threshold level of number of events\r
761          * that can be queued up in the Event queues. EDMA3CC error register\r
762          * (CCERR) will indicate whether or not at any instant of time the\r
763          * number of events queued up in any of the event queues exceeds\r
764          * or equals the threshold/watermark value that is set\r
765          * in the queue watermark threshold register (QWMTHRA).\r
766          */\r
767         {\r
768             16U,\r
769             16U,\r
770             0U,\r
771             0U,\r
772             0U,\r
773             0U,\r
774             0U,\r
775             0U\r
776         },\r
777 \r
778         /**\r
779          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
780          * An optimally-sized command is defined by the transfer controller\r
781          * default burst size (DBS). Different TCs can have different\r
782          * DBS values. It is defined in Bytes.\r
783          */\r
784             {\r
785             16U,\r
786             16U,\r
787             0U,\r
788             0U,\r
789             0U,\r
790             0U,\r
791             0U,\r
792             0U\r
793             },\r
794 \r
795         /**\r
796          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
797          * if it exists, otherwise of no use.\r
798          */\r
799             {\r
800                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
801                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
802                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
803                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
804                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
805                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
806                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
807                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
808                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
809                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
810                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
811                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
812                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
813                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
814                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
815                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
816                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
817                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
818                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
819                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
820                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
821                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
822                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
823                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
824                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
825                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
826                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
827                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
828                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
829                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
830                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
831                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
832                         },\r
833 \r
834          /**\r
835           * \brief Mapping from each DMA channel to a TCC. This specific\r
836           * TCC code will be returned when the transfer is completed\r
837           * on the mapped channel.\r
838           */\r
839             {\r
840                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
841                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
842                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
843                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
844                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
845                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
846                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
847                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
848                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
849                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
850                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
851                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
852                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
853                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
854                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
855                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
856             },\r
857 \r
858         /**\r
859          * \brief Mapping of DMA channels to Hardware Events from\r
860          * various peripherals, which use EDMA for data transfer.\r
861          * All channels need not be mapped, some can be free also.\r
862          */\r
863             {\r
864             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,\r
865             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA\r
866             }\r
867         },\r
868     {\r
869         /* EDMA3 INSTANCE# 1 */\r
870         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
871         EDMA3_NUM_DMA_CHANNELS,\r
872         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
873         EDMA3_NUM_QDMA_CHANNELS,\r
874         /** Total number of TCCs supported by the EDMA3 Controller            */\r
875         EDMA3_NUM_TCC,\r
876         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
877         EDMA3_NUM_PARAMSET,\r
878         /** Total number of Event Queues in the EDMA3 Controller              */\r
879         EDMA3_NUM_EVTQUE,\r
880         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
881         EDMA3_NUM_TC,\r
882         /** Number of Regions on this EDMA3 controller                        */\r
883         EDMA3_NUM_REGIONS,\r
884 \r
885         /**\r
886          * \brief Channel mapping existence\r
887          * A value of 0 (No channel mapping) implies that there is fixed association\r
888          * for a channel number to a parameter entry number or, in other words,\r
889          * PaRAM entry n corresponds to channel n.\r
890          */\r
891         1U,\r
892 \r
893         /** Existence of memory protection feature */\r
894         0U,\r
895 \r
896         /** Global Register Region of CC Registers */\r
897         DSP1_EDMA3_CC_BASE_ADDR,\r
898         /** Transfer Controller (TC) Registers */\r
899         {\r
900                 DSP1_EDMA3_TC0_BASE_ADDR,\r
901                 DSP1_EDMA3_TC1_BASE_ADDR,\r
902                 (void *)NULL,\r
903                 (void *)NULL,\r
904             (void *)NULL,\r
905             (void *)NULL,\r
906             (void *)NULL,\r
907             (void *)NULL\r
908         },\r
909         /** Interrupt no. for Transfer Completion */\r
910         DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
911         /** Interrupt no. for CC Error */\r
912         DSP1_EDMA3_CC_ERROR_INT,\r
913         /** Interrupt no. for TCs Error */\r
914         {\r
915             DSP1_EDMA3_TC0_ERROR_INT,\r
916             DSP1_EDMA3_TC1_ERROR_INT,\r
917             EDMA3_TC2_ERROR_INT,\r
918             EDMA3_TC3_ERROR_INT,\r
919             EDMA3_TC4_ERROR_INT,\r
920             EDMA3_TC5_ERROR_INT,\r
921             EDMA3_TC6_ERROR_INT,\r
922             EDMA3_TC7_ERROR_INT\r
923         },\r
924 \r
925         /**\r
926          * \brief EDMA3 TC priority setting\r
927          *\r
928          * User can program the priority of the Event Queues\r
929          * at a system-wide level.  This means that the user can set the\r
930          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
931          * relative to IO initiated by the other bus masters on the\r
932          * device (ARM, DSP, USB, etc)\r
933          */\r
934         {\r
935             0U,\r
936             1U,\r
937             0U,\r
938             0U,\r
939             0U,\r
940             0U,\r
941             0U,\r
942             0U\r
943         },\r
944         /**\r
945          * \brief To Configure the Threshold level of number of events\r
946          * that can be queued up in the Event queues. EDMA3CC error register\r
947          * (CCERR) will indicate whether or not at any instant of time the\r
948          * number of events queued up in any of the event queues exceeds\r
949          * or equals the threshold/watermark value that is set\r
950          * in the queue watermark threshold register (QWMTHRA).\r
951          */\r
952         {\r
953             16U,\r
954             16U,\r
955             0U,\r
956             0U,\r
957             0U,\r
958             0U,\r
959             0U,\r
960             0U\r
961         },\r
962 \r
963         /**\r
964          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
965          * An optimally-sized command is defined by the transfer controller\r
966          * default burst size (DBS). Different TCs can have different\r
967          * DBS values. It is defined in Bytes.\r
968          */\r
969             {\r
970             16U,\r
971             16U,\r
972             0U,\r
973             0U,\r
974             0U,\r
975             0U,\r
976             0U,\r
977             0U\r
978             },\r
979 \r
980         /**\r
981          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
982          * if it exists, otherwise of no use.\r
983          */\r
984             {\r
985                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
986                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
987                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
988                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
989                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
990                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
991                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
992                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
993                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
994                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
995                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
996                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
997                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
998                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
999                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1000                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1001                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1002                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1003                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1004                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1005                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1006                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1007                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1008                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1009                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1010                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1011                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1012                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1013                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1014                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1015                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1016                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
1017             },\r
1018 \r
1019          /**\r
1020           * \brief Mapping from each DMA channel to a TCC. This specific\r
1021           * TCC code will be returned when the transfer is completed\r
1022           * on the mapped channel.\r
1023           */\r
1024             {\r
1025                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1026                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1027                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1028                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1029                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1030                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1031                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1032                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1033                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1034                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1035                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1036                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1037                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1038                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1039                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1040                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1041             },\r
1042 \r
1043         /**\r
1044          * \brief Mapping of DMA channels to Hardware Events from\r
1045          * various peripherals, which use EDMA for data transfer.\r
1046          * All channels need not be mapped, some can be free also.\r
1047          */\r
1048             {\r
1049             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
1050             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
1051             }\r
1052     },\r
1053     {\r
1054         /* EDMA3 INSTANCE# 2 */\r
1055         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
1056         EDMA3_NUM_DMA_CHANNELS,\r
1057         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
1058         EDMA3_NUM_QDMA_CHANNELS,\r
1059         /** Total number of TCCs supported by the EDMA3 Controller            */\r
1060         EDMA3_NUM_TCC,\r
1061         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
1062         EDMA3_NUM_PARAMSET,\r
1063         /** Total number of Event Queues in the EDMA3 Controller              */\r
1064         EDMA3_NUM_EVTQUE,\r
1065         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
1066         EDMA3_NUM_TC,\r
1067         /** Number of Regions on this EDMA3 controller                        */\r
1068         EDMA3_NUM_REGIONS,\r
1069 \r
1070         /**\r
1071          * \brief Channel mapping existence\r
1072          * A value of 0 (No channel mapping) implies that there is fixed association\r
1073          * for a channel number to a parameter entry number or, in other words,\r
1074          * PaRAM entry n corresponds to channel n.\r
1075          */\r
1076         1U,\r
1077 \r
1078         /** Existence of memory protection feature */\r
1079         0U,\r
1080 \r
1081         /** Global Register Region of CC Registers */\r
1082         EDMA3_CC_BASE_ADDR,\r
1083         /** Transfer Controller (TC) Registers */\r
1084         {\r
1085                 EDMA3_TC0_BASE_ADDR,\r
1086                 EDMA3_TC1_BASE_ADDR,\r
1087                 (void *)NULL,\r
1088                 (void *)NULL,\r
1089             (void *)NULL,\r
1090             (void *)NULL,\r
1091             (void *)NULL,\r
1092             (void *)NULL\r
1093         },\r
1094         /** Interrupt no. for Transfer Completion */\r
1095         EDMA3_CC_XFER_COMPLETION_INT,\r
1096         /** Interrupt no. for CC Error */\r
1097         EDMA3_CC_ERROR_INT,\r
1098         /** Interrupt no. for TCs Error */\r
1099         {\r
1100             EDMA3_TC0_ERROR_INT,\r
1101             EDMA3_TC1_ERROR_INT,\r
1102             EDMA3_TC2_ERROR_INT,\r
1103             EDMA3_TC3_ERROR_INT,\r
1104             EDMA3_TC4_ERROR_INT,\r
1105             EDMA3_TC5_ERROR_INT,\r
1106             EDMA3_TC6_ERROR_INT,\r
1107             EDMA3_TC7_ERROR_INT\r
1108         },\r
1109 \r
1110         /**\r
1111          * \brief EDMA3 TC priority setting\r
1112          *\r
1113          * User can program the priority of the Event Queues\r
1114          * at a system-wide level.  This means that the user can set the\r
1115          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
1116          * relative to IO initiated by the other bus masters on the\r
1117          * device (ARM, DSP, USB, etc)\r
1118          */\r
1119         {\r
1120             0U,\r
1121             1U,\r
1122             0U,\r
1123             0U,\r
1124             0U,\r
1125             0U,\r
1126             0U,\r
1127             0U\r
1128         },\r
1129         /**\r
1130          * \brief To Configure the Threshold level of number of events\r
1131          * that can be queued up in the Event queues. EDMA3CC error register\r
1132          * (CCERR) will indicate whether or not at any instant of time the\r
1133          * number of events queued up in any of the event queues exceeds\r
1134          * or equals the threshold/watermark value that is set\r
1135          * in the queue watermark threshold register (QWMTHRA).\r
1136          */\r
1137         {\r
1138             16U,\r
1139             16U,\r
1140             0U,\r
1141             0U,\r
1142             0U,\r
1143             0U,\r
1144             0U,\r
1145             0U\r
1146         },\r
1147 \r
1148         /**\r
1149          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
1150          * An optimally-sized command is defined by the transfer controller\r
1151          * default burst size (DBS). Different TCs can have different\r
1152          * DBS values. It is defined in Bytes.\r
1153          */\r
1154             {\r
1155             16U,\r
1156             16U,\r
1157             0U,\r
1158             0U,\r
1159             0U,\r
1160             0U,\r
1161             0U,\r
1162             0U\r
1163             },\r
1164 \r
1165         /**\r
1166          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
1167          * if it exists, otherwise of no use.\r
1168          */\r
1169             {\r
1170                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1171                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1172                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1173                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1174                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1175                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1176                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1177                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1178                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1179                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1180                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1181                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1182                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1183                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1184                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1185                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1186                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1187                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1188                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1189                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1190                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1191                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1192                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1193                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1194                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1195                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1196                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1197                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1198                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1199                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1200                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1201                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
1202             },\r
1203 \r
1204          /**\r
1205           * \brief Mapping from each DMA channel to a TCC. This specific\r
1206           * TCC code will be returned when the transfer is completed\r
1207           * on the mapped channel.\r
1208           */\r
1209             {\r
1210                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1211                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1212                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1213                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1214                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1215                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1216                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1217                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1218                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1219                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1220                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1221                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1222                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1223                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1224                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1225                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1226             },\r
1227 \r
1228         /**\r
1229          * \brief Mapping of DMA channels to Hardware Events from\r
1230          * various peripherals, which use EDMA for data transfer.\r
1231          * All channels need not be mapped, some can be free also.\r
1232          */\r
1233             {\r
1234             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,\r
1235             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA\r
1236             }\r
1237     },\r
1238 \r
1239 };\r
1240 \r
1241 /**\r
1242  * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
1243  * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
1244  * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
1245  * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
1246  *\r
1247  * Only Resources owned by a perticular core are allocated by Driver\r
1248  * Reserved resources are not allocated if requested for any available resource\r
1249  */\r
1250  \r
1251 /* Driver Instance Initialization Configuration */\r
1252 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
1253     {\r
1254                 /* EDMA3 INSTANCE# 0 */\r
1255                 {\r
1256                         /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
1257                         {\r
1258                                 /* ownPaRAMSets */\r
1259                                 /* 31     0     63    32     95    64     127   96 */\r
1260                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1261                                 /* 159  128     191  160     223  192     255  224 */\r
1262                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1263                                 /* 287  256     319  288     351  320     383  352 */\r
1264                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1265                                 /* 415  384     447  416     479  448     511  480 */\r
1266                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1267 \r
1268                                 /* ownDmaChannels */\r
1269                                 /* 31     0     63    32 */\r
1270                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1271 \r
1272                                 /* ownQdmaChannels */\r
1273                                 /* 31     0 */\r
1274                                 {0x000000FFU},\r
1275 \r
1276                                 /* ownTccs */\r
1277                                 /* 31     0     63    32 */\r
1278                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1279 \r
1280                                 /* resvdPaRAMSets */\r
1281                                 /* 31     0     63    32     95    64     127   96 */\r
1282                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1283                                 /* 159  128     191  160     223  192     255  224 */\r
1284                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1285                                 /* 287  256     319  288     351  320     383  352 */\r
1286                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1287                                 /* 415  384     447  416     479  448     511  480 */\r
1288                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1289 \r
1290                                 /* resvdDmaChannels */\r
1291                                 /* 31     0     63    32 */\r
1292                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1293 \r
1294                                 /* resvdQdmaChannels */\r
1295                                 /* 31     0 */\r
1296                                 {0x00U},\r
1297 \r
1298                                 /* resvdTccs */\r
1299                                 /* 31     0     63    32 */\r
1300                                 {0x00U, 0x00U},\r
1301                         },\r
1302 \r
1303                         /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
1304                         {\r
1305                                 /* ownPaRAMSets */\r
1306                                 /* 31     0     63    32     95    64     127   96 */\r
1307                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1308                                 /* 159  128     191  160     223  192     255  224 */\r
1309                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1310                                 /* 287  256     319  288     351  320     383  352 */\r
1311                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1312                                 /* 415  384     447  416     479  448     511  480 */\r
1313                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1314 /* \r
1315  * This instance 0 and region 1 is only accessible to MPU core 1.\r
1316  * So other cores should not be access.\r
1317  */\r
1318 #ifdef BUILD_TDA2XX_MPU\r
1319                                 /* ownDmaChannels */\r
1320                                 /* 31     0     63    32 */\r
1321                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1322 #else\r
1323                                 /* ownDmaChannels */\r
1324                                 /* 31     0     63    32 */\r
1325                                 {0x00000000U, 0x00000000U},\r
1326 #endif\r
1327                                 /* ownQdmaChannels */\r
1328                                 /* 31     0 */\r
1329                                 {0x000000FFU},\r
1330 \r
1331                                 /* ownTccs */\r
1332                                 /* 31     0     63    32 */\r
1333                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1334 \r
1335                                 /* resvdPaRAMSets */\r
1336                                 /* 31     0     63    32     95    64     127   96 */\r
1337                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1338                                 /* 159  128     191  160     223  192     255  224 */\r
1339                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1340                                 /* 287  256     319  288     351  320     383  352 */\r
1341                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1342                                 /* 415  384     447  416     479  448     511  480 */\r
1343                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1344 \r
1345                                 /* resvdDmaChannels */\r
1346                                 /* 31     0     63    32 */\r
1347                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1348 \r
1349                                 /* resvdQdmaChannels */\r
1350                                 /* 31     0 */\r
1351                                 {0x00U},\r
1352 \r
1353                                 /* resvdTccs */\r
1354                                 /* 31     0     63    32 */\r
1355                                 {0x00U, 0x00U},\r
1356                         },\r
1357 \r
1358                 /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
1359                         {\r
1360                                 /* ownPaRAMSets */\r
1361                                 /* 31     0     63    32     95    64     127   96 */\r
1362                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1363                                 /* 159  128     191  160     223  192     255  224 */\r
1364                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1365                                 /* 287  256     319  288     351  320     383  352 */\r
1366                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1367                                 /* 415  384     447  416     479  448     511  480 */\r
1368                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1369 \r
1370                                 /* ownDmaChannels */\r
1371                                 /* 31     0     63    32 */\r
1372                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1373 \r
1374                                 /* ownQdmaChannels */\r
1375                                 /* 31     0 */\r
1376                                 {0x000000FFU},\r
1377 \r
1378                                 /* ownTccs */\r
1379                                 /* 31     0     63    32 */\r
1380                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1381 \r
1382                                 /* resvdPaRAMSets */\r
1383                                 /* 31     0     63    32     95    64     127   96 */\r
1384                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1385                                 /* 159  128     191  160     223  192     255  224 */\r
1386                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1387                                 /* 287  256     319  288     351  320     383  352 */\r
1388                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1389                                 /* 415  384     447  416     479  448     511  480 */\r
1390                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1391 \r
1392                                 /* resvdDmaChannels */\r
1393                                 /* 31     0     63    32 */\r
1394                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1395 \r
1396                                 /* resvdQdmaChannels */\r
1397                                 /* 31     0 */\r
1398                                 {0x00U},\r
1399 \r
1400                                 /* resvdTccs */\r
1401                                 /* 31     0     63    32 */\r
1402                                 {0x00U, 0x00U},\r
1403                         },\r
1404 \r
1405                 /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
1406                         {\r
1407                                 /* ownPaRAMSets */\r
1408                                 /* 31     0     63    32     95    64     127   96 */\r
1409                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1410                                 /* 159  128     191  160     223  192     255  224 */\r
1411                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1412                                 /* 287  256     319  288     351  320     383  352 */\r
1413                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1414                                 /* 415  384     447  416     479  448     511  480 */\r
1415                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1416 \r
1417                                 /* ownDmaChannels */\r
1418                                 /* 31     0     63    32 */\r
1419                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1420 \r
1421                                 /* ownQdmaChannels */\r
1422                                 /* 31     0 */\r
1423                                 {0x000000FFU},\r
1424 \r
1425                                 /* ownTccs */\r
1426                                 /* 31     0     63    32 */\r
1427                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1428 \r
1429                                 /* resvdPaRAMSets */\r
1430                                 /* 31     0     63    32     95    64     127   96 */\r
1431                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1432                                 /* 159  128     191  160     223  192     255  224 */\r
1433                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1434                                 /* 287  256     319  288     351  320     383  352 */\r
1435                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1436                                 /* 415  384     447  416     479  448     511  480 */\r
1437                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1438 \r
1439                                 /* resvdDmaChannels */\r
1440                                 /* 31     0     63    32 */\r
1441                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1442 \r
1443                                 /* resvdQdmaChannels */\r
1444                                 /* 31     0 */\r
1445                                 {0x00U},\r
1446 \r
1447                                 /* resvdTccs */\r
1448                                 /* 31     0     63    32 */\r
1449                                 {0x00U, 0x00U},\r
1450                         },\r
1451 \r
1452                 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
1453                         {\r
1454                                 /* ownPaRAMSets */\r
1455                                 /* 31     0     63    32     95    64     127   96 */\r
1456                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1457                                 /* 159  128     191  160     223  192     255  224 */\r
1458                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1459                                 /* 287  256     319  288     351  320     383  352 */\r
1460                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1461                                 /* 415  384     447  416     479  448     511  480 */\r
1462                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1463 \r
1464                                 /* ownDmaChannels */\r
1465                                 /* 31     0     63    32 */\r
1466                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1467 \r
1468                                 /* ownQdmaChannels */\r
1469                                 /* 31     0 */\r
1470                                 {0x000000FFU},\r
1471 \r
1472                                 /* ownTccs */\r
1473                                 /* 31     0     63    32 */\r
1474                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1475 \r
1476                                 /* resvdPaRAMSets */\r
1477                                 /* 31     0     63    32     95    64     127   96 */\r
1478                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1479                                 /* 159  128     191  160     223  192     255  224 */\r
1480                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1481                                 /* 287  256     319  288     351  320     383  352 */\r
1482                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1483                                 /* 415  384     447  416     479  448     511  480 */\r
1484                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1485 \r
1486                                 /* resvdDmaChannels */\r
1487                                 /* 31     0     63    32 */\r
1488                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1489 \r
1490                                 /* resvdQdmaChannels */\r
1491                                 /* 31     0 */\r
1492                                 {0x00U},\r
1493 \r
1494                                 /* resvdTccs */\r
1495                                 /* 31     0     63    32 */\r
1496                                 {0x00U, 0x00U},\r
1497                         },\r
1498 \r
1499                 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
1500                         {\r
1501                                 /* ownPaRAMSets */\r
1502                                 /* 31     0     63    32     95    64     127   96 */\r
1503                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1504                                 /* 159  128     191  160     223  192     255  224 */\r
1505                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1506                                 /* 287  256     319  288     351  320     383  352 */\r
1507                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1508                                 /* 415  384     447  416     479  448     511  480 */\r
1509                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1510 \r
1511                                 /* ownDmaChannels */\r
1512                                 /* 31     0     63    32 */\r
1513                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1514 \r
1515                                 /* ownQdmaChannels */\r
1516                                 /* 31     0 */\r
1517                                 {0x000000FFU},\r
1518 \r
1519                                 /* ownTccs */\r
1520                                 /* 31     0     63    32 */\r
1521                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1522 \r
1523                                 /* resvdPaRAMSets */\r
1524                                 /* 31     0     63    32     95    64     127   96 */\r
1525                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1526                                 /* 159  128     191  160     223  192     255  224 */\r
1527                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1528                                 /* 287  256     319  288     351  320     383  352 */\r
1529                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1530                                 /* 415  384     447  416     479  448     511  480 */\r
1531                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1532 \r
1533                                 /* resvdDmaChannels */\r
1534                                 /* 31     0     63    32 */\r
1535                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1536 \r
1537                                 /* resvdQdmaChannels */\r
1538                                 /* 31     0 */\r
1539                                 {0x00U},\r
1540 \r
1541                                 /* resvdTccs */\r
1542                                 /* 31     0     63    32 */\r
1543                                 {0x00U, 0x00U},\r
1544                         },\r
1545 \r
1546                 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
1547                         {\r
1548                                 /* ownPaRAMSets */\r
1549                                 /* 31     0     63    32     95    64     127   96 */\r
1550                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1551                                 /* 159  128     191  160     223  192     255  224 */\r
1552                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1553                                 /* 287  256     319  288     351  320     383  352 */\r
1554                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1555                                 /* 415  384     447  416     479  448     511  480 */\r
1556                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1557 \r
1558                                 /* ownDmaChannels */\r
1559                                 /* 31     0     63    32 */\r
1560                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1561 \r
1562                                 /* ownQdmaChannels */\r
1563                                 /* 31     0 */\r
1564                                 {0x000000FFU},\r
1565 \r
1566                                 /* ownTccs */\r
1567                                 /* 31     0     63    32 */\r
1568                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1569 \r
1570                                 /* resvdPaRAMSets */\r
1571                                 /* 31     0     63    32     95    64     127   96 */\r
1572                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1573                                 /* 159  128     191  160     223  192     255  224 */\r
1574                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1575                                 /* 287  256     319  288     351  320     383  352 */\r
1576                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1577                                 /* 415  384     447  416     479  448     511  480 */\r
1578                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1579 \r
1580                                 /* resvdDmaChannels */\r
1581                                 /* 31     0     63    32 */\r
1582                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1583 \r
1584                                 /* resvdQdmaChannels */\r
1585                                 /* 31     0 */\r
1586                                 {0x00U},\r
1587 \r
1588                                 /* resvdTccs */\r
1589                                 /* 31     0     63    32 */\r
1590                                 {0x00U, 0x00U},\r
1591                         },\r
1592 \r
1593                 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
1594                         {\r
1595                                 /* ownPaRAMSets */\r
1596                                 /* 31     0     63    32     95    64     127   96 */\r
1597                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1598                                 /* 159  128     191  160     223  192     255  224 */\r
1599                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1600                                 /* 287  256     319  288     351  320     383  352 */\r
1601                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1602                                 /* 415  384     447  416     479  448     511  480 */\r
1603                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1604 \r
1605                                 /* ownDmaChannels */\r
1606                                 /* 31     0     63    32 */\r
1607                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1608 \r
1609                                 /* ownQdmaChannels */\r
1610                                 /* 31     0 */\r
1611                                 {0x000000FFU},\r
1612 \r
1613                                 /* ownTccs */\r
1614                                 /* 31     0     63    32 */\r
1615                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1616 \r
1617                                 /* resvdPaRAMSets */\r
1618                                 /* 31     0     63    32     95    64     127   96 */\r
1619                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1620                                 /* 159  128     191  160     223  192     255  224 */\r
1621                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1622                                 /* 287  256     319  288     351  320     383  352 */\r
1623                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1624                                 /* 415  384     447  416     479  448     511  480 */\r
1625                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1626 \r
1627                                 /* resvdDmaChannels */\r
1628                                 /* 31     0     63    32 */\r
1629                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1630 \r
1631                                 /* resvdQdmaChannels */\r
1632                                 /* 31     0 */\r
1633                                 {0x00U},\r
1634 \r
1635                                 /* resvdTccs */\r
1636                                 /* 31     0     63    32 */\r
1637                                 {0x00U, 0x00U},\r
1638                         },\r
1639             },\r
1640                 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
1641                 {\r
1642                 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1643                         {\r
1644                                 /* ownPaRAMSets */\r
1645                                 /* 31     0     63    32     95    64     127   96 */\r
1646                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1647                                 /* 159  128     191  160     223  192     255  224 */\r
1648                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1649                                 /* 287  256     319  288     351  320     383  352 */\r
1650                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1651                                 /* 415  384     447  416     479  448     511  480 */\r
1652                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1653 \r
1654                                 /* ownDmaChannels */\r
1655                                 /* 31     0     63    32 */\r
1656                                 {0x00000000U, 0x00000000U},\r
1657 \r
1658                                 /* ownQdmaChannels */\r
1659                                 /* 31     0 */\r
1660                                 {0x00000000U},\r
1661 \r
1662                                 /* ownTccs */\r
1663                                 /* 31     0     63    32 */\r
1664                                 {0x00000000U, 0x00000000U},\r
1665 \r
1666                                 /* resvdPaRAMSets */\r
1667                                 /* 31     0     63    32     95    64     127   96 */\r
1668                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1669                                 /* 159  128     191  160     223  192     255  224 */\r
1670                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1671                                 /* 287  256     319  288     351  320     383  352 */\r
1672                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1673                                 /* 415  384     447  416     479  448     511  480 */\r
1674                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1675 \r
1676                                 /* resvdDmaChannels */\r
1677                                 /* 31     0     63    32 */\r
1678                                 {0x00000000U, 0x00000000U},\r
1679 \r
1680                                 /* resvdQdmaChannels */\r
1681                                 /* 31     0 */\r
1682                                 {0x00000000U},\r
1683 \r
1684                                 /* resvdTccs */\r
1685                                 /* 31     0     63    32 */\r
1686                                 {0x00000000U, 0x00000000U},\r
1687                         },\r
1688 \r
1689                         /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
1690                         {\r
1691                                 /* ownPaRAMSets */\r
1692                                 /* 31     0     63    32     95    64     127   96 */\r
1693                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1694                                 /* 159  128     191  160     223  192     255  224 */\r
1695                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1696                                 /* 287  256     319  288     351  320     383  352 */\r
1697                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1698                                 /* 415  384     447  416     479  448     511  480 */\r
1699                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1700 \r
1701                                 /* ownDmaChannels */\r
1702                                 /* 31     0     63    32 */\r
1703                                 {0x00000000U, 0x00000000U},\r
1704 \r
1705                                 /* ownQdmaChannels */\r
1706                                 /* 31     0 */\r
1707                                 {0x00000000U},\r
1708 \r
1709                                 /* ownTccs */\r
1710                                 /* 31     0     63    32 */\r
1711                                 {0x00000000U, 0x00000000U},\r
1712 \r
1713                                 /* resvdPaRAMSets */\r
1714                                 /* 31     0     63    32     95    64     127   96 */\r
1715                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1716                                 /* 159  128     191  160     223  192     255  224 */\r
1717                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1718                                 /* 287  256     319  288     351  320     383  352 */\r
1719                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1720                                 /* 415  384     447  416     479  448     511  480 */\r
1721                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1722 \r
1723                                 /* resvdDmaChannels */\r
1724                                 /* 31     0     63    32 */\r
1725                                 {0x00000000U, 0x00000000U},\r
1726 \r
1727                                 /* resvdQdmaChannels */\r
1728                                 /* 31     0 */\r
1729                                 {0x00000000U},\r
1730 \r
1731                                 /* resvdTccs */\r
1732                                 /* 31     0     63    32 */\r
1733                                 {0x00000000U, 0x00000000U},\r
1734                         },\r
1735 \r
1736                 /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
1737                         {\r
1738                                 /* ownPaRAMSets */\r
1739                                 /* 31     0     63    32     95    64     127   96 */\r
1740                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1741                                 /* 159  128     191  160     223  192     255  224 */\r
1742                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1743                                 /* 287  256     319  288     351  320     383  352 */\r
1744                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1745                                 /* 415  384     447  416     479  448     511  480 */\r
1746                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1747 \r
1748                                 /* ownDmaChannels */\r
1749                                 /* 31     0     63    32 */\r
1750                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1751 \r
1752                                 /* ownQdmaChannels */\r
1753                                 /* 31     0 */\r
1754                                 {0x000000FFU},\r
1755 \r
1756                                 /* ownTccs */\r
1757                                 /* 31     0     63    32 */\r
1758                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1759 \r
1760                                 /* resvdPaRAMSets */\r
1761                                 /* 31     0     63    32     95    64     127   96 */\r
1762                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1763                                 /* 159  128     191  160     223  192     255  224 */\r
1764                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1765                                 /* 287  256     319  288     351  320     383  352 */\r
1766                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1767                                 /* 415  384     447  416     479  448     511  480 */\r
1768                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1769 \r
1770                                 /* resvdDmaChannels */\r
1771                                 /* 31     0     63    32 */\r
1772                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1773 \r
1774                                 /* resvdQdmaChannels */\r
1775                                 /* 31     0 */\r
1776                                 {0x00U},\r
1777 \r
1778                                 /* resvdTccs */\r
1779                                 /* 31     0     63    32 */\r
1780                                 {0x00U, 0x00U},\r
1781                         },\r
1782 \r
1783                 /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
1784                         {\r
1785                                 /* ownPaRAMSets */\r
1786                                 /* 31     0     63    32     95    64     127   96 */\r
1787                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1788                                 /* 159  128     191  160     223  192     255  224 */\r
1789                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1790                                 /* 287  256     319  288     351  320     383  352 */\r
1791                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1792                                 /* 415  384     447  416     479  448     511  480 */\r
1793                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1794 \r
1795                                 /* ownDmaChannels */\r
1796                                 /* 31     0     63    32 */\r
1797                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1798 \r
1799                                 /* ownQdmaChannels */\r
1800                                 /* 31     0 */\r
1801                                 {0x000000FFU},\r
1802 \r
1803                                 /* ownTccs */\r
1804                                 /* 31     0     63    32 */\r
1805                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1806 \r
1807                                 /* resvdPaRAMSets */\r
1808                                 /* 31     0     63    32     95    64     127   96 */\r
1809                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
1810                                 /* 159  128     191  160     223  192     255  224 */\r
1811                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1812                                 /* 287  256     319  288     351  320     383  352 */\r
1813                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1814                                 /* 415  384     447  416     479  448     511  480 */\r
1815                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1816 \r
1817                                 /* resvdDmaChannels */\r
1818                                 /* 31     0     63    32 */\r
1819                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1820 \r
1821                                 /* resvdQdmaChannels */\r
1822                                 /* 31     0 */\r
1823                                 {0x00U},\r
1824 \r
1825                                 /* resvdTccs */\r
1826                                 /* 31     0     63    32 */\r
1827                                 {0x00U, 0x00U},\r
1828                         },\r
1829 \r
1830                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1831                         {\r
1832                                 /* ownPaRAMSets */\r
1833                                 /* 31     0     63    32     95    64     127   96 */\r
1834                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1835                                 /* 159  128     191  160     223  192     255  224 */\r
1836                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1837                                 /* 287  256     319  288     351  320     383  352 */\r
1838                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1839                                 /* 415  384     447  416     479  448     511  480 */\r
1840                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1841 \r
1842                                 /* ownDmaChannels */\r
1843                                 /* 31     0     63    32 */\r
1844                                 {0x00000000U, 0x00000000U},\r
1845 \r
1846                                 /* ownQdmaChannels */\r
1847                                 /* 31     0 */\r
1848                                 {0x00000000U},\r
1849 \r
1850                                 /* ownTccs */\r
1851                                 /* 31     0     63    32 */\r
1852                                 {0x00000000U, 0x00000000U},\r
1853 \r
1854                                 /* resvdPaRAMSets */\r
1855                                 /* 31     0     63    32     95    64     127   96 */\r
1856                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1857                                 /* 159  128     191  160     223  192     255  224 */\r
1858                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1859                                 /* 287  256     319  288     351  320     383  352 */\r
1860                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1861                                 /* 415  384     447  416     479  448     511  480 */\r
1862                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1863 \r
1864                                 /* resvdDmaChannels */\r
1865                                 /* 31     0     63    32 */\r
1866                                 {0x00000000U, 0x00000000U},\r
1867 \r
1868                                 /* resvdQdmaChannels */\r
1869                                 /* 31     0 */\r
1870                                 {0x00000000U},\r
1871 \r
1872                                 /* resvdTccs */\r
1873                                 /* 31     0     63    32 */\r
1874                                 {0x00000000U, 0x00000000U},\r
1875                         },\r
1876 \r
1877                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1878                         {\r
1879                                 /* ownPaRAMSets */\r
1880                                 /* 31     0     63    32     95    64     127   96 */\r
1881                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1882                                 /* 159  128     191  160     223  192     255  224 */\r
1883                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1884                                 /* 287  256     319  288     351  320     383  352 */\r
1885                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1886                                 /* 415  384     447  416     479  448     511  480 */\r
1887                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1888 \r
1889                                 /* ownDmaChannels */\r
1890                                 /* 31     0     63    32 */\r
1891                                 {0x00000000U, 0x00000000U},\r
1892 \r
1893                                 /* ownQdmaChannels */\r
1894                                 /* 31     0 */\r
1895                                 {0x00000000U},\r
1896 \r
1897                                 /* ownTccs */\r
1898                                 /* 31     0     63    32 */\r
1899                                 {0x00000000U, 0x00000000U},\r
1900 \r
1901                                 /* resvdPaRAMSets */\r
1902                                 /* 31     0     63    32     95    64     127   96 */\r
1903                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1904                                 /* 159  128     191  160     223  192     255  224 */\r
1905                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1906                                 /* 287  256     319  288     351  320     383  352 */\r
1907                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1908                                 /* 415  384     447  416     479  448     511  480 */\r
1909                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1910 \r
1911                                 /* resvdDmaChannels */\r
1912                                 /* 31     0     63    32 */\r
1913                                 {0x00000000U, 0x00000000U},\r
1914 \r
1915                                 /* resvdQdmaChannels */\r
1916                                 /* 31     0 */\r
1917                                 {0x00000000U},\r
1918 \r
1919                                 /* resvdTccs */\r
1920                                 /* 31     0     63    32 */\r
1921                                 {0x00000000U, 0x00000000U},\r
1922                         },\r
1923 \r
1924                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1925                         {\r
1926                                 /* ownPaRAMSets */\r
1927                                 /* 31     0     63    32     95    64     127   96 */\r
1928                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1929                                 /* 159  128     191  160     223  192     255  224 */\r
1930                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1931                                 /* 287  256     319  288     351  320     383  352 */\r
1932                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1933                                 /* 415  384     447  416     479  448     511  480 */\r
1934                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1935 \r
1936                                 /* ownDmaChannels */\r
1937                                 /* 31     0     63    32 */\r
1938                                 {0x00000000U, 0x00000000U},\r
1939 \r
1940                                 /* ownQdmaChannels */\r
1941                                 /* 31     0 */\r
1942                                 {0x00000000U},\r
1943 \r
1944                                 /* ownTccs */\r
1945                                 /* 31     0     63    32 */\r
1946                                 {0x00000000U, 0x00000000U},\r
1947 \r
1948                                 /* resvdPaRAMSets */\r
1949                                 /* 31     0     63    32     95    64     127   96 */\r
1950                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1951                                 /* 159  128     191  160     223  192     255  224 */\r
1952                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1953                                 /* 287  256     319  288     351  320     383  352 */\r
1954                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1955                                 /* 415  384     447  416     479  448     511  480 */\r
1956                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1957 \r
1958                                 /* resvdDmaChannels */\r
1959                                 /* 31     0     63    32 */\r
1960                                 {0x00000000U, 0x00000000U},\r
1961 \r
1962                                 /* resvdQdmaChannels */\r
1963                                 /* 31     0 */\r
1964                                 {0x00000000U},\r
1965 \r
1966                                 /* resvdTccs */\r
1967                                 /* 31     0     63    32 */\r
1968                                 {0x00000000U, 0x00000000U},\r
1969                         },\r
1970 \r
1971                 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1972                         {\r
1973                                 /* ownPaRAMSets */\r
1974                                 /* 31     0     63    32     95    64     127   96 */\r
1975                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1976                                 /* 159  128     191  160     223  192     255  224 */\r
1977                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1978                                 /* 287  256     319  288     351  320     383  352 */\r
1979                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1980                                 /* 415  384     447  416     479  448     511  480 */\r
1981                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1982 \r
1983                                 /* ownDmaChannels */\r
1984                                 /* 31     0     63    32 */\r
1985                                 {0x00000000U, 0x00000000U},\r
1986 \r
1987                                 /* ownQdmaChannels */\r
1988                                 /* 31     0 */\r
1989                                 {0x00000000U},\r
1990 \r
1991                                 /* ownTccs */\r
1992                                 /* 31     0     63    32 */\r
1993                                 {0x00000000U, 0x00000000U},\r
1994 \r
1995                                 /* resvdPaRAMSets */\r
1996                                 /* 31     0     63    32     95    64     127   96 */\r
1997                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1998                                 /* 159  128     191  160     223  192     255  224 */\r
1999                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2000                                 /* 287  256     319  288     351  320     383  352 */\r
2001                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2002                                 /* 415  384     447  416     479  448     511  480 */\r
2003                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2004 \r
2005                                 /* resvdDmaChannels */\r
2006                                 /* 31     0     63    32 */\r
2007                                 {0x00000000U, 0x00000000U},\r
2008 \r
2009                                 /* resvdQdmaChannels */\r
2010                                 /* 31     0 */\r
2011                                 {0x00000000U},\r
2012 \r
2013                                 /* resvdTccs */\r
2014                                 /* 31     0     63    32 */\r
2015                                 {0x00000000U, 0x00000000U},\r
2016                         },\r
2017             },\r
2018                 /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
2019                 {\r
2020                 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
2021                         {\r
2022                                 /* ownPaRAMSets */\r
2023                                 /* 31     0     63    32     95    64     127   96 */\r
2024                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2025                                 /* 159  128     191  160     223  192     255  224 */\r
2026                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2027                                 /* 287  256     319  288     351  320     383  352 */\r
2028                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2029                                 /* 415  384     447  416     479  448     511  480 */\r
2030                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2031 \r
2032                                 /* ownDmaChannels */\r
2033                                 /* 31     0     63    32 */\r
2034                                 {0x00000000U, 0x00000000U},\r
2035 \r
2036                                 /* ownQdmaChannels */\r
2037                                 /* 31     0 */\r
2038                                 {0x00000000U},\r
2039 \r
2040                                 /* ownTccs */\r
2041                                 /* 31     0     63    32 */\r
2042                                 {0x00000000U, 0x00000000U},\r
2043 \r
2044                                 /* resvdPaRAMSets */\r
2045                                 /* 31     0     63    32     95    64     127   96 */\r
2046                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2047                                 /* 159  128     191  160     223  192     255  224 */\r
2048                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2049                                 /* 287  256     319  288     351  320     383  352 */\r
2050                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2051                                 /* 415  384     447  416     479  448     511  480 */\r
2052                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2053 \r
2054                                 /* resvdDmaChannels */\r
2055                                 /* 31     0     63    32 */\r
2056                                 {0x00000000U, 0x00000000U},\r
2057 \r
2058                                 /* resvdQdmaChannels */\r
2059                                 /* 31     0 */\r
2060                                 {0x00000000U},\r
2061 \r
2062                                 /* resvdTccs */\r
2063                                 /* 31     0     63    32 */\r
2064                                 {0x00000000U, 0x00000000U},\r
2065                         },\r
2066 \r
2067                 /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
2068                         {\r
2069                                 /* ownPaRAMSets */\r
2070                                 /* 31     0     63    32     95    64     127   96 */\r
2071                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
2072                                 /* 159  128     191  160     223  192     255  224 */\r
2073                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2074                                 /* 287  256     319  288     351  320     383  352 */\r
2075                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2076                                 /* 415  384     447  416     479  448     511  480 */\r
2077                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},\r
2078 \r
2079                                 /* ownDmaChannels */\r
2080                                 /* 31     0     63    32 */\r
2081                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
2082 \r
2083                                 /* ownQdmaChannels */\r
2084                                 /* 31     0 */\r
2085                                 {0x000000FFU},\r
2086 \r
2087                                 /* ownTccs */\r
2088                                 /* 31     0     63    32 */\r
2089                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
2090 \r
2091                                 /* resvdPaRAMSets */\r
2092                                 /* 31     0     63    32     95    64     127   96 */\r
2093                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
2094                                 /* 159  128     191  160     223  192     255  224 */\r
2095                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2096                                 /* 287  256     319  288     351  320     383  352 */\r
2097                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2098                                 /* 415  384     447  416     479  448     511  480 */\r
2099                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2100 \r
2101                                 /* resvdDmaChannels */\r
2102                                 /* 31     0     63    32 */\r
2103                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},\r
2104 \r
2105                                 /* resvdQdmaChannels */\r
2106                                 /* 31     0 */\r
2107                                 {0x00U},\r
2108 \r
2109                                 /* resvdTccs */\r
2110                                 /* 31     0     63    32 */\r
2111                                 {0x00U, 0x00U},\r
2112                         },\r
2113 \r
2114                 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
2115                         {\r
2116                                 /* ownPaRAMSets */\r
2117                                 /* 31     0     63    32     95    64     127   96 */\r
2118                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2119                                 /* 159  128     191  160     223  192     255  224 */\r
2120                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2121                                 /* 287  256     319  288     351  320     383  352 */\r
2122                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2123                                 /* 415  384     447  416     479  448     511  480 */\r
2124                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2125 \r
2126                                 /* ownDmaChannels */\r
2127                                 /* 31     0     63    32 */\r
2128                                 {0x00000000U, 0x00000000U},\r
2129 \r
2130                                 /* ownQdmaChannels */\r
2131                                 /* 31     0 */\r
2132                                 {0x00000000U},\r
2133 \r
2134                                 /* ownTccs */\r
2135                                 /* 31     0     63    32 */\r
2136                                 {0x00000000U, 0x00000000U},\r
2137 \r
2138                                 /* resvdPaRAMSets */\r
2139                                 /* 31     0     63    32     95    64     127   96 */\r
2140                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2141                                 /* 159  128     191  160     223  192     255  224 */\r
2142                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2143                                 /* 287  256     319  288     351  320     383  352 */\r
2144                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2145                                 /* 415  384     447  416     479  448     511  480 */\r
2146                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2147 \r
2148                                 /* resvdDmaChannels */\r
2149                                 /* 31     0     63    32 */\r
2150                                 {0x00000000U, 0x00000000U},\r
2151 \r
2152                                 /* resvdQdmaChannels */\r
2153                                 /* 31     0 */\r
2154                                 {0x00000000U},\r
2155 \r
2156                                 /* resvdTccs */\r
2157                                 /* 31     0     63    32 */\r
2158                                 {0x00000000U, 0x00000000U},\r
2159                         },\r
2160 \r
2161                 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
2162                         {\r
2163                                 /* ownPaRAMSets */\r
2164                                 /* 31     0     63    32     95    64     127   96 */\r
2165                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2166                                 /* 159  128     191  160     223  192     255  224 */\r
2167                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2168                                 /* 287  256     319  288     351  320     383  352 */\r
2169                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2170                                 /* 415  384     447  416     479  448     511  480 */\r
2171                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2172 \r
2173                                 /* ownDmaChannels */\r
2174                                 /* 31     0     63    32 */\r
2175                                 {0x00000000U, 0x00000000U},\r
2176 \r
2177                                 /* ownQdmaChannels */\r
2178                                 /* 31     0 */\r
2179                                 {0x00000000U},\r
2180 \r
2181                                 /* ownTccs */\r
2182                                 /* 31     0     63    32 */\r
2183                                 {0x00000000U, 0x00000000U},\r
2184 \r
2185                                 /* resvdPaRAMSets */\r
2186                                 /* 31     0     63    32     95    64     127   96 */\r
2187                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2188                                 /* 159  128     191  160     223  192     255  224 */\r
2189                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2190                                 /* 287  256     319  288     351  320     383  352 */\r
2191                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2192                                 /* 415  384     447  416     479  448     511  480 */\r
2193                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2194 \r
2195                                 /* resvdDmaChannels */\r
2196                                 /* 31     0     63    32 */\r
2197                                 {0x00000000U, 0x00000000U},\r
2198 \r
2199                                 /* resvdQdmaChannels */\r
2200                                 /* 31     0 */\r
2201                                 {0x00000000U},\r
2202 \r
2203                                 /* resvdTccs */\r
2204                                 /* 31     0     63    32 */\r
2205                                 {0x00000000U, 0x00000000U},\r
2206                         },\r
2207 \r
2208                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
2209                         {\r
2210                                 /* ownPaRAMSets */\r
2211                                 /* 31     0     63    32     95    64     127   96 */\r
2212                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2213                                 /* 159  128     191  160     223  192     255  224 */\r
2214                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2215                                 /* 287  256     319  288     351  320     383  352 */\r
2216                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2217                                 /* 415  384     447  416     479  448     511  480 */\r
2218                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2219 \r
2220                                 /* ownDmaChannels */\r
2221                                 /* 31     0     63    32 */\r
2222                                 {0x00000000U, 0x00000000U},\r
2223 \r
2224                                 /* ownQdmaChannels */\r
2225                                 /* 31     0 */\r
2226                                 {0x00000000U},\r
2227 \r
2228                                 /* ownTccs */\r
2229                                 /* 31     0     63    32 */\r
2230                                 {0x00000000U, 0x00000000U},\r
2231 \r
2232                                 /* resvdPaRAMSets */\r
2233                                 /* 31     0     63    32     95    64     127   96 */\r
2234                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2235                                 /* 159  128     191  160     223  192     255  224 */\r
2236                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2237                                 /* 287  256     319  288     351  320     383  352 */\r
2238                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2239                                 /* 415  384     447  416     479  448     511  480 */\r
2240                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2241 \r
2242                                 /* resvdDmaChannels */\r
2243                                 /* 31     0     63    32 */\r
2244                                 {0x00000000U, 0x00000000U},\r
2245 \r
2246                                 /* resvdQdmaChannels */\r
2247                                 /* 31     0 */\r
2248                                 {0x00000000U},\r
2249 \r
2250                                 /* resvdTccs */\r
2251                                 /* 31     0     63    32 */\r
2252                                 {0x00000000U, 0x00000000U},\r
2253                         },\r
2254 \r
2255                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
2256                         {\r
2257                                 /* ownPaRAMSets */\r
2258                                 /* 31     0     63    32     95    64     127   96 */\r
2259                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2260                                 /* 159  128     191  160     223  192     255  224 */\r