[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2 * sample_tda2xx_cfg.c\r
3 *\r
4 * SoC specific EDMA3 hardware related information like number of transfer\r
5 * controllers, various interrupt ids etc. It is used while interrupts\r
6 * enabling / disabling. It needs to be ported for different SoCs.\r
7 *\r
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9 *\r
10 *\r
11 * Redistribution and use in source and binary forms, with or without\r
12 * modification, are permitted provided that the following conditions\r
13 * are met:\r
14 *\r
15 * Redistributions of source code must retain the above copyright\r
16 * notice, this list of conditions and the following disclaimer.\r
17 *\r
18 * Redistributions in binary form must reproduce the above copyright\r
19 * notice, this list of conditions and the following disclaimer in the\r
20 * documentation and/or other materials provided with the\r
21 * distribution.\r
22 *\r
23 * Neither the name of Texas Instruments Incorporated nor the names of\r
24 * its contributors may be used to endorse or promote products derived\r
25 * from this software without specific prior written permission.\r
26 *\r
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38 *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
42 #ifdef BUILD_TDA2XX_IPU\r
43 #include <ti/sysbios/family/arm/ducati/Core.h> \r
44 \r
45 #endif\r
46 \r
47 /* Number of EDMA3 controllers present in the system */\r
48 #define NUM_EDMA3_INSTANCES 2u\r
49 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
50 \r
51 /* Number of DSPs present in the system */\r
52 #define NUM_DSPS 1u\r
53 const unsigned int numDsps = NUM_DSPS;\r
54 \r
55 /* Determine the processor id by reading DNUM register. */\r
56 /* Statically allocate the region numbers with cores. */\r
57 int myCoreNum;\r
58 #define PID0_ADDRESS 0xE00FFFE0\r
59 #define CORE_ID_C0 0x0\r
60 #define CORE_ID_C1 0x1\r
61 \r
62 unsigned short determineProcId()\r
63 {\r
64 unsigned short regionNo = numEdma3Instances;\r
65 myCoreNum = numDsps;\r
66 #ifdef BUILD_TDA2XX_MPU\r
67 \r
68 asm (" push {r0-r2} \n\t"\r
69 " MRC p15, 0, r0, c0, c0, 5\n\t"\r
70 " LDR r1, =myCoreNum\n\t"\r
71 " STR r0, [r1]\n\t"\r
72 " pop {r0-r2}\n\t");\r
73 if((myCoreNum & 0x03) == 1)\r
74 regionNo = 1;\r
75 else\r
76 regionNo = 0;\r
77 #elif defined(BUILD_TDA2XX_IPU)\r
78 myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
79 if(Core_getIpuId() == 1){\r
80 if(myCoreNum == CORE_ID_C0)\r
81 regionNo = 4;\r
82 else if (myCoreNum == CORE_ID_C1)\r
83 regionNo = 5;\r
84 }\r
85 if(Core_getIpuId() == 2){\r
86 if(myCoreNum == CORE_ID_C0)\r
87 regionNo = 6;\r
88 else if (myCoreNum == CORE_ID_C1)\r
89 regionNo = 7;\r
90 }\r
91 #elif defined BUILD_TDA2XX_DSP\r
92 extern __cregister volatile unsigned int DNUM;\r
93 myCoreNum = DNUM;\r
94 if(myCoreNum == 0)\r
95 regionNo = 2;\r
96 else\r
97 regionNo = 3;\r
98 #endif\r
99 return regionNo;\r
100 }\r
101 \r
102 signed char* getGlobalAddr(signed char* addr)\r
103 {\r
104 return (addr); /* The address is already a global address */\r
105 }\r
106 unsigned short isGblConfigRequired(unsigned int dspNum)\r
107 {\r
108 (void) dspNum;\r
109 return 1;\r
110 }\r
111 \r
112 /* Semaphore handles */\r
113 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
114 \r
115 /** Number of PaRAM Sets available */\r
116 #define EDMA3_NUM_PARAMSET (512u)\r
117 \r
118 /** Number of TCCS available */\r
119 #define EDMA3_NUM_TCC (64u)\r
120 \r
121 /** Number of DMA Channels available */\r
122 #define EDMA3_NUM_DMA_CHANNELS (64u)\r
123 \r
124 /** Number of QDMA Channels available */\r
125 #define EDMA3_NUM_QDMA_CHANNELS (8u)\r
126 \r
127 /** Number of Event Queues available */\r
128 #define EDMA3_NUM_EVTQUE (4u)\r
129 \r
130 /** Number of Transfer Controllers available */\r
131 #define EDMA3_NUM_TC (2u)\r
132 \r
133 /** Number of Regions */\r
134 #define EDMA3_NUM_REGIONS (8u)\r
135 \r
136 /** Interrupt no. for Transfer Completion */\r
137 #define EDMA3_CC_XFER_COMPLETION_INT_A15 (66u)\r
138 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u)\r
139 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u)\r
140 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u)\r
141 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
142 #define COMPLETION_INT_A15_XBAR_INST_NO (29u)\r
143 #define COMPLETION_INT_DSP_XBAR_INST_NO (7u)\r
144 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u)\r
145 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u)\r
146 \r
147 /** Interrupt no. for CC Error */\r
148 #define EDMA3_CC_ERROR_INT_A15 (67u)\r
149 #define EDMA3_CC_ERROR_INT_DSP (39u)\r
150 #define EDMA3_CC_ERROR_INT_IPU (35u)\r
151 \r
152 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
153 #define CC_ERROR_INT_A15_XBAR_INST_NO (30u)\r
154 #define CC_ERROR_INT_DSP_XBAR_INST_NO (8u)\r
155 #define CC_ERROR_INT_IPU_XBAR_INST_NO (13u)\r
156 \r
157 /** Interrupt no. for TCs Error */\r
158 #define EDMA3_TC0_ERROR_INT_A15 (68u)\r
159 #define EDMA3_TC0_ERROR_INT_DSP (40u)\r
160 #define EDMA3_TC0_ERROR_INT_IPU (36u)\r
161 #define EDMA3_TC1_ERROR_INT_A15 (69u)\r
162 #define EDMA3_TC1_ERROR_INT_DSP (41u)\r
163 #define EDMA3_TC1_ERROR_INT_IPU (37u)\r
164 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
165 #define TC0_ERROR_INT_A15_XBAR_INST_NO (31u)\r
166 #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u)\r
167 #define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u)\r
168 #define TC1_ERROR_INT_A15_XBAR_INST_NO (32u)\r
169 #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u)\r
170 #define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)\r
171 \r
172 #ifdef BUILD_TDA2XX_MPU\r
173 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15\r
174 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A15\r
175 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_A15_XBAR_INST_NO\r
176 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A15\r
177 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A15\r
178 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
179 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
180 \r
181 #elif defined BUILD_TDA2XX_DSP\r
182 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP\r
183 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP\r
184 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_DSP_XBAR_INST_NO\r
185 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP\r
186 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP\r
187 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_DSP_XBAR_INST_NO\r
188 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_DSP_XBAR_INST_NO\r
189 \r
190 #elif defined BUILD_TDA2XX_IPU\r
191 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU_C0\r
192 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU\r
193 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU_XBAR_INST_NO\r
194 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU\r
195 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU\r
196 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU_XBAR_INST_NO\r
197 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU_XBAR_INST_NO\r
198 \r
199 #else\r
200 #define EDMA3_CC_XFER_COMPLETION_INT (0u)\r
201 #define EDMA3_CC_ERROR_INT (0u)\r
202 #define CC_ERROR_INT_XBAR_INST_NO (0u)\r
203 #define EDMA3_TC0_ERROR_INT (0u)\r
204 #define EDMA3_TC1_ERROR_INT (0u)\r
205 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
206 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
207 #endif\r
208 \r
209 #define EDMA3_TC2_ERROR_INT (0u)\r
210 #define EDMA3_TC3_ERROR_INT (0u)\r
211 #define EDMA3_TC4_ERROR_INT (0u)\r
212 #define EDMA3_TC5_ERROR_INT (0u)\r
213 #define EDMA3_TC6_ERROR_INT (0u)\r
214 #define EDMA3_TC7_ERROR_INT (0u)\r
215 \r
216 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19u)\r
217 #define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20u)\r
218 #define DSP1_EDMA3_CC_ERROR_INT (27u)\r
219 #define DSP1_EDMA3_TC0_ERROR_INT (28u)\r
220 #define DSP1_EDMA3_TC1_ERROR_INT (29u)\r
221 \r
222 /** XBAR interrupt source index numbers for EDMA interrupts */\r
223 #define XBAR_EDMA_TPCC_IRQ_REGION0 (361u)\r
224 #define XBAR_EDMA_TPCC_IRQ_REGION1 (362u)\r
225 #define XBAR_EDMA_TPCC_IRQ_REGION2 (363u)\r
226 #define XBAR_EDMA_TPCC_IRQ_REGION3 (364u)\r
227 #define XBAR_EDMA_TPCC_IRQ_REGION4 (365u)\r
228 #define XBAR_EDMA_TPCC_IRQ_REGION5 (366u)\r
229 #define XBAR_EDMA_TPCC_IRQ_REGION6 (367u)\r
230 #define XBAR_EDMA_TPCC_IRQ_REGION7 (368u)\r
231 \r
232 #define XBAR_EDMA_TPCC_IRQ_ERR (359u)\r
233 #define XBAR_EDMA_TC0_IRQ_ERR (370u)\r
234 #define XBAR_EDMA_TC1_IRQ_ERR (371u)\r
235 \r
236 /**\r
237 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
238 * ECM events (SoC specific). These ECM events come\r
239 * under ECM block XXX (handling those specific ECM events). Normally, block\r
240 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
241 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
242 * is mapped to a specific HWI_INT YYY in the tcf file.\r
243 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
244 * to transfer completion interrupt.\r
245 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
246 * to CC error interrupts.\r
247 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
248 * to TC error interrupts.\r
249 */\r
250 /* EDMA 0 */\r
251 \r
252 #define EDMA3_HWI_INT_XFER_COMP (7u)\r
253 #define EDMA3_HWI_INT_CC_ERR (7u)\r
254 #define EDMA3_HWI_INT_TC0_ERR (10u)\r
255 #define EDMA3_HWI_INT_TC1_ERR (10u)\r
256 #define EDMA3_HWI_INT_TC2_ERR (10u)\r
257 #define EDMA3_HWI_INT_TC3_ERR (10u)\r
258 \r
259 /**\r
260 * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
261 * various peripherals, which use EDMA for data transfer.\r
262 * All channels need not be mapped, some can be free also.\r
263 * 1: Mapped\r
264 * 0: Not mapped\r
265 *\r
266 * This mapping will be used to allocate DMA channels when user passes\r
267 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
268 * copy). The same mapping is used to allocate the TCC when user passes\r
269 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
270 * \r
271 * For Vayu Since the xbar can be used to map event to any EDMA channel,\r
272 * If the application is assigning events to other channel this variable \r
273 * should be modified\r
274 *\r
275 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
276 */\r
277 /* 31 0 */\r
278 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA (0x3FC0C06Eu) /* TBD */\r
279 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFu) /* TBD */\r
280 \r
281 \r
282 /**\r
283 * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
284 * various peripherals, which use EDMA for data transfer.\r
285 * All channels need not be mapped, some can be free also.\r
286 * 1: Mapped\r
287 * 0: Not mapped\r
288 *\r
289 * This mapping will be used to allocate DMA channels when user passes\r
290 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
291 * copy). The same mapping is used to allocate the TCC when user passes\r
292 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
293 *\r
294 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
295 */\r
296 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA (0xF3FFFFF8u) /* TBD */\r
297 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000u) /* TBD */\r
298 \r
299 \r
300 /* Variable which will be used internally for referring number of Event Queues*/\r
301 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {\r
302 EDMA3_NUM_EVTQUE,\r
303 };\r
304 \r
305 /* Variable which will be used internally for referring number of TCs. */\r
306 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
307 EDMA3_NUM_TC,\r
308 };\r
309 \r
310 /**\r
311 * Variable which will be used internally for referring transfer completion\r
312 * interrupt.\r
313 */\r
314 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
315 {\r
316 {\r
317 EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_A15,\r
318 EDMA3_CC_XFER_COMPLETION_INT_DSP, EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
319 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
320 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
321 },\r
322 {\r
323 0u, 0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
324 0u, 0u, 0u, 0u,\r
325 },\r
326 };\r
327 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
328 unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
329 {\r
330 {\r
331 COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_A15_XBAR_INST_NO,\r
332 COMPLETION_INT_DSP_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO,\r
333 COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
334 COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
335 },\r
336 };\r
337 \r
338 /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
339 unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
340 {\r
341 {\r
342 XBAR_EDMA_TPCC_IRQ_REGION0, XBAR_EDMA_TPCC_IRQ_REGION1, XBAR_EDMA_TPCC_IRQ_REGION2, XBAR_EDMA_TPCC_IRQ_REGION3,\r
343 XBAR_EDMA_TPCC_IRQ_REGION4, XBAR_EDMA_TPCC_IRQ_REGION5, XBAR_EDMA_TPCC_IRQ_REGION6, XBAR_EDMA_TPCC_IRQ_REGION7,\r
344 }\r
345 };\r
346 \r
347 /**\r
348 * Variable which will be used internally for referring channel controller's\r
349 * error interrupt.\r
350 */\r
351 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
352 EDMA3_CC_ERROR_INT,DSP1_EDMA3_CC_ERROR_INT,\r
353 };\r
354 unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] = {\r
355 CC_ERROR_INT_XBAR_INST_NO,\r
356 };\r
357 unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
358 {\r
359 XBAR_EDMA_TPCC_IRQ_ERR,\r
360 };\r
361 \r
362 /**\r
363 * Variable which will be used internally for referring transfer controllers'\r
364 * error interrupts.\r
365 */\r
366 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
367 {\r
368 {\r
369 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
370 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
371 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
372 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
373 },\r
374 {\r
375 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
376 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
377 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
378 DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
379 }\r
380 };\r
381 unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =\r
382 {\r
383 {\r
384 TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
385 0u, 0u,\r
386 0u, 0u,\r
387 0u, 0u,\r
388 }\r
389 };\r
390 \r
391 unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][8] =\r
392 {\r
393 {\r
394 XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
395 0u, 0u,\r
396 0u, 0u, 0u, 0u,\r
397 }\r
398 };\r
399 \r
400 \r
401 /**\r
402 * Variables which will be used internally for referring the hardware interrupt\r
403 * for various EDMA3 interrupts.\r
404 */\r
405 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
406 EDMA3_HWI_INT_XFER_COMP, EDMA3_HWI_INT_XFER_COMP,\r
407 };\r
408 \r
409 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
410 EDMA3_HWI_INT_CC_ERR, EDMA3_HWI_INT_CC_ERR,\r
411 };\r
412 \r
413 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
414 {\r
415 EDMA3_HWI_INT_TC0_ERR,\r
416 EDMA3_HWI_INT_TC1_ERR,\r
417 EDMA3_HWI_INT_TC2_ERR,\r
418 EDMA3_HWI_INT_TC3_ERR\r
419 },\r
420 {\r
421 EDMA3_HWI_INT_TC0_ERR,\r
422 EDMA3_HWI_INT_TC1_ERR,\r
423 EDMA3_HWI_INT_TC2_ERR,\r
424 EDMA3_HWI_INT_TC3_ERR\r
425 }\r
426 };\r
427 \r
428 /**\r
429 * \brief Base address as seen from the different cores may be different\r
430 * And is defined based on the core\r
431 */\r
432 #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
433 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))\r
434 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))\r
435 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))\r
436 #elif (defined BUILD_TDA2XX_IPU)\r
437 #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))\r
438 #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))\r
439 #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))\r
440 #else\r
441 #define EDMA3_CC_BASE_ADDR ((void *)(0x0))\r
442 #define EDMA3_TC0_BASE_ADDR ((void *)(0x0))\r
443 #define EDMA3_TC1_BASE_ADDR ((void *)(0x0))\r
444 #endif\r
445 \r
446 #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000))\r
447 #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000))\r
448 #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000))\r
449 \r
450 /* Driver Object Initialization Configuration */\r
451 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
452 {\r
453 {\r
454 /* EDMA3 INSTANCE# 0 */\r
455 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
456 EDMA3_NUM_DMA_CHANNELS,\r
457 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
458 EDMA3_NUM_QDMA_CHANNELS,\r
459 /** Total number of TCCs supported by the EDMA3 Controller */\r
460 EDMA3_NUM_TCC,\r
461 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
462 EDMA3_NUM_PARAMSET,\r
463 /** Total number of Event Queues in the EDMA3 Controller */\r
464 EDMA3_NUM_EVTQUE,\r
465 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
466 EDMA3_NUM_TC,\r
467 /** Number of Regions on this EDMA3 controller */\r
468 EDMA3_NUM_REGIONS,\r
469 \r
470 /**\r
471 * \brief Channel mapping existence\r
472 * A value of 0 (No channel mapping) implies that there is fixed association\r
473 * for a channel number to a parameter entry number or, in other words,\r
474 * PaRAM entry n corresponds to channel n.\r
475 */\r
476 1u,\r
477 \r
478 /** Existence of memory protection feature */\r
479 0u,\r
480 \r
481 /** Global Register Region of CC Registers */\r
482 EDMA3_CC_BASE_ADDR,\r
483 /** Transfer Controller (TC) Registers */\r
484 {\r
485 EDMA3_TC0_BASE_ADDR,\r
486 EDMA3_TC1_BASE_ADDR,\r
487 (void *)NULL,\r
488 (void *)NULL,\r
489 (void *)NULL,\r
490 (void *)NULL,\r
491 (void *)NULL,\r
492 (void *)NULL\r
493 },\r
494 /** Interrupt no. for Transfer Completion */\r
495 EDMA3_CC_XFER_COMPLETION_INT,\r
496 /** Interrupt no. for CC Error */\r
497 EDMA3_CC_ERROR_INT,\r
498 /** Interrupt no. for TCs Error */\r
499 {\r
500 EDMA3_TC0_ERROR_INT,\r
501 EDMA3_TC1_ERROR_INT,\r
502 EDMA3_TC2_ERROR_INT,\r
503 EDMA3_TC3_ERROR_INT,\r
504 EDMA3_TC4_ERROR_INT,\r
505 EDMA3_TC5_ERROR_INT,\r
506 EDMA3_TC6_ERROR_INT,\r
507 EDMA3_TC7_ERROR_INT\r
508 },\r
509 \r
510 /**\r
511 * \brief EDMA3 TC priority setting\r
512 *\r
513 * User can program the priority of the Event Queues\r
514 * at a system-wide level. This means that the user can set the\r
515 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
516 * relative to IO initiated by the other bus masters on the\r
517 * device (ARM, DSP, USB, etc)\r
518 */\r
519 {\r
520 0u,\r
521 1u,\r
522 0u,\r
523 0u,\r
524 0u,\r
525 0u,\r
526 0u,\r
527 0u\r
528 },\r
529 /**\r
530 * \brief To Configure the Threshold level of number of events\r
531 * that can be queued up in the Event queues. EDMA3CC error register\r
532 * (CCERR) will indicate whether or not at any instant of time the\r
533 * number of events queued up in any of the event queues exceeds\r
534 * or equals the threshold/watermark value that is set\r
535 * in the queue watermark threshold register (QWMTHRA).\r
536 */\r
537 {\r
538 16u,\r
539 16u,\r
540 0u,\r
541 0u,\r
542 0u,\r
543 0u,\r
544 0u,\r
545 0u\r
546 },\r
547 \r
548 /**\r
549 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
550 * An optimally-sized command is defined by the transfer controller\r
551 * default burst size (DBS). Different TCs can have different\r
552 * DBS values. It is defined in Bytes.\r
553 */\r
554 {\r
555 16u,\r
556 16u,\r
557 0u,\r
558 0u,\r
559 0u,\r
560 0u,\r
561 0u,\r
562 0u\r
563 },\r
564 \r
565 /**\r
566 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
567 * if it exists, otherwise of no use.\r
568 */\r
569 {\r
570 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
571 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
572 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
573 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
574 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
575 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
576 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
577 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
578 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
579 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
580 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
581 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
582 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
583 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
584 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
585 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
586 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
587 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
588 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
589 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
590 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
591 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
592 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
593 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
594 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
595 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
596 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
597 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
598 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
599 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
600 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
601 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
602 },\r
603 \r
604 /**\r
605 * \brief Mapping from each DMA channel to a TCC. This specific\r
606 * TCC code will be returned when the transfer is completed\r
607 * on the mapped channel.\r
608 */\r
609 {\r
610 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
611 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
612 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
613 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
614 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
615 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
616 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
617 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
618 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
619 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
620 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
621 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
622 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
623 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
624 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
625 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
626 },\r
627 \r
628 /**\r
629 * \brief Mapping of DMA channels to Hardware Events from\r
630 * various peripherals, which use EDMA for data transfer.\r
631 * All channels need not be mapped, some can be free also.\r
632 */\r
633 {\r
634 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,\r
635 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA\r
636 }\r
637 },\r
638 {\r
639 /* EDMA3 INSTANCE# 1 */\r
640 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
641 EDMA3_NUM_DMA_CHANNELS,\r
642 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
643 EDMA3_NUM_QDMA_CHANNELS,\r
644 /** Total number of TCCs supported by the EDMA3 Controller */\r
645 EDMA3_NUM_TCC,\r
646 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
647 EDMA3_NUM_PARAMSET,\r
648 /** Total number of Event Queues in the EDMA3 Controller */\r
649 EDMA3_NUM_EVTQUE,\r
650 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
651 EDMA3_NUM_TC,\r
652 /** Number of Regions on this EDMA3 controller */\r
653 EDMA3_NUM_REGIONS,\r
654 \r
655 /**\r
656 * \brief Channel mapping existence\r
657 * A value of 0 (No channel mapping) implies that there is fixed association\r
658 * for a channel number to a parameter entry number or, in other words,\r
659 * PaRAM entry n corresponds to channel n.\r
660 */\r
661 1u,\r
662 \r
663 /** Existence of memory protection feature */\r
664 0u,\r
665 \r
666 /** Global Register Region of CC Registers */\r
667 DSP1_EDMA3_CC_BASE_ADDR,\r
668 /** Transfer Controller (TC) Registers */\r
669 {\r
670 DSP1_EDMA3_TC0_BASE_ADDR,\r
671 DSP1_EDMA3_TC1_BASE_ADDR,\r
672 (void *)NULL,\r
673 (void *)NULL,\r
674 (void *)NULL,\r
675 (void *)NULL,\r
676 (void *)NULL,\r
677 (void *)NULL\r
678 },\r
679 /** Interrupt no. for Transfer Completion */\r
680 DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
681 /** Interrupt no. for CC Error */\r
682 DSP1_EDMA3_CC_ERROR_INT,\r
683 /** Interrupt no. for TCs Error */\r
684 {\r
685 DSP1_EDMA3_TC0_ERROR_INT,\r
686 DSP1_EDMA3_TC1_ERROR_INT,\r
687 EDMA3_TC2_ERROR_INT,\r
688 EDMA3_TC3_ERROR_INT,\r
689 EDMA3_TC4_ERROR_INT,\r
690 EDMA3_TC5_ERROR_INT,\r
691 EDMA3_TC6_ERROR_INT,\r
692 EDMA3_TC7_ERROR_INT\r
693 },\r
694 \r
695 /**\r
696 * \brief EDMA3 TC priority setting\r
697 *\r
698 * User can program the priority of the Event Queues\r
699 * at a system-wide level. This means that the user can set the\r
700 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
701 * relative to IO initiated by the other bus masters on the\r
702 * device (ARM, DSP, USB, etc)\r
703 */\r
704 {\r
705 0u,\r
706 1u,\r
707 0u,\r
708 0u,\r
709 0u,\r
710 0u,\r
711 0u,\r
712 0u\r
713 },\r
714 /**\r
715 * \brief To Configure the Threshold level of number of events\r
716 * that can be queued up in the Event queues. EDMA3CC error register\r
717 * (CCERR) will indicate whether or not at any instant of time the\r
718 * number of events queued up in any of the event queues exceeds\r
719 * or equals the threshold/watermark value that is set\r
720 * in the queue watermark threshold register (QWMTHRA).\r
721 */\r
722 {\r
723 16u,\r
724 16u,\r
725 0u,\r
726 0u,\r
727 0u,\r
728 0u,\r
729 0u,\r
730 0u\r
731 },\r
732 \r
733 /**\r
734 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
735 * An optimally-sized command is defined by the transfer controller\r
736 * default burst size (DBS). Different TCs can have different\r
737 * DBS values. It is defined in Bytes.\r
738 */\r
739 {\r
740 16u,\r
741 16u,\r
742 0u,\r
743 0u,\r
744 0u,\r
745 0u,\r
746 0u,\r
747 0u\r
748 },\r
749 \r
750 /**\r
751 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
752 * if it exists, otherwise of no use.\r
753 */\r
754 {\r
755 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
756 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
757 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
758 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
759 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
760 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
761 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
762 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
763 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
764 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
765 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
766 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
767 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
768 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
769 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
770 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
771 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
772 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
773 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
774 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
775 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
776 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
777 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
778 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
779 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
780 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
781 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
782 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
783 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
784 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
785 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
786 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
787 },\r
788 \r
789 /**\r
790 * \brief Mapping from each DMA channel to a TCC. This specific\r
791 * TCC code will be returned when the transfer is completed\r
792 * on the mapped channel.\r
793 */\r
794 {\r
795 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
796 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
797 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
798 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
799 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
800 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
801 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
802 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
803 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
804 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
805 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
806 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
807 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
808 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
809 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
810 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
811 },\r
812 \r
813 /**\r
814 * \brief Mapping of DMA channels to Hardware Events from\r
815 * various peripherals, which use EDMA for data transfer.\r
816 * All channels need not be mapped, some can be free also.\r
817 */\r
818 {\r
819 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
820 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
821 }\r
822 },\r
823 };\r
824 \r
825 /**\r
826 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
827 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
828 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
829 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
830 *\r
831 * Only Resources owned by a perticular core are allocated by Driver\r
832 * Reserved resources are not allocated if requested for any available resource\r
833 */\r
834 \r
835 /* Driver Instance Initialization Configuration */\r
836 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
837 {\r
838 /* EDMA3 INSTANCE# 0 */\r
839 {\r
840 /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
841 {\r
842 /* ownPaRAMSets */\r
843 /* 31 0 63 32 95 64 127 96 */\r
844 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
845 /* 159 128 191 160 223 192 255 224 */\r
846 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
847 /* 287 256 319 288 351 320 383 352 */\r
848 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
849 /* 415 384 447 416 479 448 511 480 */\r
850 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
851 \r
852 /* ownDmaChannels */\r
853 /* 31 0 63 32 */\r
854 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
855 \r
856 /* ownQdmaChannels */\r
857 /* 31 0 */\r
858 {0x000000FFu},\r
859 \r
860 /* ownTccs */\r
861 /* 31 0 63 32 */\r
862 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
863 \r
864 /* resvdPaRAMSets */\r
865 /* 31 0 63 32 95 64 127 96 */\r
866 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
867 /* 159 128 191 160 223 192 255 224 */\r
868 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
869 /* 287 256 319 288 351 320 383 352 */\r
870 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
871 /* 415 384 447 416 479 448 511 480 */\r
872 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
873 \r
874 /* resvdDmaChannels */\r
875 /* 31 0 63 32 */\r
876 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
877 \r
878 /* resvdQdmaChannels */\r
879 /* 31 0 */\r
880 {0x00u},\r
881 \r
882 /* resvdTccs */\r
883 /* 31 0 63 32 */\r
884 {0x00u, 0x00u},\r
885 },\r
886 \r
887 /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
888 {\r
889 /* ownPaRAMSets */\r
890 /* 31 0 63 32 95 64 127 96 */\r
891 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
892 /* 159 128 191 160 223 192 255 224 */\r
893 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
894 /* 287 256 319 288 351 320 383 352 */\r
895 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
896 /* 415 384 447 416 479 448 511 480 */\r
897 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
898 \r
899 /* ownDmaChannels */\r
900 /* 31 0 63 32 */\r
901 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
902 \r
903 /* ownQdmaChannels */\r
904 /* 31 0 */\r
905 {0x000000FFu},\r
906 \r
907 /* ownTccs */\r
908 /* 31 0 63 32 */\r
909 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
910 \r
911 /* resvdPaRAMSets */\r
912 /* 31 0 63 32 95 64 127 96 */\r
913 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
914 /* 159 128 191 160 223 192 255 224 */\r
915 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
916 /* 287 256 319 288 351 320 383 352 */\r
917 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
918 /* 415 384 447 416 479 448 511 480 */\r
919 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
920 \r
921 /* resvdDmaChannels */\r
922 /* 31 0 63 32 */\r
923 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
924 \r
925 /* resvdQdmaChannels */\r
926 /* 31 0 */\r
927 {0x00u},\r
928 \r
929 /* resvdTccs */\r
930 /* 31 0 63 32 */\r
931 {0x00u, 0x00u},\r
932 },\r
933 \r
934 /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
935 {\r
936 /* ownPaRAMSets */\r
937 /* 31 0 63 32 95 64 127 96 */\r
938 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
939 /* 159 128 191 160 223 192 255 224 */\r
940 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
941 /* 287 256 319 288 351 320 383 352 */\r
942 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
943 /* 415 384 447 416 479 448 511 480 */\r
944 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
945 \r
946 /* ownDmaChannels */\r
947 /* 31 0 63 32 */\r
948 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
949 \r
950 /* ownQdmaChannels */\r
951 /* 31 0 */\r
952 {0x000000FFu},\r
953 \r
954 /* ownTccs */\r
955 /* 31 0 63 32 */\r
956 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
957 \r
958 /* resvdPaRAMSets */\r
959 /* 31 0 63 32 95 64 127 96 */\r
960 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
961 /* 159 128 191 160 223 192 255 224 */\r
962 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
963 /* 287 256 319 288 351 320 383 352 */\r
964 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
965 /* 415 384 447 416 479 448 511 480 */\r
966 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
967 \r
968 /* resvdDmaChannels */\r
969 /* 31 0 63 32 */\r
970 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
971 \r
972 /* resvdQdmaChannels */\r
973 /* 31 0 */\r
974 {0x00u},\r
975 \r
976 /* resvdTccs */\r
977 /* 31 0 63 32 */\r
978 {0x00u, 0x00u},\r
979 },\r
980 \r
981 /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
982 {\r
983 /* ownPaRAMSets */\r
984 /* 31 0 63 32 95 64 127 96 */\r
985 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
986 /* 159 128 191 160 223 192 255 224 */\r
987 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
988 /* 287 256 319 288 351 320 383 352 */\r
989 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
990 /* 415 384 447 416 479 448 511 480 */\r
991 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
992 \r
993 /* ownDmaChannels */\r
994 /* 31 0 63 32 */\r
995 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
996 \r
997 /* ownQdmaChannels */\r
998 /* 31 0 */\r
999 {0x000000FFu},\r
1000 \r
1001 /* ownTccs */\r
1002 /* 31 0 63 32 */\r
1003 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1004 \r
1005 /* resvdPaRAMSets */\r
1006 /* 31 0 63 32 95 64 127 96 */\r
1007 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1008 /* 159 128 191 160 223 192 255 224 */\r
1009 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1010 /* 287 256 319 288 351 320 383 352 */\r
1011 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1012 /* 415 384 447 416 479 448 511 480 */\r
1013 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1014 \r
1015 /* resvdDmaChannels */\r
1016 /* 31 0 63 32 */\r
1017 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1018 \r
1019 /* resvdQdmaChannels */\r
1020 /* 31 0 */\r
1021 {0x00u},\r
1022 \r
1023 /* resvdTccs */\r
1024 /* 31 0 63 32 */\r
1025 {0x00u, 0x00u},\r
1026 },\r
1027 \r
1028 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
1029 {\r
1030 /* ownPaRAMSets */\r
1031 /* 31 0 63 32 95 64 127 96 */\r
1032 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1033 /* 159 128 191 160 223 192 255 224 */\r
1034 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1035 /* 287 256 319 288 351 320 383 352 */\r
1036 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1037 /* 415 384 447 416 479 448 511 480 */\r
1038 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1039 \r
1040 /* ownDmaChannels */\r
1041 /* 31 0 63 32 */\r
1042 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1043 \r
1044 /* ownQdmaChannels */\r
1045 /* 31 0 */\r
1046 {0x000000FFu},\r
1047 \r
1048 /* ownTccs */\r
1049 /* 31 0 63 32 */\r
1050 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1051 \r
1052 /* resvdPaRAMSets */\r
1053 /* 31 0 63 32 95 64 127 96 */\r
1054 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1055 /* 159 128 191 160 223 192 255 224 */\r
1056 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1057 /* 287 256 319 288 351 320 383 352 */\r
1058 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1059 /* 415 384 447 416 479 448 511 480 */\r
1060 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1061 \r
1062 /* resvdDmaChannels */\r
1063 /* 31 0 63 32 */\r
1064 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1065 \r
1066 /* resvdQdmaChannels */\r
1067 /* 31 0 */\r
1068 {0x00u},\r
1069 \r
1070 /* resvdTccs */\r
1071 /* 31 0 63 32 */\r
1072 {0x00u, 0x00u},\r
1073 },\r
1074 \r
1075 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
1076 {\r
1077 /* ownPaRAMSets */\r
1078 /* 31 0 63 32 95 64 127 96 */\r
1079 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1080 /* 159 128 191 160 223 192 255 224 */\r
1081 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1082 /* 287 256 319 288 351 320 383 352 */\r
1083 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1084 /* 415 384 447 416 479 448 511 480 */\r
1085 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1086 \r
1087 /* ownDmaChannels */\r
1088 /* 31 0 63 32 */\r
1089 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1090 \r
1091 /* ownQdmaChannels */\r
1092 /* 31 0 */\r
1093 {0x000000FFu},\r
1094 \r
1095 /* ownTccs */\r
1096 /* 31 0 63 32 */\r
1097 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1098 \r
1099 /* resvdPaRAMSets */\r
1100 /* 31 0 63 32 95 64 127 96 */\r
1101 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1102 /* 159 128 191 160 223 192 255 224 */\r
1103 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1104 /* 287 256 319 288 351 320 383 352 */\r
1105 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1106 /* 415 384 447 416 479 448 511 480 */\r
1107 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1108 \r
1109 /* resvdDmaChannels */\r
1110 /* 31 0 63 32 */\r
1111 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1112 \r
1113 /* resvdQdmaChannels */\r
1114 /* 31 0 */\r
1115 {0x00u},\r
1116 \r
1117 /* resvdTccs */\r
1118 /* 31 0 63 32 */\r
1119 {0x00u, 0x00u},\r
1120 },\r
1121 \r
1122 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
1123 {\r
1124 /* ownPaRAMSets */\r
1125 /* 31 0 63 32 95 64 127 96 */\r
1126 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1127 /* 159 128 191 160 223 192 255 224 */\r
1128 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1129 /* 287 256 319 288 351 320 383 352 */\r
1130 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1131 /* 415 384 447 416 479 448 511 480 */\r
1132 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1133 \r
1134 /* ownDmaChannels */\r
1135 /* 31 0 63 32 */\r
1136 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1137 \r
1138 /* ownQdmaChannels */\r
1139 /* 31 0 */\r
1140 {0x000000FFu},\r
1141 \r
1142 /* ownTccs */\r
1143 /* 31 0 63 32 */\r
1144 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1145 \r
1146 /* resvdPaRAMSets */\r
1147 /* 31 0 63 32 95 64 127 96 */\r
1148 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1149 /* 159 128 191 160 223 192 255 224 */\r
1150 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1151 /* 287 256 319 288 351 320 383 352 */\r
1152 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1153 /* 415 384 447 416 479 448 511 480 */\r
1154 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1155 \r
1156 /* resvdDmaChannels */\r
1157 /* 31 0 63 32 */\r
1158 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1159 \r
1160 /* resvdQdmaChannels */\r
1161 /* 31 0 */\r
1162 {0x00u},\r
1163 \r
1164 /* resvdTccs */\r
1165 /* 31 0 63 32 */\r
1166 {0x00u, 0x00u},\r
1167 },\r
1168 \r
1169 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
1170 {\r
1171 /* ownPaRAMSets */\r
1172 /* 31 0 63 32 95 64 127 96 */\r
1173 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1174 /* 159 128 191 160 223 192 255 224 */\r
1175 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1176 /* 287 256 319 288 351 320 383 352 */\r
1177 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1178 /* 415 384 447 416 479 448 511 480 */\r
1179 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1180 \r
1181 /* ownDmaChannels */\r
1182 /* 31 0 63 32 */\r
1183 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1184 \r
1185 /* ownQdmaChannels */\r
1186 /* 31 0 */\r
1187 {0x000000FFu},\r
1188 \r
1189 /* ownTccs */\r
1190 /* 31 0 63 32 */\r
1191 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1192 \r
1193 /* resvdPaRAMSets */\r
1194 /* 31 0 63 32 95 64 127 96 */\r
1195 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1196 /* 159 128 191 160 223 192 255 224 */\r
1197 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1198 /* 287 256 319 288 351 320 383 352 */\r
1199 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1200 /* 415 384 447 416 479 448 511 480 */\r
1201 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1202 \r
1203 /* resvdDmaChannels */\r
1204 /* 31 0 63 32 */\r
1205 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
1206 \r
1207 /* resvdQdmaChannels */\r
1208 /* 31 0 */\r
1209 {0x00u},\r
1210 \r
1211 /* resvdTccs */\r
1212 /* 31 0 63 32 */\r
1213 {0x00u, 0x00u},\r
1214 },\r
1215 },\r
1216 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
1217 {\r
1218 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1219 {\r
1220 /* ownPaRAMSets */\r
1221 /* 31 0 63 32 95 64 127 96 */\r
1222 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1223 /* 159 128 191 160 223 192 255 224 */\r
1224 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1225 /* 287 256 319 288 351 320 383 352 */\r
1226 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1227 /* 415 384 447 416 479 448 511 480 */\r
1228 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1229 \r
1230 /* ownDmaChannels */\r
1231 /* 31 0 63 32 */\r
1232 {0x00000000u, 0x00000000u},\r
1233 \r
1234 /* ownQdmaChannels */\r
1235 /* 31 0 */\r
1236 {0x00000000u},\r
1237 \r
1238 /* ownTccs */\r
1239 /* 31 0 63 32 */\r
1240 {0x00000000u, 0x00000000u},\r
1241 \r
1242 /* resvdPaRAMSets */\r
1243 /* 31 0 63 32 95 64 127 96 */\r
1244 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1245 /* 159 128 191 160 223 192 255 224 */\r
1246 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1247 /* 287 256 319 288 351 320 383 352 */\r
1248 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1249 /* 415 384 447 416 479 448 511 480 */\r
1250 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1251 \r
1252 /* resvdDmaChannels */\r
1253 /* 31 0 63 32 */\r
1254 {0x00000000u, 0x00000000u},\r
1255 \r
1256 /* resvdQdmaChannels */\r
1257 /* 31 0 */\r
1258 {0x00000000u},\r
1259 \r
1260 /* resvdTccs */\r
1261 /* 31 0 63 32 */\r
1262 {0x00000000u, 0x00000000u},\r
1263 },\r
1264 \r
1265 /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
1266 {\r
1267 /* ownPaRAMSets */\r
1268 /* 31 0 63 32 95 64 127 96 */\r
1269 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1270 /* 159 128 191 160 223 192 255 224 */\r
1271 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1272 /* 287 256 319 288 351 320 383 352 */\r
1273 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1274 /* 415 384 447 416 479 448 511 480 */\r
1275 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1276 \r
1277 /* ownDmaChannels */\r
1278 /* 31 0 63 32 */\r
1279 {0x00000000u, 0x00000000u},\r
1280 \r
1281 /* ownQdmaChannels */\r
1282 /* 31 0 */\r
1283 {0x00000000u},\r
1284 \r
1285 /* ownTccs */\r
1286 /* 31 0 63 32 */\r
1287 {0x00000000u, 0x00000000u},\r
1288 \r
1289 /* resvdPaRAMSets */\r
1290 /* 31 0 63 32 95 64 127 96 */\r
1291 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1292 /* 159 128 191 160 223 192 255 224 */\r
1293 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1294 /* 287 256 319 288 351 320 383 352 */\r
1295 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1296 /* 415 384 447 416 479 448 511 480 */\r
1297 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1298 \r
1299 /* resvdDmaChannels */\r
1300 /* 31 0 63 32 */\r
1301 {0x00000000u, 0x00000000u},\r
1302 \r
1303 /* resvdQdmaChannels */\r
1304 /* 31 0 */\r
1305 {0x00000000u},\r
1306 \r
1307 /* resvdTccs */\r
1308 /* 31 0 63 32 */\r
1309 {0x00000000u, 0x00000000u},\r
1310 },\r
1311 \r
1312 /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
1313 {\r
1314 /* ownPaRAMSets */\r
1315 /* 31 0 63 32 95 64 127 96 */\r
1316 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1317 /* 159 128 191 160 223 192 255 224 */\r
1318 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1319 /* 287 256 319 288 351 320 383 352 */\r
1320 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1321 /* 415 384 447 416 479 448 511 480 */\r
1322 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1323 \r
1324 /* ownDmaChannels */\r
1325 /* 31 0 63 32 */\r
1326 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1327 \r
1328 /* ownQdmaChannels */\r
1329 /* 31 0 */\r
1330 {0x000000FFu},\r
1331 \r
1332 /* ownTccs */\r
1333 /* 31 0 63 32 */\r
1334 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1335 \r
1336 /* resvdPaRAMSets */\r
1337 /* 31 0 63 32 95 64 127 96 */\r
1338 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1339 /* 159 128 191 160 223 192 255 224 */\r
1340 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1341 /* 287 256 319 288 351 320 383 352 */\r
1342 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1343 /* 415 384 447 416 479 448 511 480 */\r
1344 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1345 \r
1346 /* resvdDmaChannels */\r
1347 /* 31 0 63 32 */\r
1348 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1349 \r
1350 /* resvdQdmaChannels */\r
1351 /* 31 0 */\r
1352 {0x00u},\r
1353 \r
1354 /* resvdTccs */\r
1355 /* 31 0 63 32 */\r
1356 {0x00u, 0x00u},\r
1357 },\r
1358 \r
1359 /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
1360 {\r
1361 /* ownPaRAMSets */\r
1362 /* 31 0 63 32 95 64 127 96 */\r
1363 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1364 /* 159 128 191 160 223 192 255 224 */\r
1365 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1366 /* 287 256 319 288 351 320 383 352 */\r
1367 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1368 /* 415 384 447 416 479 448 511 480 */\r
1369 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1370 \r
1371 /* ownDmaChannels */\r
1372 /* 31 0 63 32 */\r
1373 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1374 \r
1375 /* ownQdmaChannels */\r
1376 /* 31 0 */\r
1377 {0x000000FFu},\r
1378 \r
1379 /* ownTccs */\r
1380 /* 31 0 63 32 */\r
1381 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1382 \r
1383 /* resvdPaRAMSets */\r
1384 /* 31 0 63 32 95 64 127 96 */\r
1385 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1386 /* 159 128 191 160 223 192 255 224 */\r
1387 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1388 /* 287 256 319 288 351 320 383 352 */\r
1389 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1390 /* 415 384 447 416 479 448 511 480 */\r
1391 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1392 \r
1393 /* resvdDmaChannels */\r
1394 /* 31 0 63 32 */\r
1395 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1396 \r
1397 /* resvdQdmaChannels */\r
1398 /* 31 0 */\r
1399 {0x00u},\r
1400 \r
1401 /* resvdTccs */\r
1402 /* 31 0 63 32 */\r
1403 {0x00u, 0x00u},\r
1404 },\r
1405 \r
1406 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1407 {\r
1408 /* ownPaRAMSets */\r
1409 /* 31 0 63 32 95 64 127 96 */\r
1410 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1411 /* 159 128 191 160 223 192 255 224 */\r
1412 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1413 /* 287 256 319 288 351 320 383 352 */\r
1414 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1415 /* 415 384 447 416 479 448 511 480 */\r
1416 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1417 \r
1418 /* ownDmaChannels */\r
1419 /* 31 0 63 32 */\r
1420 {0x00000000u, 0x00000000u},\r
1421 \r
1422 /* ownQdmaChannels */\r
1423 /* 31 0 */\r
1424 {0x00000000u},\r
1425 \r
1426 /* ownTccs */\r
1427 /* 31 0 63 32 */\r
1428 {0x00000000u, 0x00000000u},\r
1429 \r
1430 /* resvdPaRAMSets */\r
1431 /* 31 0 63 32 95 64 127 96 */\r
1432 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1433 /* 159 128 191 160 223 192 255 224 */\r
1434 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1435 /* 287 256 319 288 351 320 383 352 */\r
1436 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1437 /* 415 384 447 416 479 448 511 480 */\r
1438 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1439 \r
1440 /* resvdDmaChannels */\r
1441 /* 31 0 63 32 */\r
1442 {0x00000000u, 0x00000000u},\r
1443 \r
1444 /* resvdQdmaChannels */\r
1445 /* 31 0 */\r
1446 {0x00000000u},\r
1447 \r
1448 /* resvdTccs */\r
1449 /* 31 0 63 32 */\r
1450 {0x00000000u, 0x00000000u},\r
1451 },\r
1452 \r
1453 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1454 {\r
1455 /* ownPaRAMSets */\r
1456 /* 31 0 63 32 95 64 127 96 */\r
1457 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1458 /* 159 128 191 160 223 192 255 224 */\r
1459 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1460 /* 287 256 319 288 351 320 383 352 */\r
1461 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1462 /* 415 384 447 416 479 448 511 480 */\r
1463 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1464 \r
1465 /* ownDmaChannels */\r
1466 /* 31 0 63 32 */\r
1467 {0x00000000u, 0x00000000u},\r
1468 \r
1469 /* ownQdmaChannels */\r
1470 /* 31 0 */\r
1471 {0x00000000u},\r
1472 \r
1473 /* ownTccs */\r
1474 /* 31 0 63 32 */\r
1475 {0x00000000u, 0x00000000u},\r
1476 \r
1477 /* resvdPaRAMSets */\r
1478 /* 31 0 63 32 95 64 127 96 */\r
1479 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1480 /* 159 128 191 160 223 192 255 224 */\r
1481 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1482 /* 287 256 319 288 351 320 383 352 */\r
1483 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1484 /* 415 384 447 416 479 448 511 480 */\r
1485 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1486 \r
1487 /* resvdDmaChannels */\r
1488 /* 31 0 63 32 */\r
1489 {0x00000000u, 0x00000000u},\r
1490 \r
1491 /* resvdQdmaChannels */\r
1492 /* 31 0 */\r
1493 {0x00000000u},\r
1494 \r
1495 /* resvdTccs */\r
1496 /* 31 0 63 32 */\r
1497 {0x00000000u, 0x00000000u},\r
1498 },\r
1499 \r
1500 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1501 {\r
1502 /* ownPaRAMSets */\r
1503 /* 31 0 63 32 95 64 127 96 */\r
1504 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1505 /* 159 128 191 160 223 192 255 224 */\r
1506 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1507 /* 287 256 319 288 351 320 383 352 */\r
1508 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1509 /* 415 384 447 416 479 448 511 480 */\r
1510 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1511 \r
1512 /* ownDmaChannels */\r
1513 /* 31 0 63 32 */\r
1514 {0x00000000u, 0x00000000u},\r
1515 \r
1516 /* ownQdmaChannels */\r
1517 /* 31 0 */\r
1518 {0x00000000u},\r
1519 \r
1520 /* ownTccs */\r
1521 /* 31 0 63 32 */\r
1522 {0x00000000u, 0x00000000u},\r
1523 \r
1524 /* resvdPaRAMSets */\r
1525 /* 31 0 63 32 95 64 127 96 */\r
1526 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1527 /* 159 128 191 160 223 192 255 224 */\r
1528 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1529 /* 287 256 319 288 351 320 383 352 */\r
1530 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1531 /* 415 384 447 416 479 448 511 480 */\r
1532 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1533 \r
1534 /* resvdDmaChannels */\r
1535 /* 31 0 63 32 */\r
1536 {0x00000000u, 0x00000000u},\r
1537 \r
1538 /* resvdQdmaChannels */\r
1539 /* 31 0 */\r
1540 {0x00000000u},\r
1541 \r
1542 /* resvdTccs */\r
1543 /* 31 0 63 32 */\r
1544 {0x00000000u, 0x00000000u},\r
1545 },\r
1546 \r
1547 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1548 {\r
1549 /* ownPaRAMSets */\r
1550 /* 31 0 63 32 95 64 127 96 */\r
1551 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1552 /* 159 128 191 160 223 192 255 224 */\r
1553 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1554 /* 287 256 319 288 351 320 383 352 */\r
1555 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1556 /* 415 384 447 416 479 448 511 480 */\r
1557 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1558 \r
1559 /* ownDmaChannels */\r
1560 /* 31 0 63 32 */\r
1561 {0x00000000u, 0x00000000u},\r
1562 \r
1563 /* ownQdmaChannels */\r
1564 /* 31 0 */\r
1565 {0x00000000u},\r
1566 \r
1567 /* ownTccs */\r
1568 /* 31 0 63 32 */\r
1569 {0x00000000u, 0x00000000u},\r
1570 \r
1571 /* resvdPaRAMSets */\r
1572 /* 31 0 63 32 95 64 127 96 */\r
1573 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1574 /* 159 128 191 160 223 192 255 224 */\r
1575 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1576 /* 287 256 319 288 351 320 383 352 */\r
1577 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1578 /* 415 384 447 416 479 448 511 480 */\r
1579 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1580 \r
1581 /* resvdDmaChannels */\r
1582 /* 31 0 63 32 */\r
1583 {0x00000000u, 0x00000000u},\r
1584 \r
1585 /* resvdQdmaChannels */\r
1586 /* 31 0 */\r
1587 {0x00000000u},\r
1588 \r
1589 /* resvdTccs */\r
1590 /* 31 0 63 32 */\r
1591 {0x00000000u, 0x00000000u},\r
1592 },\r
1593 },\r
1594 };\r
1595 \r
1596 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
1597 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
1598 {\r
1599 /* EDMA3 INSTANCE# 0 */\r
1600 {\r
1601 /* Event to channel map for region 0 */\r
1602 {\r
1603 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1604 -1, -1, -1, -1, -1, -1, -1, -1,\r
1605 -1, -1, -1, -1, -1, -1, -1, -1,\r
1606 -1, -1, -1, -1, -1, -1, -1, -1,\r
1607 -1, -1, -1, -1, -1, -1, -1, -1,\r
1608 -1, -1, -1, -1, -1, -1, -1, -1,\r
1609 -1, -1, -1, -1, -1, -1, -1, -1,\r
1610 -1, -1, -1, -1, -1, -1, -1}\r
1611 },\r
1612 /* Event to channel map for region 1 */\r
1613 {\r
1614 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1615 -1, -1, -1, -1, -1, -1, -1, -1,\r
1616 -1, -1, -1, -1, -1, -1, -1, -1,\r
1617 -1, -1, -1, -1, -1, -1, -1, -1,\r
1618 -1, -1, -1, -1, -1, -1, -1, -1,\r
1619 -1, -1, -1, -1, -1, -1, -1, -1,\r
1620 -1, -1, -1, -1, -1, -1, -1, -1,\r
1621 -1, -1, -1, -1, -1, -1, -1}\r
1622 },\r
1623 /* Event to channel map for region 2 */\r
1624 {\r
1625 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1626 -1, -1, -1, -1, -1, -1, -1, -1,\r
1627 -1, -1, -1, -1, -1, -1, -1, -1,\r
1628 -1, -1, -1, -1, -1, -1, -1, -1,\r
1629 -1, -1, -1, -1, -1, -1, -1, -1,\r
1630 -1, -1, -1, -1, -1, -1, -1, -1,\r
1631 -1, -1, -1, -1, -1, -1, -1, -1,\r
1632 -1, -1, -1, -1, -1, -1, -1}\r
1633 },\r
1634 /* Event to channel map for region 3 */\r
1635 {\r
1636 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1637 -1, -1, -1, -1, -1, -1, -1, -1,\r
1638 -1, -1, -1, -1, -1, -1, -1, -1,\r
1639 -1, -1, -1, -1, -1, -1, -1, -1,\r
1640 -1, -1, -1, -1, -1, -1, -1, -1,\r
1641 -1, -1, -1, -1, -1, -1, -1, -1,\r
1642 -1, -1, -1, -1, -1, -1, -1, -1,\r
1643 -1, -1, -1, -1, -1, -1, -1}\r
1644 },\r
1645 /* Event to channel map for region 4 */\r
1646 {\r
1647 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1648 -1, -1, -1, -1, -1, -1, -1, -1,\r
1649 -1, -1, -1, -1, -1, -1, -1, -1,\r
1650 -1, -1, -1, -1, -1, -1, -1, -1,\r
1651 -1, -1, -1, -1, -1, -1, -1, -1,\r
1652 -1, -1, -1, -1, -1, -1, -1, -1,\r
1653 -1, -1, -1, -1, -1, -1, -1, -1,\r
1654 -1, -1, -1, -1, -1, -1, -1}\r
1655 },\r
1656 /* Event to channel map for region 5 */\r
1657 {\r
1658 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1659 -1, -1, -1, -1, -1, -1, -1, -1,\r
1660 -1, -1, -1, -1, -1, -1, -1, -1,\r
1661 -1, -1, -1, -1, -1, -1, -1, -1,\r
1662 -1, -1, -1, -1, -1, -1, -1, -1,\r
1663 -1, -1, -1, -1, -1, -1, -1, -1,\r
1664 -1, -1, -1, -1, -1, -1, -1, -1,\r
1665 -1, -1, -1, -1, -1, -1, -1}\r
1666 },\r
1667 /* Event to channel map for region 6 */\r
1668 {\r
1669 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1670 -1, -1, -1, -1, -1, -1, -1, -1,\r
1671 -1, -1, -1, -1, -1, -1, -1, -1,\r
1672 -1, -1, -1, -1, -1, -1, -1, -1,\r
1673 -1, -1, -1, -1, -1, -1, -1, -1,\r
1674 -1, -1, -1, -1, -1, -1, -1, -1,\r
1675 -1, -1, -1, -1, -1, -1, -1, -1,\r
1676 -1, -1, -1, -1, -1, -1, -1}\r
1677 },\r
1678 /* Event to channel map for region 7 */\r
1679 {\r
1680 {-1, -1, -1, -1, -1, -1, -1, -1,\r
1681 -1, -1, -1, -1, -1, -1, -1, -1,\r
1682 -1, -1, -1, -1, -1, -1, -1, -1,\r
1683 -1, -1, -1, -1, -1, -1, -1, -1,\r
1684 -1, -1, -1, -1, -1, -1, -1, -1,\r
1685 -1, -1, -1, -1, -1, -1, -1, -1,\r
1686 -1, -1, -1, -1, -1, -1, -1, -1,\r
1687 -1, -1, -1, -1, -1, -1, -1}\r
1688 },\r
1689 }\r
1690 };\r
1691 \r
1692 /* End of File */\r
1693 \r