PRSDK-3125: Update remainig
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2  * sample_tda2xx_cfg.c\r
3  *\r
4  * SoC specific EDMA3 hardware related information like number of transfer\r
5  * controllers, various interrupt ids etc. It is used while interrupts\r
6  * enabling / disabling. It needs to be ported for different SoCs.\r
7  *\r
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9  *\r
10  *\r
11  *  Redistribution and use in source and binary forms, with or without\r
12  *  modification, are permitted provided that the following conditions\r
13  *  are met:\r
14  *\r
15  *    Redistributions of source code must retain the above copyright\r
16  *    notice, this list of conditions and the following disclaimer.\r
17  *\r
18  *    Redistributions in binary form must reproduce the above copyright\r
19  *    notice, this list of conditions and the following disclaimer in the\r
20  *    documentation and/or other materials provided with the\r
21  *    distribution.\r
22  *\r
23  *    Neither the name of Texas Instruments Incorporated nor the names of\r
24  *    its contributors may be used to endorse or promote products derived\r
25  *    from this software without specific prior written permission.\r
26  *\r
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38  *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
42 #ifdef BUILD_TDA2XX_IPU\r
43 #include <ti/sysbios/family/arm/ducati/Core.h> \r
44 \r
45 #endif\r
46 \r
47 /* Number of EDMA3 controllers present in the system */\r
48 #define NUM_EDMA3_INSTANCES         3U\r
49 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;\r
50 \r
51 /* Number of DSPs present in the system */\r
52 #define NUM_DSPS                    1U\r
53 const uint32_t numDsps = NUM_DSPS;\r
54 \r
55 /* Determine the processor id by reading DNUM register. */\r
56 /* Statically allocate the region numbers with cores. */\r
57 volatile int32_t myCoreNum;\r
58 #define PID0_ADDRESS 0xE00FFFE0U\r
59 #define CORE_ID_C0 0x0U\r
60 #define CORE_ID_C1 0x1U\r
61 \r
62 #ifdef BUILD_TDA2XX_MPU\r
63 static inline void readProcFeatureReg(void);\r
64 static inline void readProcFeatureReg(void)\r
65 {\r
66     asm ("    push    {r0-r2} \n\t"\r
67              "    MRC p15, 0, r0, c0, c0, 5\n\t"\r
68                  "    LDR      r1, =myCoreNum\n\t"\r
69                  "    STR      r0, [r1]\n\t"\r
70                  "    pop    {r0-r2}\n\t");\r
71 }\r
72 #endif\r
73 \r
74 uint16_t determineProcId(void);\r
75 \r
76 int8_t*  getGlobalAddr(int8_t* addr);\r
77 \r
78 uint16_t isGblConfigRequired(uint32_t dspNum);\r
79 \r
80 uint16_t determineProcId(void)\r
81 {\r
82     uint16_t regionNo = (uint16_t)numEdma3Instances;\r
83 #ifdef BUILD_TDA2XX_DSP\r
84     extern __cregister volatile uint32_t DNUM;\r
85 #endif\r
86 \r
87     myCoreNum = (int32_t)numDsps;\r
88 \r
89 #ifdef BUILD_TDA2XX_MPU\r
90     readProcFeatureReg();\r
91 /* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */\r
92         regionNo = 0U;\r
93     if(((uint32_t)myCoreNum & 0x03U) == 1U)\r
94     {\r
95         regionNo = 1U;\r
96     }\r
97 #elif defined(BUILD_TDA2XX_IPU)\r
98     myCoreNum = (*(volatile uint32_t *)(PID0_ADDRESS));\r
99     if(Core_getIpuId() == 1U){\r
100         if(myCoreNum == (int32_t)CORE_ID_C0)\r
101         {\r
102             regionNo = 4U;\r
103         }\r
104         else if (myCoreNum == (int32_t)CORE_ID_C1)\r
105         {\r
106             regionNo = 5U;\r
107         }\r
108         else\r
109         {\r
110             /* Nothing to be done here*/\r
111         }\r
112     }\r
113     if(Core_getIpuId() == 2U){\r
114         if(myCoreNum == (int32_t)CORE_ID_C0)\r
115         {\r
116             regionNo = 6U;\r
117         }\r
118         else if (myCoreNum == (int32_t)CORE_ID_C1)\r
119         {\r
120             regionNo = 7U;\r
121         }\r
122         else\r
123         {\r
124             /* Nothing to be done here*/\r
125         }\r
126     }\r
127 #elif defined(BUILD_TDA2XX_DSP)\r
128 \r
129         myCoreNum = (int32_t)DNUM;\r
130         if(myCoreNum == 0)\r
131     {\r
132                 regionNo = 2U;\r
133     }\r
134         else\r
135     {\r
136                 regionNo = 3U;\r
137     }\r
138 #elif defined(BUILD_TDA2XX_EVE)\r
139     regionNo = 1U;\r
140 #endif\r
141         return regionNo;\r
142 }\r
143 \r
144 int8_t*  getGlobalAddr(int8_t* addr)\r
145 {\r
146      return (addr); /* The address is already a global address */\r
147 }\r
148 uint16_t isGblConfigRequired(uint32_t dspNum)\r
149 {\r
150     (void) dspNum;\r
151         return 1U;\r
152 }\r
153 \r
154 /* Semaphore handles */\r
155 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
156 \r
157 /** Number of PaRAM Sets available                                            */\r
158 #define EDMA3_NUM_PARAMSET                              (512U)\r
159 \r
160 /** Number of TCCS available                                                  */\r
161 #define EDMA3_NUM_TCC                                   (64U)\r
162 \r
163 /** Number of DMA Channels available                                          */\r
164 #define EDMA3_NUM_DMA_CHANNELS                          (64U)\r
165 \r
166 /** Number of QDMA Channels available                                         */\r
167 #define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
168 \r
169 /** Number of Event Queues available                                          */\r
170 #define EDMA3_NUM_EVTQUE                                (4U)\r
171 \r
172 /** Number of Transfer Controllers available                                  */\r
173 #define EDMA3_NUM_TC                                    (2U)\r
174 \r
175 /** Number of Regions                                                         */\r
176 #define EDMA3_NUM_REGIONS                               (8U)\r
177 \r
178 /* EDMA3 configuaration for EVE */\r
179 \r
180 /** Number of PaRAM Sets available                                            */\r
181 #define EDMA3_NUM_PARAMSET_EVE                          (64U)\r
182 \r
183 /** Number of TCCS available                                                  */\r
184 #define EDMA3_NUM_TCC_EVE                               (16U)\r
185 \r
186 /** Number of DMA Channels available                                          */\r
187 #define EDMA3_NUM_DMA_CHANNELS_EVE                      (16U)\r
188 \r
189 /** Number of QDMA Channels available                                         */\r
190 #define EDMA3_NUM_QDMA_CHANNELS_EVE                     (8U)\r
191 \r
192 /** Number of Event Queues available                                          */\r
193 #define EDMA3_NUM_EVTQUE_EVE                            (2U)\r
194 \r
195 /** Number of Transfer Controllers available                                  */\r
196 #define EDMA3_NUM_TC_EVE                                (2U)\r
197 \r
198 /** Number of Regions                                                         */\r
199 #define EDMA3_NUM_REGIONS_EVE                           (8U)\r
200 \r
201 \r
202 /** Interrupt no. for Transfer Completion */\r
203 #define EDMA3_CC_XFER_COMPLETION_INT_A15                (66U)\r
204 #define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38U)\r
205 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34U)\r
206 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33U)\r
207 #define EDMA3_CC_XFER_COMPLETION_INT_EVE                (8U)\r
208 \r
209 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
210 #define COMPLETION_INT_A15_XBAR_INST_NO                 (29U)\r
211 #define COMPLETION_INT_DSP_XBAR_INST_NO                 (7U)\r
212 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12U)\r
213 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11U)\r
214 \r
215 /** Interrupt no. for CC Error */\r
216 #define EDMA3_CC_ERROR_INT_A15                          (67U)\r
217 #define EDMA3_CC_ERROR_INT_DSP                          (39U)\r
218 #define EDMA3_CC_ERROR_INT_IPU                          (35U)\r
219 #define EDMA3_CC_ERROR_INT_EVE                          (23U)\r
220 \r
221 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
222 #define CC_ERROR_INT_A15_XBAR_INST_NO                   (30U)\r
223 #define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8U)\r
224 #define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13U)\r
225 \r
226 /** Interrupt no. for TCs Error */\r
227 #define EDMA3_TC0_ERROR_INT_A15                         (68U)\r
228 #define EDMA3_TC0_ERROR_INT_DSP                         (40U)\r
229 #define EDMA3_TC0_ERROR_INT_IPU                         (36U)\r
230 #define EDMA3_TC0_ERROR_INT_EVE                         (24U)\r
231 #define EDMA3_TC1_ERROR_INT_A15                         (69U)\r
232 #define EDMA3_TC1_ERROR_INT_DSP                         (41U)\r
233 #define EDMA3_TC1_ERROR_INT_IPU                         (37U)\r
234 #define EDMA3_TC1_ERROR_INT_EVE                         (25U)\r
235 \r
236 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
237 #define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31U)\r
238 #define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9U) \r
239 #define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14U)\r
240 #define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32U)\r
241 #define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10U)\r
242 #define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)\r
243 \r
244 #ifdef BUILD_TDA2XX_MPU\r
245 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A15)\r
246 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_A15)\r
247 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_A15_XBAR_INST_NO)\r
248 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_A15)\r
249 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_A15)\r
250 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
251 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
252 \r
253 #elif defined BUILD_TDA2XX_DSP\r
254 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_DSP)\r
255 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_DSP)\r
256 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_DSP_XBAR_INST_NO)\r
257 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_DSP)\r
258 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_DSP)\r
259 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_DSP_XBAR_INST_NO)\r
260 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_DSP_XBAR_INST_NO)\r
261 \r
262 #elif defined BUILD_TDA2XX_IPU\r
263 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)\r
264 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_IPU)\r
265 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_IPU_XBAR_INST_NO)\r
266 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_IPU)\r
267 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_IPU)\r
268 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_IPU_XBAR_INST_NO)\r
269 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_IPU_XBAR_INST_NO)\r
270 \r
271 #elif defined BUILD_TDA2XX_EVE\r
272 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_EVE)\r
273 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_EVE)\r
274 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_EVE)\r
275 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_EVE)\r
276 /* For accessing EVE internal edma, there is no need to configure Xbar */\r
277 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
278 #define TC0_ERROR_INT_XBAR_INST_NO                      (0U)\r
279 #define TC1_ERROR_INT_XBAR_INST_NO                      (0U)\r
280 \r
281 #else\r
282 #define EDMA3_CC_XFER_COMPLETION_INT                    (0U)\r
283 #define EDMA3_CC_ERROR_INT                              (0U)\r
284 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
285 #define EDMA3_TC0_ERROR_INT                             (0U)\r
286 #define EDMA3_TC1_ERROR_INT                             (0U)\r
287 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
288 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
289 #endif\r
290 \r
291 #define EDMA3_TC2_ERROR_INT                             (0U)\r
292 #define EDMA3_TC3_ERROR_INT                             (0U)\r
293 #define EDMA3_TC4_ERROR_INT                             (0U)\r
294 #define EDMA3_TC5_ERROR_INT                             (0U)\r
295 #define EDMA3_TC6_ERROR_INT                             (0U)\r
296 #define EDMA3_TC7_ERROR_INT                             (0U)\r
297 \r
298 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19U)\r
299 #define DSP2_EDMA3_CC_XFER_COMPLETION_INT               (20U)\r
300 #define DSP1_EDMA3_CC_ERROR_INT                         (27U)\r
301 #define DSP1_EDMA3_TC0_ERROR_INT                        (28U)\r
302 #define DSP1_EDMA3_TC1_ERROR_INT                        (29U)\r
303 \r
304 /** XBAR interrupt source index numbers for EDMA interrupts */\r
305 #define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)\r
306 #define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)\r
307 #define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)\r
308 #define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)\r
309 #define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)\r
310 #define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)\r
311 #define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)\r
312 #define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)\r
313 \r
314 #define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)\r
315 #define XBAR_EDMA_TC0_IRQ_ERR                           (370U)\r
316 #define XBAR_EDMA_TC1_IRQ_ERR                           (371U)\r
317 \r
318 /**\r
319  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
320  * ECM events (SoC specific). These ECM events come\r
321  * under ECM block XXX (handling those specific ECM events). Normally, block\r
322  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
323  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
324  * is mapped to a specific HWI_INT YYY in the tcf file.\r
325  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
326  * to transfer completion interrupt.\r
327  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
328  * to CC error interrupts.\r
329  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
330  * to TC error interrupts.\r
331  */\r
332 /* EDMA 0 */\r
333 \r
334 #define EDMA3_HWI_INT_XFER_COMP                           (7U)\r
335 #define EDMA3_HWI_INT_CC_ERR                              (7U)\r
336 #define EDMA3_HWI_INT_TC0_ERR                             (10U)\r
337 #define EDMA3_HWI_INT_TC1_ERR                             (10U)\r
338 #define EDMA3_HWI_INT_TC2_ERR                             (10U)\r
339 #define EDMA3_HWI_INT_TC3_ERR                             (10U)\r
340 \r
341 /**\r
342  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
343  * various peripherals, which use EDMA for data transfer.\r
344  * All channels need not be mapped, some can be free also.\r
345  * 1: Mapped\r
346  * 0: Not mapped (channel available)\r
347  *\r
348  * This mapping will be used to allocate DMA channels when user passes\r
349  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
350  * copy). The same mapping is used to allocate the TCC when user passes\r
351  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
352  * \r
353  * For Vayu Since the xbar can be used to map event to any EDMA channel,\r
354  * If the application is assigning events to other channel this variable \r
355  * should be modified\r
356  *\r
357  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
358  */\r
359                                                       /* 31     0 */\r
360 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06EU)  /* TBD */\r
361 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */\r
362 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA        (0x00000000U)  /* TBD */\r
363 \r
364 /**\r
365  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
366  * various peripherals, which use EDMA for data transfer.\r
367  * All channels need not be mapped, some can be free also.\r
368  * 1: Mapped\r
369  * 0: Not mapped (channel available)\r
370  *\r
371  * This mapping will be used to allocate DMA channels when user passes\r
372  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
373  * copy). The same mapping is used to allocate the TCC when user passes\r
374  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
375  *\r
376  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
377  */\r
378 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCU) /* TBD */\r
379 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */\r
380 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA        (0x00000000U) /* TBD */\r
381 \r
382 \r
383 /* Variable which will be used internally for referring number of Event Queues*/\r
384 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
385                                                         EDMA3_NUM_EVTQUE,\r
386                                                         EDMA3_NUM_EVTQUE,\r
387                                                         EDMA3_NUM_EVTQUE\r
388                                                     };\r
389 \r
390 /* Variable which will be used internally for referring number of TCs.        */\r
391 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
392                                                     EDMA3_NUM_TC,\r
393                                                     EDMA3_NUM_TC,\r
394                                                     EDMA3_NUM_TC\r
395                                                 };\r
396 \r
397 /**\r
398  * Variable which will be used internally for referring transfer completion\r
399  * interrupt.\r
400  */\r
401 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
402 {\r
403     /* EDMA3 INSTANCE# 0 */\r
404     {\r
405         EDMA3_CC_XFER_COMPLETION_INT_A15,\r
406         EDMA3_CC_XFER_COMPLETION_INT_A15,\r
407                 EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
408         EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
409                 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
410         EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
411         EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
412         EDMA3_CC_XFER_COMPLETION_INT_IPU_C1\r
413     },\r
414     /* EDMA3 INSTANCE# 1 */\r
415     {\r
416         0U,\r
417         0U,\r
418         DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
419         DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
420         0U,\r
421         0U,\r
422         0U,\r
423         0U\r
424     },\r
425     /* EDMA3 INSTANCE# 2 */\r
426     {\r
427         0U,\r
428         /* Region 1 (Associated to EVE core)*/\r
429         EDMA3_CC_XFER_COMPLETION_INT_EVE,\r
430         0U,\r
431         0U,\r
432         0U,\r
433         0U,\r
434         0U,\r
435         0U,\r
436     }\r
437 };\r
438 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
439 uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
440 {\r
441     /* EDMA3 INSTANCE# 0 */\r
442     {\r
443         COMPLETION_INT_A15_XBAR_INST_NO,\r
444         COMPLETION_INT_A15_XBAR_INST_NO,\r
445                 COMPLETION_INT_DSP_XBAR_INST_NO,\r
446         COMPLETION_INT_DSP_XBAR_INST_NO,\r
447                 COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
448         COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
449         COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
450         COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
451     },\r
452     /* EDMA3 INSTANCE# 1 */\r
453     {\r
454         0U,\r
455         0U,\r
456         0U,\r
457         0U,\r
458         0U,\r
459         0U,\r
460         0U,\r
461         0U\r
462     },\r
463     /* EDMA3 INSTANCE# 2 */\r
464     {\r
465      /* \r
466       * For accessing EVE internal edma,\r
467       * there is no need to configure Xbar.\r
468       * So getting to zero.\r
469       */\r
470         0U,\r
471         0U,\r
472         0U,\r
473         0U,\r
474         0U,\r
475         0U,\r
476         0U,\r
477         0U\r
478     }\r
479 };\r
480 \r
481 /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
482 uint32_t ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
483 {\r
484     /* EDMA3 INSTANCE# 0 */\r
485         {\r
486                 XBAR_EDMA_TPCC_IRQ_REGION0,\r
487         XBAR_EDMA_TPCC_IRQ_REGION1,\r
488         XBAR_EDMA_TPCC_IRQ_REGION2,\r
489         XBAR_EDMA_TPCC_IRQ_REGION3,\r
490                 XBAR_EDMA_TPCC_IRQ_REGION4,\r
491         XBAR_EDMA_TPCC_IRQ_REGION5,\r
492         XBAR_EDMA_TPCC_IRQ_REGION6,\r
493         XBAR_EDMA_TPCC_IRQ_REGION7\r
494         },\r
495     /* EDMA3 INSTANCE# 1 */\r
496     {\r
497                 XBAR_EDMA_TPCC_IRQ_REGION0,\r
498         XBAR_EDMA_TPCC_IRQ_REGION1,\r
499         XBAR_EDMA_TPCC_IRQ_REGION2,\r
500         XBAR_EDMA_TPCC_IRQ_REGION3,\r
501                 XBAR_EDMA_TPCC_IRQ_REGION4,\r
502         XBAR_EDMA_TPCC_IRQ_REGION5,\r
503         XBAR_EDMA_TPCC_IRQ_REGION6,\r
504         XBAR_EDMA_TPCC_IRQ_REGION7\r
505         },\r
506     /* EDMA3 INSTANCE# 2 */\r
507     {\r
508      /* \r
509       * For accessing EVE internal edma,\r
510       * there is no need to configure Xbar.\r
511       * So getting to zero.\r
512       */\r
513                 0U,\r
514         0U,\r
515         0U,\r
516         0U,\r
517                 0U,\r
518         0U,\r
519         0U,\r
520         0U\r
521         }\r
522 };\r
523 \r
524 /**\r
525  * Variable which will be used internally for referring channel controller's\r
526  * error interrupt.\r
527  */\r
528 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = \r
529 {\r
530     EDMA3_CC_ERROR_INT,\r
531     DSP1_EDMA3_CC_ERROR_INT,\r
532     EDMA3_CC_ERROR_INT\r
533 };\r
534 uint32_t ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =\r
535 {\r
536     CC_ERROR_INT_XBAR_INST_NO,\r
537     CC_ERROR_INT_XBAR_INST_NO,\r
538     CC_ERROR_INT_XBAR_INST_NO\r
539 };\r
540 uint32_t ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
541 {\r
542         XBAR_EDMA_TPCC_IRQ_ERR,\r
543     XBAR_EDMA_TPCC_IRQ_ERR,\r
544     XBAR_EDMA_TPCC_IRQ_ERR\r
545 };\r
546 \r
547 /**\r
548  * Variable which will be used internally for referring transfer controllers'\r
549  * error interrupts.\r
550  */\r
551 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
552 {\r
553     /* EDMA3 INSTANCE# 0 */\r
554     {\r
555         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
556         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
557         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
558         EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
559     },\r
560     /* EDMA3 INSTANCE# 1 */\r
561     {\r
562         DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
563         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
564         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
565         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
566     },\r
567     /* EDMA3 INSTANCE# 2 */\r
568     {\r
569         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
570         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
571         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
572         EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
573     }\r
574 };\r
575 uint32_t tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
576 {\r
577     /* EDMA3 INSTANCE# 0 */\r
578     {\r
579        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
580        0U, 0U,\r
581        0U, 0U,\r
582        0U, 0U,\r
583     },\r
584     /* EDMA3 INSTANCE# 1 */\r
585     {\r
586        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
587        0U, 0U,\r
588        0U, 0U,\r
589        0U, 0U,\r
590     },\r
591     /* EDMA3 INSTANCE# 2 */\r
592     {\r
593        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
594        0U, 0U,\r
595        0U, 0U,\r
596        0U, 0U,\r
597     }\r
598 };\r
599 \r
600 uint32_t tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
601 {\r
602     /* EDMA3 INSTANCE# 0 */\r
603     {\r
604        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
605        0U, 0U,\r
606        0U, 0U, 0U, 0U,\r
607     },\r
608     /* EDMA3 INSTANCE# 1 */\r
609     {\r
610        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
611        0U, 0U,\r
612        0U, 0U, 0U, 0U,\r
613     },\r
614     /* EDMA3 INSTANCE# 2 */\r
615     {\r
616        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
617        0U, 0U,\r
618        0U, 0U, 0U, 0U,\r
619     }\r
620 };\r
621 \r
622 \r
623 /**\r
624  * Variables which will be used internally for referring the hardware interrupt\r
625  * for various EDMA3 interrupts.\r
626  */\r
627 uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
628 {\r
629     EDMA3_HWI_INT_XFER_COMP,\r
630     EDMA3_HWI_INT_XFER_COMP,\r
631     EDMA3_CC_XFER_COMPLETION_INT\r
632 };\r
633 \r
634 uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
635 {\r
636     EDMA3_HWI_INT_CC_ERR,\r
637     EDMA3_HWI_INT_CC_ERR,\r
638     EDMA3_CC_ERROR_INT\r
639 };\r
640 \r
641 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
642 {\r
643     /* EDMA3 INSTANCE# 0 */\r
644     {\r
645          EDMA3_HWI_INT_TC0_ERR ,\r
646          EDMA3_HWI_INT_TC1_ERR ,\r
647          EDMA3_HWI_INT_TC2_ERR ,\r
648          EDMA3_HWI_INT_TC3_ERR ,\r
649          0U ,\r
650          0U ,\r
651          0U ,\r
652          0U \r
653     },\r
654     /* EDMA3 INSTANCE# 1 */\r
655     {\r
656          EDMA3_HWI_INT_TC0_ERR ,\r
657          EDMA3_HWI_INT_TC1_ERR ,\r
658          EDMA3_HWI_INT_TC2_ERR ,\r
659          EDMA3_HWI_INT_TC3_ERR ,\r
660          0U ,\r
661          0U ,\r
662          0U ,\r
663          0U \r
664     },\r
665     /* EDMA3 INSTANCE# 2 */\r
666     {\r
667          EDMA3_TC0_ERROR_INT ,\r
668          EDMA3_TC1_ERROR_INT ,\r
669          EDMA3_TC2_ERROR_INT ,\r
670          EDMA3_TC3_ERROR_INT ,\r
671          0U ,\r
672          0U ,\r
673          0U ,\r
674          0U \r
675     }\r
676 };\r
677 \r
678 /**\r
679  * \brief Base address as seen from the different cores may be different\r
680  * And is defined based on the core\r
681  */\r
682 #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
683 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
684 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
685 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
686 #elif (defined BUILD_TDA2XX_IPU)\r
687 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))\r
688 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))\r
689 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))\r
690 #elif (defined BUILD_TDA2XX_EVE)\r
691 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x400A0000))\r
692 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x40086000))\r
693 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x40087000))\r
694 #else\r
695 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))\r
696 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))\r
697 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))\r
698 #endif\r
699 \r
700 #define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))\r
701 #define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))\r
702 #define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))\r
703 \r
704 /* Driver Object Initialization Configuration */\r
705 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
706 {\r
707     {\r
708         /* EDMA3 INSTANCE# 0 */\r
709         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
710         EDMA3_NUM_DMA_CHANNELS,\r
711         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
712         EDMA3_NUM_QDMA_CHANNELS,\r
713         /** Total number of TCCs supported by the EDMA3 Controller            */\r
714         EDMA3_NUM_TCC,\r
715         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
716         EDMA3_NUM_PARAMSET,\r
717         /** Total number of Event Queues in the EDMA3 Controller              */\r
718         EDMA3_NUM_EVTQUE,\r
719         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
720         EDMA3_NUM_TC,\r
721         /** Number of Regions on this EDMA3 controller                        */\r
722         EDMA3_NUM_REGIONS,\r
723 \r
724         /**\r
725          * \brief Channel mapping existence\r
726          * A value of 0 (No channel mapping) implies that there is fixed association\r
727          * for a channel number to a parameter entry number or, in other words,\r
728          * PaRAM entry n corresponds to channel n.\r
729          */\r
730         1U,\r
731 \r
732         /** Existence of memory protection feature */\r
733         0U,\r
734 \r
735         /** Global Register Region of CC Registers */\r
736         EDMA3_CC_BASE_ADDR,\r
737         /** Transfer Controller (TC) Registers */\r
738         {\r
739                 EDMA3_TC0_BASE_ADDR,\r
740                 EDMA3_TC1_BASE_ADDR,\r
741                 (void *)NULL,\r
742                 (void *)NULL,\r
743             (void *)NULL,\r
744             (void *)NULL,\r
745             (void *)NULL,\r
746             (void *)NULL\r
747         },\r
748         /** Interrupt no. for Transfer Completion */\r
749         EDMA3_CC_XFER_COMPLETION_INT,\r
750         /** Interrupt no. for CC Error */\r
751         EDMA3_CC_ERROR_INT,\r
752         /** Interrupt no. for TCs Error */\r
753         {\r
754             EDMA3_TC0_ERROR_INT,\r
755             EDMA3_TC1_ERROR_INT,\r
756             EDMA3_TC2_ERROR_INT,\r
757             EDMA3_TC3_ERROR_INT,\r
758             EDMA3_TC4_ERROR_INT,\r
759             EDMA3_TC5_ERROR_INT,\r
760             EDMA3_TC6_ERROR_INT,\r
761             EDMA3_TC7_ERROR_INT\r
762         },\r
763 \r
764         /**\r
765          * \brief EDMA3 TC priority setting\r
766          *\r
767          * User can program the priority of the Event Queues\r
768          * at a system-wide level.  This means that the user can set the\r
769          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
770          * relative to IO initiated by the other bus masters on the\r
771          * device (ARM, DSP, USB, etc)\r
772          */\r
773         {\r
774             0U,\r
775             1U,\r
776             0U,\r
777             0U,\r
778             0U,\r
779             0U,\r
780             0U,\r
781             0U\r
782         },\r
783         /**\r
784          * \brief To Configure the Threshold level of number of events\r
785          * that can be queued up in the Event queues. EDMA3CC error register\r
786          * (CCERR) will indicate whether or not at any instant of time the\r
787          * number of events queued up in any of the event queues exceeds\r
788          * or equals the threshold/watermark value that is set\r
789          * in the queue watermark threshold register (QWMTHRA).\r
790          */\r
791         {\r
792             16U,\r
793             16U,\r
794             0U,\r
795             0U,\r
796             0U,\r
797             0U,\r
798             0U,\r
799             0U\r
800         },\r
801 \r
802         /**\r
803          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
804          * An optimally-sized command is defined by the transfer controller\r
805          * default burst size (DBS). Different TCs can have different\r
806          * DBS values. It is defined in Bytes.\r
807          */\r
808             {\r
809             16U,\r
810             16U,\r
811             0U,\r
812             0U,\r
813             0U,\r
814             0U,\r
815             0U,\r
816             0U\r
817             },\r
818 \r
819         /**\r
820          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
821          * if it exists, otherwise of no use.\r
822          */\r
823             {\r
824                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
825                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
826                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
827                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
828                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
829                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
830                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
831                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
832                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
833                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
834                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
835                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
836                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
837                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
838                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
839                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
840                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
841                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
842                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
843                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
844                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
845                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
846                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
847                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
848                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
849                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
850                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
851                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
852                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
853                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
854                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
855                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
856                         },\r
857 \r
858          /**\r
859           * \brief Mapping from each DMA channel to a TCC. This specific\r
860           * TCC code will be returned when the transfer is completed\r
861           * on the mapped channel.\r
862           */\r
863             {\r
864                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
865                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
866                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
867                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
868                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
869                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
870                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
871                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
872                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
873                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
874                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
875                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
876                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
877                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
878                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
879                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
880             },\r
881 \r
882         /**\r
883          * \brief Mapping of DMA channels to Hardware Events from\r
884          * various peripherals, which use EDMA for data transfer.\r
885          * All channels need not be mapped, some can be free also.\r
886          */\r
887             {\r
888             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,\r
889             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA\r
890             }\r
891         },\r
892     {\r
893         /* EDMA3 INSTANCE# 1 */\r
894         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
895         EDMA3_NUM_DMA_CHANNELS,\r
896         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
897         EDMA3_NUM_QDMA_CHANNELS,\r
898         /** Total number of TCCs supported by the EDMA3 Controller            */\r
899         EDMA3_NUM_TCC,\r
900         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
901         EDMA3_NUM_PARAMSET,\r
902         /** Total number of Event Queues in the EDMA3 Controller              */\r
903         EDMA3_NUM_EVTQUE,\r
904         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
905         EDMA3_NUM_TC,\r
906         /** Number of Regions on this EDMA3 controller                        */\r
907         EDMA3_NUM_REGIONS,\r
908 \r
909         /**\r
910          * \brief Channel mapping existence\r
911          * A value of 0 (No channel mapping) implies that there is fixed association\r
912          * for a channel number to a parameter entry number or, in other words,\r
913          * PaRAM entry n corresponds to channel n.\r
914          */\r
915         1U,\r
916 \r
917         /** Existence of memory protection feature */\r
918         0U,\r
919 \r
920         /** Global Register Region of CC Registers */\r
921         DSP1_EDMA3_CC_BASE_ADDR,\r
922         /** Transfer Controller (TC) Registers */\r
923         {\r
924                 DSP1_EDMA3_TC0_BASE_ADDR,\r
925                 DSP1_EDMA3_TC1_BASE_ADDR,\r
926                 (void *)NULL,\r
927                 (void *)NULL,\r
928             (void *)NULL,\r
929             (void *)NULL,\r
930             (void *)NULL,\r
931             (void *)NULL\r
932         },\r
933         /** Interrupt no. for Transfer Completion */\r
934         DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
935         /** Interrupt no. for CC Error */\r
936         DSP1_EDMA3_CC_ERROR_INT,\r
937         /** Interrupt no. for TCs Error */\r
938         {\r
939             DSP1_EDMA3_TC0_ERROR_INT,\r
940             DSP1_EDMA3_TC1_ERROR_INT,\r
941             EDMA3_TC2_ERROR_INT,\r
942             EDMA3_TC3_ERROR_INT,\r
943             EDMA3_TC4_ERROR_INT,\r
944             EDMA3_TC5_ERROR_INT,\r
945             EDMA3_TC6_ERROR_INT,\r
946             EDMA3_TC7_ERROR_INT\r
947         },\r
948 \r
949         /**\r
950          * \brief EDMA3 TC priority setting\r
951          *\r
952          * User can program the priority of the Event Queues\r
953          * at a system-wide level.  This means that the user can set the\r
954          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
955          * relative to IO initiated by the other bus masters on the\r
956          * device (ARM, DSP, USB, etc)\r
957          */\r
958         {\r
959             0U,\r
960             1U,\r
961             0U,\r
962             0U,\r
963             0U,\r
964             0U,\r
965             0U,\r
966             0U\r
967         },\r
968         /**\r
969          * \brief To Configure the Threshold level of number of events\r
970          * that can be queued up in the Event queues. EDMA3CC error register\r
971          * (CCERR) will indicate whether or not at any instant of time the\r
972          * number of events queued up in any of the event queues exceeds\r
973          * or equals the threshold/watermark value that is set\r
974          * in the queue watermark threshold register (QWMTHRA).\r
975          */\r
976         {\r
977             16U,\r
978             16U,\r
979             0U,\r
980             0U,\r
981             0U,\r
982             0U,\r
983             0U,\r
984             0U\r
985         },\r
986 \r
987         /**\r
988          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
989          * An optimally-sized command is defined by the transfer controller\r
990          * default burst size (DBS). Different TCs can have different\r
991          * DBS values. It is defined in Bytes.\r
992          */\r
993             {\r
994             16U,\r
995             16U,\r
996             0U,\r
997             0U,\r
998             0U,\r
999             0U,\r
1000             0U,\r
1001             0U\r
1002             },\r
1003 \r
1004         /**\r
1005          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
1006          * if it exists, otherwise of no use.\r
1007          */\r
1008             {\r
1009                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1010                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1011                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1012                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1013                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1014                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1015                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1016                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1017                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1018                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1019                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1020                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1021                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1022                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1023                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1024                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1025                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1026                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1027                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1028                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1029                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1030                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1031                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1032                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1033                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1034                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1035                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1036                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1037                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1038                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1039                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1040                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
1041             },\r
1042 \r
1043          /**\r
1044           * \brief Mapping from each DMA channel to a TCC. This specific\r
1045           * TCC code will be returned when the transfer is completed\r
1046           * on the mapped channel.\r
1047           */\r
1048             {\r
1049                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1050                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1051                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1052                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1053                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1054                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1055                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1056                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1057                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1058                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1059                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1060                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1061                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1062                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1063                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1064                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1065             },\r
1066 \r
1067         /**\r
1068          * \brief Mapping of DMA channels to Hardware Events from\r
1069          * various peripherals, which use EDMA for data transfer.\r
1070          * All channels need not be mapped, some can be free also.\r
1071          */\r
1072             {\r
1073             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
1074             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
1075             }\r
1076     },\r
1077     {\r
1078         /* EDMA3 INSTANCE# 2 */\r
1079         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
1080         EDMA3_NUM_DMA_CHANNELS_EVE,\r
1081         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
1082         EDMA3_NUM_QDMA_CHANNELS_EVE,\r
1083         /** Total number of TCCs supported by the EDMA3 Controller            */\r
1084         EDMA3_NUM_TCC_EVE,\r
1085         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
1086         EDMA3_NUM_PARAMSET_EVE,\r
1087         /** Total number of Event Queues in the EDMA3 Controller              */\r
1088         EDMA3_NUM_EVTQUE_EVE,\r
1089         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
1090         EDMA3_NUM_TC_EVE,\r
1091         /** Number of Regions on this EDMA3 controller                        */\r
1092         EDMA3_NUM_REGIONS_EVE,\r
1093 \r
1094         /**\r
1095          * \brief Channel mapping existence\r
1096          * A value of 0 (No channel mapping) implies that there is fixed association\r
1097          * for a channel number to a parameter entry number or, in other words,\r
1098          * PaRAM entry n corresponds to channel n.\r
1099          */\r
1100         1U,\r
1101 \r
1102         /** Existence of memory protection feature */\r
1103         0U,\r
1104 \r
1105         /** Global Register Region of CC Registers */\r
1106         EDMA3_CC_BASE_ADDR,\r
1107         /** Transfer Controller (TC) Registers */\r
1108         {\r
1109                 EDMA3_TC0_BASE_ADDR,\r
1110                 EDMA3_TC1_BASE_ADDR,\r
1111                 (void *)NULL,\r
1112                 (void *)NULL,\r
1113             (void *)NULL,\r
1114             (void *)NULL,\r
1115             (void *)NULL,\r
1116             (void *)NULL\r
1117         },\r
1118         /** Interrupt no. for Transfer Completion */\r
1119         EDMA3_CC_XFER_COMPLETION_INT,\r
1120         /** Interrupt no. for CC Error */\r
1121         EDMA3_CC_ERROR_INT,\r
1122         /** Interrupt no. for TCs Error */\r
1123         {\r
1124             EDMA3_TC0_ERROR_INT,\r
1125             EDMA3_TC1_ERROR_INT,\r
1126             EDMA3_TC2_ERROR_INT,\r
1127             EDMA3_TC3_ERROR_INT,\r
1128             EDMA3_TC4_ERROR_INT,\r
1129             EDMA3_TC5_ERROR_INT,\r
1130             EDMA3_TC6_ERROR_INT,\r
1131             EDMA3_TC7_ERROR_INT\r
1132         },\r
1133 \r
1134         /**\r
1135          * \brief EDMA3 TC priority setting\r
1136          *\r
1137          * User can program the priority of the Event Queues\r
1138          * at a system-wide level.  This means that the user can set the\r
1139          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
1140          * relative to IO initiated by the other bus masters on the\r
1141          * device (ARM, DSP, USB, etc)\r
1142          */\r
1143         {\r
1144             0U,\r
1145             1U,\r
1146             0U,\r
1147             0U,\r
1148             0U,\r
1149             0U,\r
1150             0U,\r
1151             0U\r
1152         },\r
1153         /**\r
1154          * \brief To Configure the Threshold level of number of events\r
1155          * that can be queued up in the Event queues. EDMA3CC error register\r
1156          * (CCERR) will indicate whether or not at any instant of time the\r
1157          * number of events queued up in any of the event queues exceeds\r
1158          * or equals the threshold/watermark value that is set\r
1159          * in the queue watermark threshold register (QWMTHRA).\r
1160          */\r
1161         {\r
1162             16U,\r
1163             16U,\r
1164             0U,\r
1165             0U,\r
1166             0U,\r
1167             0U,\r
1168             0U,\r
1169             0U\r
1170         },\r
1171 \r
1172         /**\r
1173          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
1174          * An optimally-sized command is defined by the transfer controller\r
1175          * default burst size (DBS). Different TCs can have different\r
1176          * DBS values. It is defined in Bytes.\r
1177          */\r
1178             {\r
1179             16U,\r
1180             16U,\r
1181             0U,\r
1182             0U,\r
1183             0U,\r
1184             0U,\r
1185             0U,\r
1186             0U\r
1187             },\r
1188 \r
1189         /**\r
1190          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
1191          * if it exists, otherwise of no use.\r
1192          */\r
1193             {\r
1194                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1195                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1196                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1197                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1198                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1199                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1200                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1201                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1202                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1203                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1204                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1205                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1206                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1207                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1208                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1209                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1210                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1211                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1212                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1213                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1214                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1215                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1216                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1217                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1218                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1219                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1220                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1221                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1222                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1223                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1224                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1225                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
1226             },\r
1227 \r
1228          /**\r
1229           * \brief Mapping from each DMA channel to a TCC. This specific\r
1230           * TCC code will be returned when the transfer is completed\r
1231           * on the mapped channel.\r
1232           */\r
1233             {\r
1234                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1235                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1236                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1237                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1238                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1239                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1240                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1241                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1242                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1243                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1244                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1245                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1246                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1247                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1248                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1249                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1250             },\r
1251 \r
1252         /**\r
1253          * \brief Mapping of DMA channels to Hardware Events from\r
1254          * various peripherals, which use EDMA for data transfer.\r
1255          * All channels need not be mapped, some can be free also.\r
1256          */\r
1257             {\r
1258             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,\r
1259             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA\r
1260             }\r
1261     },\r
1262 \r
1263 };\r
1264 \r
1265 /**\r
1266  * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
1267  * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
1268  * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
1269  * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
1270  *\r
1271  * Only Resources owned by a perticular core are allocated by Driver\r
1272  * Reserved resources are not allocated if requested for any available resource\r
1273  */\r
1274  \r
1275 /* Driver Instance Initialization Configuration */\r
1276 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
1277     {\r
1278                 /* EDMA3 INSTANCE# 0 */\r
1279                 {\r
1280                         /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
1281                         {\r
1282                                 /* ownPaRAMSets */\r
1283                                 /* 31     0     63    32     95    64     127   96 */\r
1284                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1285                                 /* 159  128     191  160     223  192     255  224 */\r
1286                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1287                                 /* 287  256     319  288     351  320     383  352 */\r
1288                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1289                                 /* 415  384     447  416     479  448     511  480 */\r
1290                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1291 \r
1292                                 /* ownDmaChannels */\r
1293                                 /* 31     0     63    32 */\r
1294                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1295 \r
1296                                 /* ownQdmaChannels */\r
1297                                 /* 31     0 */\r
1298                                 {0x000000FFU},\r
1299 \r
1300                                 /* ownTccs */\r
1301                                 /* 31     0     63    32 */\r
1302                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1303 \r
1304                                 /* resvdPaRAMSets */\r
1305                                 /* 31     0     63    32     95    64     127   96 */\r
1306                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1307                                 /* 159  128     191  160     223  192     255  224 */\r
1308                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1309                                 /* 287  256     319  288     351  320     383  352 */\r
1310                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1311                                 /* 415  384     447  416     479  448     511  480 */\r
1312                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1313 \r
1314                                 /* resvdDmaChannels */\r
1315                                 /* 31     0     63    32 */\r
1316                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1317 \r
1318                                 /* resvdQdmaChannels */\r
1319                                 /* 31     0 */\r
1320                                 {0x00U},\r
1321 \r
1322                                 /* resvdTccs */\r
1323                                 /* 31     0     63    32 */\r
1324                                 {0x00U, 0x00U},\r
1325                         },\r
1326 \r
1327                         /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
1328                         {\r
1329                                 /* ownPaRAMSets */\r
1330                                 /* 31     0     63    32     95    64     127   96 */\r
1331                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1332                                 /* 159  128     191  160     223  192     255  224 */\r
1333                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1334                                 /* 287  256     319  288     351  320     383  352 */\r
1335                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1336                                 /* 415  384     447  416     479  448     511  480 */\r
1337                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1338 /* \r
1339  * This instance 0 and region 1 is only accessible to MPU core 1.\r
1340  * So other cores should not be access.\r
1341  */\r
1342 #ifdef BUILD_TDA2XX_MPU\r
1343                                 /* ownDmaChannels */\r
1344                                 /* 31     0     63    32 */\r
1345                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1346 #else\r
1347                                 /* ownDmaChannels */\r
1348                                 /* 31     0     63    32 */\r
1349                                 {0x00000000U, 0x00000000U},\r
1350 #endif\r
1351                                 /* ownQdmaChannels */\r
1352                                 /* 31     0 */\r
1353                                 {0x000000FFU},\r
1354 \r
1355                                 /* ownTccs */\r
1356                                 /* 31     0     63    32 */\r
1357                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1358 \r
1359                                 /* resvdPaRAMSets */\r
1360                                 /* 31     0     63    32     95    64     127   96 */\r
1361                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1362                                 /* 159  128     191  160     223  192     255  224 */\r
1363                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1364                                 /* 287  256     319  288     351  320     383  352 */\r
1365                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1366                                 /* 415  384     447  416     479  448     511  480 */\r
1367                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1368 \r
1369                                 /* resvdDmaChannels */\r
1370                                 /* 31     0     63    32 */\r
1371                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1372 \r
1373                                 /* resvdQdmaChannels */\r
1374                                 /* 31     0 */\r
1375                                 {0x00U},\r
1376 \r
1377                                 /* resvdTccs */\r
1378                                 /* 31     0     63    32 */\r
1379                                 {0x00U, 0x00U},\r
1380                         },\r
1381 \r
1382                 /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
1383                         {\r
1384                                 /* ownPaRAMSets */\r
1385                                 /* 31     0     63    32     95    64     127   96 */\r
1386                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1387                                 /* 159  128     191  160     223  192     255  224 */\r
1388                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1389                                 /* 287  256     319  288     351  320     383  352 */\r
1390                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1391                                 /* 415  384     447  416     479  448     511  480 */\r
1392                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1393 \r
1394                                 /* ownDmaChannels */\r
1395                                 /* 31     0     63    32 */\r
1396                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1397 \r
1398                                 /* ownQdmaChannels */\r
1399                                 /* 31     0 */\r
1400                                 {0x000000FFU},\r
1401 \r
1402                                 /* ownTccs */\r
1403                                 /* 31     0     63    32 */\r
1404                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1405 \r
1406                                 /* resvdPaRAMSets */\r
1407                                 /* 31     0     63    32     95    64     127   96 */\r
1408                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1409                                 /* 159  128     191  160     223  192     255  224 */\r
1410                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1411                                 /* 287  256     319  288     351  320     383  352 */\r
1412                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1413                                 /* 415  384     447  416     479  448     511  480 */\r
1414                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1415 \r
1416                                 /* resvdDmaChannels */\r
1417                                 /* 31     0     63    32 */\r
1418                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1419 \r
1420                                 /* resvdQdmaChannels */\r
1421                                 /* 31     0 */\r
1422                                 {0x00U},\r
1423 \r
1424                                 /* resvdTccs */\r
1425                                 /* 31     0     63    32 */\r
1426                                 {0x00U, 0x00U},\r
1427                         },\r
1428 \r
1429                 /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
1430                         {\r
1431                                 /* ownPaRAMSets */\r
1432                                 /* 31     0     63    32     95    64     127   96 */\r
1433                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1434                                 /* 159  128     191  160     223  192     255  224 */\r
1435                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1436                                 /* 287  256     319  288     351  320     383  352 */\r
1437                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1438                                 /* 415  384     447  416     479  448     511  480 */\r
1439                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1440 \r
1441                                 /* ownDmaChannels */\r
1442                                 /* 31     0     63    32 */\r
1443                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1444 \r
1445                                 /* ownQdmaChannels */\r
1446                                 /* 31     0 */\r
1447                                 {0x000000FFU},\r
1448 \r
1449                                 /* ownTccs */\r
1450                                 /* 31     0     63    32 */\r
1451                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1452 \r
1453                                 /* resvdPaRAMSets */\r
1454                                 /* 31     0     63    32     95    64     127   96 */\r
1455                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1456                                 /* 159  128     191  160     223  192     255  224 */\r
1457                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1458                                 /* 287  256     319  288     351  320     383  352 */\r
1459                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1460                                 /* 415  384     447  416     479  448     511  480 */\r
1461                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1462 \r
1463                                 /* resvdDmaChannels */\r
1464                                 /* 31     0     63    32 */\r
1465                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1466 \r
1467                                 /* resvdQdmaChannels */\r
1468                                 /* 31     0 */\r
1469                                 {0x00U},\r
1470 \r
1471                                 /* resvdTccs */\r
1472                                 /* 31     0     63    32 */\r
1473                                 {0x00U, 0x00U},\r
1474                         },\r
1475 \r
1476                 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
1477                         {\r
1478                                 /* ownPaRAMSets */\r
1479                                 /* 31     0     63    32     95    64     127   96 */\r
1480                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1481                                 /* 159  128     191  160     223  192     255  224 */\r
1482                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1483                                 /* 287  256     319  288     351  320     383  352 */\r
1484                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1485                                 /* 415  384     447  416     479  448     511  480 */\r
1486                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1487 \r
1488                                 /* ownDmaChannels */\r
1489                                 /* 31     0     63    32 */\r
1490                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1491 \r
1492                                 /* ownQdmaChannels */\r
1493                                 /* 31     0 */\r
1494                                 {0x000000FFU},\r
1495 \r
1496                                 /* ownTccs */\r
1497                                 /* 31     0     63    32 */\r
1498                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1499 \r
1500                                 /* resvdPaRAMSets */\r
1501                                 /* 31     0     63    32     95    64     127   96 */\r
1502                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1503                                 /* 159  128     191  160     223  192     255  224 */\r
1504                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1505                                 /* 287  256     319  288     351  320     383  352 */\r
1506                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1507                                 /* 415  384     447  416     479  448     511  480 */\r
1508                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1509 \r
1510                                 /* resvdDmaChannels */\r
1511                                 /* 31     0     63    32 */\r
1512                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1513 \r
1514                                 /* resvdQdmaChannels */\r
1515                                 /* 31     0 */\r
1516                                 {0x00U},\r
1517 \r
1518                                 /* resvdTccs */\r
1519                                 /* 31     0     63    32 */\r
1520                                 {0x00U, 0x00U},\r
1521                         },\r
1522 \r
1523                 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
1524                         {\r
1525                                 /* ownPaRAMSets */\r
1526                                 /* 31     0     63    32     95    64     127   96 */\r
1527                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1528                                 /* 159  128     191  160     223  192     255  224 */\r
1529                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1530                                 /* 287  256     319  288     351  320     383  352 */\r
1531                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1532                                 /* 415  384     447  416     479  448     511  480 */\r
1533                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1534 \r
1535                                 /* ownDmaChannels */\r
1536                                 /* 31     0     63    32 */\r
1537                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1538 \r
1539                                 /* ownQdmaChannels */\r
1540                                 /* 31     0 */\r
1541                                 {0x000000FFU},\r
1542 \r
1543                                 /* ownTccs */\r
1544                                 /* 31     0     63    32 */\r
1545                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1546 \r
1547                                 /* resvdPaRAMSets */\r
1548                                 /* 31     0     63    32     95    64     127   96 */\r
1549                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1550                                 /* 159  128     191  160     223  192     255  224 */\r
1551                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1552                                 /* 287  256     319  288     351  320     383  352 */\r
1553                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1554                                 /* 415  384     447  416     479  448     511  480 */\r
1555                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1556 \r
1557                                 /* resvdDmaChannels */\r
1558                                 /* 31     0     63    32 */\r
1559                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1560 \r
1561                                 /* resvdQdmaChannels */\r
1562                                 /* 31     0 */\r
1563                                 {0x00U},\r
1564 \r
1565                                 /* resvdTccs */\r
1566                                 /* 31     0     63    32 */\r
1567                                 {0x00U, 0x00U},\r
1568                         },\r
1569 \r
1570                 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
1571                         {\r
1572                                 /* ownPaRAMSets */\r
1573                                 /* 31     0     63    32     95    64     127   96 */\r
1574                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1575                                 /* 159  128     191  160     223  192     255  224 */\r
1576                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1577                                 /* 287  256     319  288     351  320     383  352 */\r
1578                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1579                                 /* 415  384     447  416     479  448     511  480 */\r
1580                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1581 \r
1582                                 /* ownDmaChannels */\r
1583                                 /* 31     0     63    32 */\r
1584                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1585 \r
1586                                 /* ownQdmaChannels */\r
1587                                 /* 31     0 */\r
1588                                 {0x000000FFU},\r
1589 \r
1590                                 /* ownTccs */\r
1591                                 /* 31     0     63    32 */\r
1592                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1593 \r
1594                                 /* resvdPaRAMSets */\r
1595                                 /* 31     0     63    32     95    64     127   96 */\r
1596                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1597                                 /* 159  128     191  160     223  192     255  224 */\r
1598                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1599                                 /* 287  256     319  288     351  320     383  352 */\r
1600                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1601                                 /* 415  384     447  416     479  448     511  480 */\r
1602                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1603 \r
1604                                 /* resvdDmaChannels */\r
1605                                 /* 31     0     63    32 */\r
1606                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1607 \r
1608                                 /* resvdQdmaChannels */\r
1609                                 /* 31     0 */\r
1610                                 {0x00U},\r
1611 \r
1612                                 /* resvdTccs */\r
1613                                 /* 31     0     63    32 */\r
1614                                 {0x00U, 0x00U},\r
1615                         },\r
1616 \r
1617                 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
1618                         {\r
1619                                 /* ownPaRAMSets */\r
1620                                 /* 31     0     63    32     95    64     127   96 */\r
1621                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1622                                 /* 159  128     191  160     223  192     255  224 */\r
1623                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1624                                 /* 287  256     319  288     351  320     383  352 */\r
1625                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1626                                 /* 415  384     447  416     479  448     511  480 */\r
1627                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1628 \r
1629                                 /* ownDmaChannels */\r
1630                                 /* 31     0     63    32 */\r
1631                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1632 \r
1633                                 /* ownQdmaChannels */\r
1634                                 /* 31     0 */\r
1635                                 {0x000000FFU},\r
1636 \r
1637                                 /* ownTccs */\r
1638                                 /* 31     0     63    32 */\r
1639                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1640 \r
1641                                 /* resvdPaRAMSets */\r
1642                                 /* 31     0     63    32     95    64     127   96 */\r
1643                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1644                                 /* 159  128     191  160     223  192     255  224 */\r
1645                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1646                                 /* 287  256     319  288     351  320     383  352 */\r
1647                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1648                                 /* 415  384     447  416     479  448     511  480 */\r
1649                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1650 \r
1651                                 /* resvdDmaChannels */\r
1652                                 /* 31     0     63    32 */\r
1653                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1654 \r
1655                                 /* resvdQdmaChannels */\r
1656                                 /* 31     0 */\r
1657                                 {0x00U},\r
1658 \r
1659                                 /* resvdTccs */\r
1660                                 /* 31     0     63    32 */\r
1661                                 {0x00U, 0x00U},\r
1662                         },\r
1663             },\r
1664                 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
1665                 {\r
1666                 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1667                         {\r
1668                                 /* ownPaRAMSets */\r
1669                                 /* 31     0     63    32     95    64     127   96 */\r
1670                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1671                                 /* 159  128     191  160     223  192     255  224 */\r
1672                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1673                                 /* 287  256     319  288     351  320     383  352 */\r
1674                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1675                                 /* 415  384     447  416     479  448     511  480 */\r
1676                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1677 \r
1678                                 /* ownDmaChannels */\r
1679                                 /* 31     0     63    32 */\r
1680                                 {0x00000000U, 0x00000000U},\r
1681 \r
1682                                 /* ownQdmaChannels */\r
1683                                 /* 31     0 */\r
1684                                 {0x00000000U},\r
1685 \r
1686                                 /* ownTccs */\r
1687                                 /* 31     0     63    32 */\r
1688                                 {0x00000000U, 0x00000000U},\r
1689 \r
1690                                 /* resvdPaRAMSets */\r
1691                                 /* 31     0     63    32     95    64     127   96 */\r
1692                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1693                                 /* 159  128     191  160     223  192     255  224 */\r
1694                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1695                                 /* 287  256     319  288     351  320     383  352 */\r
1696                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1697                                 /* 415  384     447  416     479  448     511  480 */\r
1698                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1699 \r
1700                                 /* resvdDmaChannels */\r
1701                                 /* 31     0     63    32 */\r
1702                                 {0x00000000U, 0x00000000U},\r
1703 \r
1704                                 /* resvdQdmaChannels */\r
1705                                 /* 31     0 */\r
1706                                 {0x00000000U},\r
1707 \r
1708                                 /* resvdTccs */\r
1709                                 /* 31     0     63    32 */\r
1710                                 {0x00000000U, 0x00000000U},\r
1711                         },\r
1712 \r
1713                         /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
1714                         {\r
1715                                 /* ownPaRAMSets */\r
1716                                 /* 31     0     63    32     95    64     127   96 */\r
1717                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1718                                 /* 159  128     191  160     223  192     255  224 */\r
1719                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1720                                 /* 287  256     319  288     351  320     383  352 */\r
1721                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1722                                 /* 415  384     447  416     479  448     511  480 */\r
1723                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1724 \r
1725                                 /* ownDmaChannels */\r
1726                                 /* 31     0     63    32 */\r
1727                                 {0x00000000U, 0x00000000U},\r
1728 \r
1729                                 /* ownQdmaChannels */\r
1730                                 /* 31     0 */\r
1731                                 {0x00000000U},\r
1732 \r
1733                                 /* ownTccs */\r
1734                                 /* 31     0     63    32 */\r
1735                                 {0x00000000U, 0x00000000U},\r
1736 \r
1737                                 /* resvdPaRAMSets */\r
1738                                 /* 31     0     63    32     95    64     127   96 */\r
1739                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1740                                 /* 159  128     191  160     223  192     255  224 */\r
1741                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1742                                 /* 287  256     319  288     351  320     383  352 */\r
1743                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1744                                 /* 415  384     447  416     479  448     511  480 */\r
1745                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1746 \r
1747                                 /* resvdDmaChannels */\r
1748                                 /* 31     0     63    32 */\r
1749                                 {0x00000000U, 0x00000000U},\r
1750 \r
1751                                 /* resvdQdmaChannels */\r
1752                                 /* 31     0 */\r
1753                                 {0x00000000U},\r
1754 \r
1755                                 /* resvdTccs */\r
1756                                 /* 31     0     63    32 */\r
1757                                 {0x00000000U, 0x00000000U},\r
1758                         },\r
1759 \r
1760                 /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
1761                         {\r
1762                                 /* ownPaRAMSets */\r
1763                                 /* 31     0     63    32     95    64     127   96 */\r
1764                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1765                                 /* 159  128     191  160     223  192     255  224 */\r
1766                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1767                                 /* 287  256     319  288     351  320     383  352 */\r
1768                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1769                                 /* 415  384     447  416     479  448     511  480 */\r
1770                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1771 \r
1772                                 /* ownDmaChannels */\r
1773                                 /* 31     0     63    32 */\r
1774                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1775 \r
1776                                 /* ownQdmaChannels */\r
1777                                 /* 31     0 */\r
1778                                 {0x000000FFU},\r
1779 \r
1780                                 /* ownTccs */\r
1781                                 /* 31     0     63    32 */\r
1782                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1783 \r
1784                                 /* resvdPaRAMSets */\r
1785                                 /* 31     0     63    32     95    64     127   96 */\r
1786                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1787                                 /* 159  128     191  160     223  192     255  224 */\r
1788                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1789                                 /* 287  256     319  288     351  320     383  352 */\r
1790                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1791                                 /* 415  384     447  416     479  448     511  480 */\r
1792                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1793 \r
1794                                 /* resvdDmaChannels */\r
1795                                 /* 31     0     63    32 */\r
1796                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1797 \r
1798                                 /* resvdQdmaChannels */\r
1799                                 /* 31     0 */\r
1800                                 {0x00U},\r
1801 \r
1802                                 /* resvdTccs */\r
1803                                 /* 31     0     63    32 */\r
1804                                 {0x00U, 0x00U},\r
1805                         },\r
1806 \r
1807                 /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
1808                         {\r
1809                                 /* ownPaRAMSets */\r
1810                                 /* 31     0     63    32     95    64     127   96 */\r
1811                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1812                                 /* 159  128     191  160     223  192     255  224 */\r
1813                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1814                                 /* 287  256     319  288     351  320     383  352 */\r
1815                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1816                                 /* 415  384     447  416     479  448     511  480 */\r
1817                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1818 \r
1819                                 /* ownDmaChannels */\r
1820                                 /* 31     0     63    32 */\r
1821                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1822 \r
1823                                 /* ownQdmaChannels */\r
1824                                 /* 31     0 */\r
1825                                 {0x000000FFU},\r
1826 \r
1827                                 /* ownTccs */\r
1828                                 /* 31     0     63    32 */\r
1829                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1830 \r
1831                                 /* resvdPaRAMSets */\r
1832                                 /* 31     0     63    32     95    64     127   96 */\r
1833                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1834                                 /* 159  128     191  160     223  192     255  224 */\r
1835                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1836                                 /* 287  256     319  288     351  320     383  352 */\r
1837                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1838                                 /* 415  384     447  416     479  448     511  480 */\r
1839                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1840 \r
1841                                 /* resvdDmaChannels */\r
1842                                 /* 31     0     63    32 */\r
1843                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1844 \r
1845                                 /* resvdQdmaChannels */\r
1846                                 /* 31     0 */\r
1847                                 {0x00U},\r
1848 \r
1849                                 /* resvdTccs */\r
1850                                 /* 31     0     63    32 */\r
1851                                 {0x00U, 0x00U},\r
1852                         },\r
1853 \r
1854                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1855                         {\r
1856                                 /* ownPaRAMSets */\r
1857                                 /* 31     0     63    32     95    64     127   96 */\r
1858                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1859                                 /* 159  128     191  160     223  192     255  224 */\r
1860                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1861                                 /* 287  256     319  288     351  320     383  352 */\r
1862                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1863                                 /* 415  384     447  416     479  448     511  480 */\r
1864                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1865 \r
1866                                 /* ownDmaChannels */\r
1867                                 /* 31     0     63    32 */\r
1868                                 {0x00000000U, 0x00000000U},\r
1869 \r
1870                                 /* ownQdmaChannels */\r
1871                                 /* 31     0 */\r
1872                                 {0x00000000U},\r
1873 \r
1874                                 /* ownTccs */\r
1875                                 /* 31     0     63    32 */\r
1876                                 {0x00000000U, 0x00000000U},\r
1877 \r
1878                                 /* resvdPaRAMSets */\r
1879                                 /* 31     0     63    32     95    64     127   96 */\r
1880                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1881                                 /* 159  128     191  160     223  192     255  224 */\r
1882                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1883                                 /* 287  256     319  288     351  320     383  352 */\r
1884                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1885                                 /* 415  384     447  416     479  448     511  480 */\r
1886                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1887 \r
1888                                 /* resvdDmaChannels */\r
1889                                 /* 31     0     63    32 */\r
1890                                 {0x00000000U, 0x00000000U},\r
1891 \r
1892                                 /* resvdQdmaChannels */\r
1893                                 /* 31     0 */\r
1894                                 {0x00000000U},\r
1895 \r
1896                                 /* resvdTccs */\r
1897                                 /* 31     0     63    32 */\r
1898                                 {0x00000000U, 0x00000000U},\r
1899                         },\r
1900 \r
1901                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1902                         {\r
1903                                 /* ownPaRAMSets */\r
1904                                 /* 31     0     63    32     95    64     127   96 */\r
1905                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1906                                 /* 159  128     191  160     223  192     255  224 */\r
1907                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1908                                 /* 287  256     319  288     351  320     383  352 */\r
1909                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1910                                 /* 415  384     447  416     479  448     511  480 */\r
1911                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1912 \r
1913                                 /* ownDmaChannels */\r
1914                                 /* 31     0     63    32 */\r
1915                                 {0x00000000U, 0x00000000U},\r
1916 \r
1917                                 /* ownQdmaChannels */\r
1918                                 /* 31     0 */\r
1919                                 {0x00000000U},\r
1920 \r
1921                                 /* ownTccs */\r
1922                                 /* 31     0     63    32 */\r
1923                                 {0x00000000U, 0x00000000U},\r
1924 \r
1925                                 /* resvdPaRAMSets */\r
1926                                 /* 31     0     63    32     95    64     127   96 */\r
1927                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1928                                 /* 159  128     191  160     223  192     255  224 */\r
1929                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1930                                 /* 287  256     319  288     351  320     383  352 */\r
1931                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1932                                 /* 415  384     447  416     479  448     511  480 */\r
1933                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1934 \r
1935                                 /* resvdDmaChannels */\r
1936                                 /* 31     0     63    32 */\r
1937                                 {0x00000000U, 0x00000000U},\r
1938 \r
1939                                 /* resvdQdmaChannels */\r
1940                                 /* 31     0 */\r
1941                                 {0x00000000U},\r
1942 \r
1943                                 /* resvdTccs */\r
1944                                 /* 31     0     63    32 */\r
1945                                 {0x00000000U, 0x00000000U},\r
1946                         },\r
1947 \r
1948                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1949                         {\r
1950                                 /* ownPaRAMSets */\r
1951                                 /* 31     0     63    32     95    64     127   96 */\r
1952                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1953                                 /* 159  128     191  160     223  192     255  224 */\r
1954                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1955                                 /* 287  256     319  288     351  320     383  352 */\r
1956                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1957                                 /* 415  384     447  416     479  448     511  480 */\r
1958                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1959 \r
1960                                 /* ownDmaChannels */\r
1961                                 /* 31     0     63    32 */\r
1962                                 {0x00000000U, 0x00000000U},\r
1963 \r
1964                                 /* ownQdmaChannels */\r
1965                                 /* 31     0 */\r
1966                                 {0x00000000U},\r
1967 \r
1968                                 /* ownTccs */\r
1969                                 /* 31     0     63    32 */\r
1970                                 {0x00000000U, 0x00000000U},\r
1971 \r
1972                                 /* resvdPaRAMSets */\r
1973                                 /* 31     0     63    32     95    64     127   96 */\r
1974                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1975                                 /* 159  128     191  160     223  192     255  224 */\r
1976                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1977                                 /* 287  256     319  288     351  320     383  352 */\r
1978                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1979                                 /* 415  384     447  416     479  448     511  480 */\r
1980                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1981 \r
1982                                 /* resvdDmaChannels */\r
1983                                 /* 31     0     63    32 */\r
1984                                 {0x00000000U, 0x00000000U},\r
1985 \r
1986                                 /* resvdQdmaChannels */\r
1987                                 /* 31     0 */\r
1988                                 {0x00000000U},\r
1989 \r
1990                                 /* resvdTccs */\r
1991                                 /* 31     0     63    32 */\r
1992                                 {0x00000000U, 0x00000000U},\r
1993                         },\r
1994 \r
1995                 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1996                         {\r
1997                                 /* ownPaRAMSets */\r
1998                                 /* 31     0     63    32     95    64     127   96 */\r
1999                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2000                                 /* 159  128     191  160     223  192     255  224 */\r
2001                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2002                                 /* 287  256     319  288     351  320     383  352 */\r
2003                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2004                                 /* 415  384     447  416     479  448     511  480 */\r
2005                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2006 \r
2007                                 /* ownDmaChannels */\r
2008                                 /* 31     0     63    32 */\r
2009                                 {0x00000000U, 0x00000000U},\r
2010 \r
2011                                 /* ownQdmaChannels */\r
2012                                 /* 31     0 */\r
2013                                 {0x00000000U},\r
2014 \r
2015                                 /* ownTccs */\r
2016                                 /* 31     0     63    32 */\r
2017                                 {0x00000000U, 0x00000000U},\r
2018 \r
2019                                 /* resvdPaRAMSets */\r
2020                                 /* 31     0     63    32     95    64     127   96 */\r
2021                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2022                                 /* 159  128     191  160     223  192     255  224 */\r
2023                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2024                                 /* 287  256     319  288     351  320     383  352 */\r
2025                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2026                                 /* 415  384     447  416     479  448     511  480 */\r
2027                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2028 \r
2029                                 /* resvdDmaChannels */\r
2030                                 /* 31     0     63    32 */\r
2031                                 {0x00000000U, 0x00000000U},\r
2032 \r
2033                                 /* resvdQdmaChannels */\r
2034                                 /* 31     0 */\r
2035                                 {0x00000000U},\r
2036 \r
2037                                 /* resvdTccs */\r
2038                                 /* 31     0     63    32 */\r
2039                                 {0x00000000U, 0x00000000U},\r
2040                         },\r
2041             },\r
2042                 /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
2043                 {\r
2044                 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
2045                         {\r
2046                                 /* ownPaRAMSets */\r
2047                                 /* 31     0     63    32     95    64     127   96 */\r
2048                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2049                                 /* 159  128     191  160     223  192     255  224 */\r
2050                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2051                                 /* 287  256     319  288     351  320     383  352 */\r
2052                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2053                                 /* 415  384     447  416     479  448     511  480 */\r
2054                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2055 \r
2056                                 /* ownDmaChannels */\r
2057                                 /* 31     0     63    32 */\r
2058                                 {0x00000000U, 0x00000000U},\r
2059 \r
2060                                 /* ownQdmaChannels */\r
2061                                 /* 31     0 */\r
2062                                 {0x00000000U},\r
2063 \r
2064                                 /* ownTccs */\r
2065                                 /* 31     0     63    32 */\r
2066                                 {0x00000000U, 0x00000000U},\r
2067 \r
2068                                 /* resvdPaRAMSets */\r
2069                                 /* 31     0     63    32     95    64     127   96 */\r
2070                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2071                                 /* 159  128     191  160     223  192     255  224 */\r
2072                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2073                                 /* 287  256     319  288     351  320     383  352 */\r
2074                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2075                                 /* 415  384     447  416     479  448     511  480 */\r
2076                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2077 \r
2078                                 /* resvdDmaChannels */\r
2079                                 /* 31     0     63    32 */\r
2080                                 {0x00000000U, 0x00000000U},\r
2081 \r
2082                                 /* resvdQdmaChannels */\r
2083                                 /* 31     0 */\r
2084                                 {0x00000000U},\r
2085 \r
2086                                 /* resvdTccs */\r
2087                                 /* 31     0     63    32 */\r
2088                                 {0x00000000U, 0x00000000U},\r
2089                         },\r
2090 \r
2091                 /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
2092                         {\r
2093                                 /* ownPaRAMSets */\r
2094                                 /* 31     0     63    32     95    64     127   96 */\r
2095                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
2096                                 /* 159  128     191  160     223  192     255  224 */\r
2097                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2098                                 /* 287  256     319  288     351  320     383  352 */\r
2099                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2100                                 /* 415  384     447  416     479  448     511  480 */\r
2101                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},\r
2102 \r
2103                                 /* ownDmaChannels */\r
2104                                 /* 31     0     63    32 */\r
2105                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
2106 \r
2107                                 /* ownQdmaChannels */\r
2108                                 /* 31     0 */\r
2109                                 {0x000000FFU},\r
2110 \r
2111                                 /* ownTccs */\r
2112                                 /* 31     0     63    32 */\r
2113                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
2114 \r
2115                                 /* resvdPaRAMSets */\r
2116                                 /* 31     0     63    32     95    64     127   96 */\r
2117                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2118                                 /* 159  128     191  160     223  192     255  224 */\r
2119                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2120                                 /* 287  256     319  288     351  320     383  352 */\r
2121                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2122                                 /* 415  384     447  416     479  448     511  480 */\r
2123                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2124 \r
2125                                 /* resvdDmaChannels */\r
2126                                 /* 31     0     63    32 */\r
2127                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},\r
2128 \r
2129                                 /* resvdQdmaChannels */\r
2130                                 /* 31     0 */\r
2131                                 {0x00U},\r
2132 \r
2133                                 /* resvdTccs */\r
2134                                 /* 31     0     63    32 */\r
2135                                 {0x00U, 0x00U},\r
2136                         },\r
2137 \r
2138                 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
2139                         {\r
2140                                 /* ownPaRAMSets */\r
2141                                 /* 31     0     63    32     95    64     127   96 */\r
2142                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2143                                 /* 159  128     191  160     223  192     255  224 */\r
2144                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2145                                 /* 287  256     319  288     351  320     383  352 */\r
2146                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2147                                 /* 415  384     447  416     479  448     511  480 */\r
2148                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2149 \r
2150                                 /* ownDmaChannels */\r
2151                                 /* 31     0     63    32 */\r
2152                                 {0x00000000U, 0x00000000U},\r
2153 \r
2154                                 /* ownQdmaChannels */\r
2155                                 /* 31     0 */\r
2156                                 {0x00000000U},\r
2157 \r
2158                                 /* ownTccs */\r
2159                                 /* 31     0     63    32 */\r
2160                                 {0x00000000U, 0x00000000U},\r
2161 \r
2162                                 /* resvdPaRAMSets */\r
2163                                 /* 31     0     63    32     95    64     127   96 */\r
2164                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2165                                 /* 159  128     191  160     223  192     255  224 */\r
2166                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2167                                 /* 287  256     319  288     351  320     383  352 */\r
2168                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2169                                 /* 415  384     447  416     479  448     511  480 */\r
2170                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2171 \r
2172                                 /* resvdDmaChannels */\r
2173                                 /* 31     0     63    32 */\r
2174                                 {0x00000000U, 0x00000000U},\r
2175 \r
2176                                 /* resvdQdmaChannels */\r
2177                                 /* 31     0 */\r
2178                                 {0x00000000U},\r
2179 \r
2180                                 /* resvdTccs */\r
2181                                 /* 31     0     63    32 */\r
2182                                 {0x00000000U, 0x00000000U},\r
2183                         },\r
2184 \r
2185                 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
2186                         {\r
2187                                 /* ownPaRAMSets */\r
2188                                 /* 31     0     63    32     95    64     127   96 */\r
2189                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2190                                 /* 159  128     191  160     223  192     255  224 */\r
2191                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2192                                 /* 287  256     319  288     351  320     383  352 */\r
2193                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2194                                 /* 415  384     447  416     479  448     511  480 */\r
2195                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2196 \r
2197                                 /* ownDmaChannels */\r
2198                                 /* 31     0     63    32 */\r
2199                                 {0x00000000U, 0x00000000U},\r
2200 \r
2201                                 /* ownQdmaChannels */\r
2202                                 /* 31     0 */\r
2203                                 {0x00000000U},\r
2204 \r
2205                                 /* ownTccs */\r
2206                                 /* 31     0     63    32 */\r
2207                                 {0x00000000U, 0x00000000U},\r
2208 \r
2209                                 /* resvdPaRAMSets */\r
2210                                 /* 31     0     63    32     95    64     127   96 */\r
2211                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2212                                 /* 159  128     191  160     223  192     255  224 */\r
2213                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2214                                 /* 287  256     319  288     351  320     383  352 */\r
2215                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2216                                 /* 415  384     447  416     479  448     511  480 */\r
2217                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2218 \r
2219                                 /* resvdDmaChannels */\r
2220                                 /* 31     0     63    32 */\r
2221                                 {0x00000000U, 0x00000000U},\r
2222 \r
2223                                 /* resvdQdmaChannels */\r
2224                                 /* 31     0 */\r
2225                                 {0x00000000U},\r
2226 \r
2227                                 /* resvdTccs */\r
2228                                 /* 31     0     63    32 */\r
2229                                 {0x00000000U, 0x00000000U},\r
2230                         },\r
2231 \r
2232                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
2233                         {\r
2234                                 /* ownPaRAMSets */\r
2235                                 /* 31     0     63    32     95    64     127   96 */\r
2236                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2237                                 /* 159  128     191  160     223  192     255  224 */\r
2238                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2239                                 /* 287  256     319  288     351  320     383  352 */\r
2240                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2241                                 /* 415  384     447  416     479  448     511  480 */\r
2242                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2243 \r
2244                                 /* ownDmaChannels */\r
2245                                 /* 31     0     63    32 */\r
2246                                 {0x00000000U, 0x00000000U},\r
2247 \r
2248                                 /* ownQdmaChannels */\r
2249                                 /* 31     0 */\r
2250                                 {0x00000000U},\r
2251 \r
2252                                 /* ownTccs */\r
2253                                 /* 31     0     63    32 */\r
2254                                 {0x00000000U, 0x00000000U},\r
2255 \r
2256                                 /* resvdPaRAMSets */\r
2257                                 /* 31     0     63    32     95    64     127   96 */\r
2258                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2259                                 /* 159  128     191  160     223  192     255  224 */\r
2260                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2261                                 /* 287  256     319  288     351  320     383  352 */\r
2262                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r