[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2 * sample_tda2xx_cfg.c\r
3 *\r
4 * SoC specific EDMA3 hardware related information like number of transfer\r
5 * controllers, various interrupt ids etc. It is used while interrupts\r
6 * enabling / disabling. It needs to be ported for different SoCs.\r
7 *\r
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9 *\r
10 *\r
11 * Redistribution and use in source and binary forms, with or without\r
12 * modification, are permitted provided that the following conditions\r
13 * are met:\r
14 *\r
15 * Redistributions of source code must retain the above copyright\r
16 * notice, this list of conditions and the following disclaimer.\r
17 *\r
18 * Redistributions in binary form must reproduce the above copyright\r
19 * notice, this list of conditions and the following disclaimer in the\r
20 * documentation and/or other materials provided with the\r
21 * distribution.\r
22 *\r
23 * Neither the name of Texas Instruments Incorporated nor the names of\r
24 * its contributors may be used to endorse or promote products derived\r
25 * from this software without specific prior written permission.\r
26 *\r
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38 *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
42 \r
43 /* Number of EDMA3 controllers present in the system */\r
44 #define NUM_EDMA3_INSTANCES 2u\r
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
46 \r
47 /* Number of DSPs present in the system */\r
48 #define NUM_DSPS 1u\r
49 const unsigned int numDsps = NUM_DSPS;\r
50 \r
51 /* Determine the processor id by reading DNUM register. */\r
52 /* Statically allocate the region numbers with cores. */\r
53 unsigned short determineProcId()\r
54 {\r
55 #ifdef BUILD_TDA2XX_MPU\r
56 return 0;\r
57 #elif defined BUILD_TDA2XX_DSP\r
58 return 1;\r
59 #elif defined BUILD_TDA2XX_IPU0\r
60 return 2;\r
61 #elif defined BUILD_TDA2XX_IPU1\r
62 return 3;\r
63 #else\r
64 return 4;\r
65 #endif\r
66 }\r
67 \r
68 signed char* getGlobalAddr(signed char* addr)\r
69 {\r
70 return (addr); /* The address is already a global address */\r
71 }\r
72 unsigned short isGblConfigRequired(unsigned int dspNum)\r
73 {\r
74 (void) dspNum;\r
75 return 1;\r
76 }\r
77 \r
78 /* Semaphore handles */\r
79 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
80 \r
81 /** Number of PaRAM Sets available */\r
82 #define EDMA3_NUM_PARAMSET (512u)\r
83 \r
84 /** Number of TCCS available */\r
85 #define EDMA3_NUM_TCC (64u)\r
86 \r
87 /** Number of DMA Channels available */\r
88 #define EDMA3_NUM_DMA_CHANNELS (64u)\r
89 \r
90 /** Number of QDMA Channels available */\r
91 #define EDMA3_NUM_QDMA_CHANNELS (8u)\r
92 \r
93 /** Number of Event Queues available */\r
94 #define EDMA3_NUM_EVTQUE (4u)\r
95 \r
96 /** Number of Transfer Controllers available */\r
97 #define EDMA3_NUM_TC (2u)\r
98 \r
99 /** Number of Regions */\r
100 #define EDMA3_NUM_REGIONS (8u)\r
101 \r
102 /** Interrupt no. for Transfer Completion */\r
103 #define EDMA3_CC_XFER_COMPLETION_INT_A15 (66u)\r
104 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u)\r
105 #define EDMA3_CC_XFER_COMPLETION_INT_IPU0 (34u)\r
106 #define EDMA3_CC_XFER_COMPLETION_INT_IPU1 (34u)\r
107 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
108 #define COMPLETION_INT_A15_XBAR_INST_NO (29u)\r
109 #define COMPLETION_INT_DSP_XBAR_INST_NO (7u)\r
110 #define COMPLETION_INT_IPU0_XBAR_INST_NO (12u)\r
111 #define COMPLETION_INT_IPU1_XBAR_INST_NO (12u)\r
112 \r
113 /** Interrupt no. for CC Error */\r
114 #define EDMA3_CC_ERROR_INT_A15 (67u)\r
115 #define EDMA3_CC_ERROR_INT_DSP (39u)\r
116 #define EDMA3_CC_ERROR_INT_IPU0 (35u)\r
117 #define EDMA3_CC_ERROR_INT_IPU1 (35u)\r
118 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
119 #define CC_ERROR_INT_A15_XBAR_INST_NO (30u)\r
120 #define CC_ERROR_INT_DSP_XBAR_INST_NO (8u)\r
121 #define CC_ERROR_INT_IPU0_XBAR_INST_NO (13u)\r
122 #define CC_ERROR_INT_IPU1_XBAR_INST_NO (13u)\r
123 \r
124 \r
125 /** Interrupt no. for TCs Error */\r
126 #define EDMA3_TC0_ERROR_INT_A15 (68u)\r
127 #define EDMA3_TC0_ERROR_INT_DSP (40u)\r
128 #define EDMA3_TC0_ERROR_INT_IPU0 (36u)\r
129 #define EDMA3_TC0_ERROR_INT_IPU1 (36u)\r
130 #define EDMA3_TC1_ERROR_INT_A15 (69u)\r
131 #define EDMA3_TC1_ERROR_INT_DSP (41u)\r
132 #define EDMA3_TC1_ERROR_INT_IPU0 (37u)\r
133 #define EDMA3_TC1_ERROR_INT_IPU1 (37u)\r
134 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
135 #define TC0_ERROR_INT_A15_XBAR_INST_NO (31u)\r
136 #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u)\r
137 #define TC0_ERROR_INT_IPU0_XBAR_INST_NO (14u)\r
138 #define TC0_ERROR_INT_IPU1_XBAR_INST_NO (14u)\r
139 #define TC1_ERROR_INT_A15_XBAR_INST_NO (32u)\r
140 #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u)\r
141 #define TC1_ERROR_INT_IPU0_XBAR_INST_NO (15u)\r
142 #define TC1_ERROR_INT_IPU1_XBAR_INST_NO (15u)\r
143 \r
144 #ifdef BUILD_TDA2XX_MPU\r
145 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15\r
146 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A15\r
147 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_A15_XBAR_INST_NO\r
148 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A15\r
149 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A15\r
150 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
151 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
152 \r
153 #elif defined BUILD_TDA2XX_DSP\r
154 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP\r
155 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP\r
156 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_DSP_XBAR_INST_NO\r
157 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP\r
158 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP\r
159 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_DSP_XBAR_INST_NO\r
160 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_DSP_XBAR_INST_NO\r
161 \r
162 #elif defined BUILD_TDA2XX_IPU1\r
163 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU0\r
164 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU0\r
165 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU0_XBAR_INST_NO\r
166 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU0\r
167 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU0\r
168 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU0_XBAR_INST_NO\r
169 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU0_XBAR_INST_NO\r
170 \r
171 #elif defined BUILD_TDA2XX_IPU2\r
172 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU1\r
173 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU1\r
174 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU1_XBAR_INST_NO\r
175 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU1\r
176 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU1\r
177 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU1_XBAR_INST_NO\r
178 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU1_XBAR_INST_NO\r
179 \r
180 #else\r
181 #define EDMA3_CC_XFER_COMPLETION_INT {0u}\r
182 #define EDMA3_CC_ERROR_INT {0u}\r
183 #define CC_ERROR_INT_XBAR_INST_NO {0u}\r
184 #define EDMA3_TC0_ERROR_INT (0u)\r
185 #define EDMA3_TC1_ERROR_INT (0u)\r
186 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
187 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
188 #endif\r
189 \r
190 #define EDMA3_TC2_ERROR_INT (0u)\r
191 #define EDMA3_TC3_ERROR_INT (0u)\r
192 #define EDMA3_TC4_ERROR_INT (0u)\r
193 #define EDMA3_TC5_ERROR_INT (0u)\r
194 #define EDMA3_TC6_ERROR_INT (0u)\r
195 #define EDMA3_TC7_ERROR_INT (0u)\r
196 \r
197 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (18u)\r
198 #define DSP1_EDMA3_CC_ERROR_INT {27u}\r
199 #define DSP1_EDMA3_TC0_ERROR_INT (28u)\r
200 #define DSP1_EDMA3_TC1_ERROR_INT (29u)\r
201 \r
202 /** XBAR interrupt source index numbers for EDMA interrupts */\r
203 #define XBAR_EDMA_TPCC_IRQ_REGION0 (361u)\r
204 #define XBAR_EDMA_TPCC_IRQ_REGION1 (362u)\r
205 #define XBAR_EDMA_TPCC_IRQ_REGION2 (363u)\r
206 #define XBAR_EDMA_TPCC_IRQ_REGION3 (364u)\r
207 #define XBAR_EDMA_TPCC_IRQ_REGION4 (365u)\r
208 #define XBAR_EDMA_TPCC_IRQ_REGION5 (366u)\r
209 #define XBAR_EDMA_TPCC_IRQ_REGION6 (367u)\r
210 #define XBAR_EDMA_TPCC_IRQ_REGION7 (368u)\r
211 \r
212 #define XBAR_EDMA_TPCC_IRQ_ERR (359u)\r
213 #define XBAR_EDMA_TC0_IRQ_ERR (370u)\r
214 #define XBAR_EDMA_TC1_IRQ_ERR (371u)\r
215 \r
216 /**\r
217 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
218 * ECM events (SoC specific). These ECM events come\r
219 * under ECM block XXX (handling those specific ECM events). Normally, block\r
220 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
221 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
222 * is mapped to a specific HWI_INT YYY in the tcf file.\r
223 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
224 * to transfer completion interrupt.\r
225 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
226 * to CC error interrupts.\r
227 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
228 * to TC error interrupts.\r
229 */\r
230 /* EDMA 0 */\r
231 \r
232 #define EDMA3_HWI_INT_XFER_COMP (7u)\r
233 #define EDMA3_HWI_INT_CC_ERR (7u)\r
234 #define EDMA3_HWI_INT_TC0_ERR (10u)\r
235 #define EDMA3_HWI_INT_TC1_ERR (10u)\r
236 #define EDMA3_HWI_INT_TC2_ERR (10u)\r
237 #define EDMA3_HWI_INT_TC3_ERR (10u)\r
238 \r
239 /**\r
240 * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
241 * various peripherals, which use EDMA for data transfer.\r
242 * All channels need not be mapped, some can be free also.\r
243 * 1: Mapped\r
244 * 0: Not mapped\r
245 *\r
246 * This mapping will be used to allocate DMA channels when user passes\r
247 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
248 * copy). The same mapping is used to allocate the TCC when user passes\r
249 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
250 *\r
251 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
252 */\r
253 /* 31 0 */\r
254 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x00000000u) /* TBD */\r
255 \r
256 \r
257 /**\r
258 * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
259 * various peripherals, which use EDMA for data transfer.\r
260 * All channels need not be mapped, some can be free also.\r
261 * 1: Mapped\r
262 * 0: Not mapped\r
263 *\r
264 * This mapping will be used to allocate DMA channels when user passes\r
265 * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
266 * copy). The same mapping is used to allocate the TCC when user passes\r
267 * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
268 *\r
269 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
270 */\r
271 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x00000000u) /* TBD */\r
272 \r
273 \r
274 /* Variable which will be used internally for referring number of Event Queues*/\r
275 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {\r
276 EDMA3_NUM_EVTQUE,\r
277 };\r
278 \r
279 /* Variable which will be used internally for referring number of TCs. */\r
280 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
281 EDMA3_NUM_TC,\r
282 };\r
283 \r
284 /**\r
285 * Variable which will be used internally for referring transfer completion\r
286 * interrupt.\r
287 */\r
288 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
289 {\r
290 {\r
291 EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
292 EDMA3_CC_XFER_COMPLETION_INT_IPU0, EDMA3_CC_XFER_COMPLETION_INT_IPU1,\r
293 0u, 0u, 0u, 0u,\r
294 },\r
295 {\r
296 0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,\r
297 0u, 0u, 0u, 0u,\r
298 },\r
299 };\r
300 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
301 unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
302 {\r
303 {\r
304 COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO,\r
305 COMPLETION_INT_IPU0_XBAR_INST_NO, COMPLETION_INT_IPU1_XBAR_INST_NO,\r
306 0u, 0u, 0u, 0u,\r
307 },\r
308 };\r
309 \r
310 /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
311 unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
312 {\r
313 {\r
314 XBAR_EDMA_TPCC_IRQ_REGION0, XBAR_EDMA_TPCC_IRQ_REGION1, XBAR_EDMA_TPCC_IRQ_REGION2, XBAR_EDMA_TPCC_IRQ_REGION3,\r
315 XBAR_EDMA_TPCC_IRQ_REGION4, XBAR_EDMA_TPCC_IRQ_REGION5, XBAR_EDMA_TPCC_IRQ_REGION6, XBAR_EDMA_TPCC_IRQ_REGION7,\r
316 }\r
317 };\r
318 \r
319 /**\r
320 * Variable which will be used internally for referring channel controller's\r
321 * error interrupt.\r
322 */\r
323 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
324 EDMA3_CC_ERROR_INT,DSP1_EDMA3_CC_ERROR_INT,\r
325 };\r
326 unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] = {\r
327 CC_ERROR_INT_XBAR_INST_NO,\r
328 };\r
329 unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
330 {\r
331 XBAR_EDMA_TPCC_IRQ_ERR,\r
332 };\r
333 \r
334 /**\r
335 * Variable which will be used internally for referring transfer controllers'\r
336 * error interrupts.\r
337 */\r
338 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
339 {\r
340 {\r
341 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
342 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
343 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
344 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
345 },\r
346 {\r
347 DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
348 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
349 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
350 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
351 }\r
352 };\r
353 unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =\r
354 {\r
355 {\r
356 TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
357 0u, 0u,\r
358 0u, 0u,\r
359 0u, 0u,\r
360 }\r
361 };\r
362 \r
363 unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][8] =\r
364 {\r
365 {\r
366 XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
367 0u, 0u,\r
368 0u, 0u, 0u, 0u,\r
369 }\r
370 };\r
371 \r
372 \r
373 /**\r
374 * Variables which will be used internally for referring the hardware interrupt\r
375 * for various EDMA3 interrupts.\r
376 */\r
377 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
378 EDMA3_HWI_INT_XFER_COMP, EDMA3_HWI_INT_XFER_COMP,\r
379 };\r
380 \r
381 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
382 EDMA3_HWI_INT_CC_ERR, EDMA3_HWI_INT_CC_ERR,\r
383 };\r
384 \r
385 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
386 {\r
387 EDMA3_HWI_INT_TC0_ERR,\r
388 EDMA3_HWI_INT_TC1_ERR,\r
389 EDMA3_HWI_INT_TC2_ERR,\r
390 EDMA3_HWI_INT_TC3_ERR\r
391 },\r
392 {\r
393 EDMA3_HWI_INT_TC0_ERR,\r
394 EDMA3_HWI_INT_TC1_ERR,\r
395 EDMA3_HWI_INT_TC2_ERR,\r
396 EDMA3_HWI_INT_TC3_ERR\r
397 }\r
398 };\r
399 \r
400 /**\r
401 * \brief Base address as seen from the different cores may be different\r
402 * And is defined based on the core\r
403 */\r
404 #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
405 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))\r
406 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))\r
407 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))\r
408 #elif ((defined BUILD_TDA2XX_IPU0) || (defined BUILD_TDA2XX_IPU1))\r
409 #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))\r
410 #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))\r
411 #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))\r
412 #else\r
413 #define EDMA3_CC_BASE_ADDR ((void *)(0x0))\r
414 #define EDMA3_TC0_BASE_ADDR ((void *)(0x0))\r
415 #define EDMA3_TC1_BASE_ADDR ((void *)(0x0))\r
416 #endif\r
417 \r
418 #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000))\r
419 #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000))\r
420 #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000))\r
421 \r
422 /* Driver Object Initialization Configuration */\r
423 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
424 {\r
425 {\r
426 /* EDMA3 INSTANCE# 0 */\r
427 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
428 EDMA3_NUM_DMA_CHANNELS,\r
429 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
430 EDMA3_NUM_QDMA_CHANNELS,\r
431 /** Total number of TCCs supported by the EDMA3 Controller */\r
432 EDMA3_NUM_TCC,\r
433 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
434 EDMA3_NUM_PARAMSET,\r
435 /** Total number of Event Queues in the EDMA3 Controller */\r
436 EDMA3_NUM_EVTQUE,\r
437 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
438 EDMA3_NUM_TC,\r
439 /** Number of Regions on this EDMA3 controller */\r
440 EDMA3_NUM_REGIONS,\r
441 \r
442 /**\r
443 * \brief Channel mapping existence\r
444 * A value of 0 (No channel mapping) implies that there is fixed association\r
445 * for a channel number to a parameter entry number or, in other words,\r
446 * PaRAM entry n corresponds to channel n.\r
447 */\r
448 1u,\r
449 \r
450 /** Existence of memory protection feature */\r
451 0u,\r
452 \r
453 /** Global Register Region of CC Registers */\r
454 EDMA3_CC_BASE_ADDR,\r
455 /** Transfer Controller (TC) Registers */\r
456 {\r
457 EDMA3_TC0_BASE_ADDR,\r
458 EDMA3_TC1_BASE_ADDR,\r
459 (void *)NULL,\r
460 (void *)NULL,\r
461 (void *)NULL,\r
462 (void *)NULL,\r
463 (void *)NULL,\r
464 (void *)NULL\r
465 },\r
466 /** Interrupt no. for Transfer Completion */\r
467 EDMA3_CC_XFER_COMPLETION_INT,\r
468 /** Interrupt no. for CC Error */\r
469 EDMA3_CC_ERROR_INT,\r
470 /** Interrupt no. for TCs Error */\r
471 {\r
472 EDMA3_TC0_ERROR_INT,\r
473 EDMA3_TC1_ERROR_INT,\r
474 EDMA3_TC2_ERROR_INT,\r
475 EDMA3_TC3_ERROR_INT,\r
476 EDMA3_TC4_ERROR_INT,\r
477 EDMA3_TC5_ERROR_INT,\r
478 EDMA3_TC6_ERROR_INT,\r
479 EDMA3_TC7_ERROR_INT\r
480 },\r
481 \r
482 /**\r
483 * \brief EDMA3 TC priority setting\r
484 *\r
485 * User can program the priority of the Event Queues\r
486 * at a system-wide level. This means that the user can set the\r
487 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
488 * relative to IO initiated by the other bus masters on the\r
489 * device (ARM, DSP, USB, etc)\r
490 */\r
491 {\r
492 0u,\r
493 1u,\r
494 0u,\r
495 0u,\r
496 0u,\r
497 0u,\r
498 0u,\r
499 0u\r
500 },\r
501 /**\r
502 * \brief To Configure the Threshold level of number of events\r
503 * that can be queued up in the Event queues. EDMA3CC error register\r
504 * (CCERR) will indicate whether or not at any instant of time the\r
505 * number of events queued up in any of the event queues exceeds\r
506 * or equals the threshold/watermark value that is set\r
507 * in the queue watermark threshold register (QWMTHRA).\r
508 */\r
509 {\r
510 16u,\r
511 16u,\r
512 0u,\r
513 0u,\r
514 0u,\r
515 0u,\r
516 0u,\r
517 0u\r
518 },\r
519 \r
520 /**\r
521 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
522 * An optimally-sized command is defined by the transfer controller\r
523 * default burst size (DBS). Different TCs can have different\r
524 * DBS values. It is defined in Bytes.\r
525 */\r
526 {\r
527 16u,\r
528 16u,\r
529 0u,\r
530 0u,\r
531 0u,\r
532 0u,\r
533 0u,\r
534 0u\r
535 },\r
536 \r
537 /**\r
538 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
539 * if it exists, otherwise of no use.\r
540 */\r
541 {\r
542 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
543 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
544 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
545 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
546 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
547 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
548 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
549 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
550 },\r
551 \r
552 /**\r
553 * \brief Mapping from each DMA channel to a TCC. This specific\r
554 * TCC code will be returned when the transfer is completed\r
555 * on the mapped channel.\r
556 */\r
557 {\r
558 0u, 1u, 2u, 3u,\r
559 4u, 5u, 6u, 7u,\r
560 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
561 12u, 13u, 14u, 15u,\r
562 16u, 17u, 18u, 19u,\r
563 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
564 24u, 25u, 26u, 27u,\r
565 28u, 29u, 30u, 31u,\r
566 32u, 33u, 34u, 35u,\r
567 36u, 37u, 38u, 39u,\r
568 40u, 41u, 42u, 43u,\r
569 44u, 45u, 46u, 47u,\r
570 48u, 49u, 50u, 51u,\r
571 52u, 53u, 54u, 55u,\r
572 56u, 57u, 58u, 59u,\r
573 60u, 61u, 62u, 63u\r
574 },\r
575 \r
576 /**\r
577 * \brief Mapping of DMA channels to Hardware Events from\r
578 * various peripherals, which use EDMA for data transfer.\r
579 * All channels need not be mapped, some can be free also.\r
580 */\r
581 {\r
582 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
583 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
584 }\r
585 },\r
586 {\r
587 /* EDMA3 INSTANCE# 1 */\r
588 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
589 EDMA3_NUM_DMA_CHANNELS,\r
590 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
591 EDMA3_NUM_QDMA_CHANNELS,\r
592 /** Total number of TCCs supported by the EDMA3 Controller */\r
593 EDMA3_NUM_TCC,\r
594 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
595 EDMA3_NUM_PARAMSET,\r
596 /** Total number of Event Queues in the EDMA3 Controller */\r
597 EDMA3_NUM_EVTQUE,\r
598 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
599 EDMA3_NUM_TC,\r
600 /** Number of Regions on this EDMA3 controller */\r
601 EDMA3_NUM_REGIONS,\r
602 \r
603 /**\r
604 * \brief Channel mapping existence\r
605 * A value of 0 (No channel mapping) implies that there is fixed association\r
606 * for a channel number to a parameter entry number or, in other words,\r
607 * PaRAM entry n corresponds to channel n.\r
608 */\r
609 1u,\r
610 \r
611 /** Existence of memory protection feature */\r
612 0u,\r
613 \r
614 /** Global Register Region of CC Registers */\r
615 DSP1_EDMA3_CC_BASE_ADDR,\r
616 /** Transfer Controller (TC) Registers */\r
617 {\r
618 DSP1_EDMA3_TC0_BASE_ADDR,\r
619 DSP1_EDMA3_TC1_BASE_ADDR,\r
620 (void *)NULL,\r
621 (void *)NULL,\r
622 (void *)NULL,\r
623 (void *)NULL,\r
624 (void *)NULL,\r
625 (void *)NULL\r
626 },\r
627 /** Interrupt no. for Transfer Completion */\r
628 DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
629 /** Interrupt no. for CC Error */\r
630 DSP1_EDMA3_CC_ERROR_INT,\r
631 /** Interrupt no. for TCs Error */\r
632 {\r
633 DSP1_EDMA3_TC0_ERROR_INT,\r
634 DSP1_EDMA3_TC1_ERROR_INT,\r
635 EDMA3_TC2_ERROR_INT,\r
636 EDMA3_TC3_ERROR_INT,\r
637 EDMA3_TC4_ERROR_INT,\r
638 EDMA3_TC5_ERROR_INT,\r
639 EDMA3_TC6_ERROR_INT,\r
640 EDMA3_TC7_ERROR_INT\r
641 },\r
642 \r
643 /**\r
644 * \brief EDMA3 TC priority setting\r
645 *\r
646 * User can program the priority of the Event Queues\r
647 * at a system-wide level. This means that the user can set the\r
648 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
649 * relative to IO initiated by the other bus masters on the\r
650 * device (ARM, DSP, USB, etc)\r
651 */\r
652 {\r
653 0u,\r
654 1u,\r
655 0u,\r
656 0u,\r
657 0u,\r
658 0u,\r
659 0u,\r
660 0u\r
661 },\r
662 /**\r
663 * \brief To Configure the Threshold level of number of events\r
664 * that can be queued up in the Event queues. EDMA3CC error register\r
665 * (CCERR) will indicate whether or not at any instant of time the\r
666 * number of events queued up in any of the event queues exceeds\r
667 * or equals the threshold/watermark value that is set\r
668 * in the queue watermark threshold register (QWMTHRA).\r
669 */\r
670 {\r
671 16u,\r
672 16u,\r
673 0u,\r
674 0u,\r
675 0u,\r
676 0u,\r
677 0u,\r
678 0u\r
679 },\r
680 \r
681 /**\r
682 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
683 * An optimally-sized command is defined by the transfer controller\r
684 * default burst size (DBS). Different TCs can have different\r
685 * DBS values. It is defined in Bytes.\r
686 */\r
687 {\r
688 16u,\r
689 16u,\r
690 0u,\r
691 0u,\r
692 0u,\r
693 0u,\r
694 0u,\r
695 0u\r
696 },\r
697 \r
698 /**\r
699 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
700 * if it exists, otherwise of no use.\r
701 */\r
702 {\r
703 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
704 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
705 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
706 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
707 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
708 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
709 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
710 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
711 },\r
712 \r
713 /**\r
714 * \brief Mapping from each DMA channel to a TCC. This specific\r
715 * TCC code will be returned when the transfer is completed\r
716 * on the mapped channel.\r
717 */\r
718 {\r
719 0u, 1u, 2u, 3u,\r
720 4u, 5u, 6u, 7u,\r
721 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
722 12u, 13u, 14u, 15u,\r
723 16u, 17u, 18u, 19u,\r
724 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
725 24u, 25u, 26u, 27u,\r
726 28u, 29u, 30u, 31u,\r
727 32u, 33u, 34u, 35u,\r
728 36u, 37u, 38u, 39u,\r
729 40u, 41u, 42u, 43u,\r
730 44u, 45u, 46u, 47u,\r
731 48u, 49u, 50u, 51u,\r
732 52u, 53u, 54u, 55u,\r
733 56u, 57u, 58u, 59u,\r
734 60u, 61u, 62u, 63u\r
735 },\r
736 \r
737 /**\r
738 * \brief Mapping of DMA channels to Hardware Events from\r
739 * various peripherals, which use EDMA for data transfer.\r
740 * All channels need not be mapped, some can be free also.\r
741 */\r
742 {\r
743 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
744 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
745 }\r
746 },\r
747 };\r
748 \r
749 /**\r
750 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
751 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
752 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
753 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
754 *\r
755 * Only Resources owned by a perticular core are allocated by Driver\r
756 * Reserved resources are not allocated if requested for any available resource\r
757 */\r
758 \r
759 /* Driver Instance Initialization Configuration */\r
760 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
761 {\r
762 /* EDMA3 INSTANCE# 0 */\r
763 {\r
764 /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
765 {\r
766 /* ownPaRAMSets */\r
767 /* 31 0 63 32 95 64 127 96 */\r
768 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
769 /* 159 128 191 160 223 192 255 224 */\r
770 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
771 /* 287 256 319 288 351 320 383 352 */\r
772 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
773 /* 415 384 447 416 479 448 511 480 */\r
774 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
775 \r
776 /* ownDmaChannels */\r
777 /* 31 0 63 32 */\r
778 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
779 \r
780 /* ownQdmaChannels */\r
781 /* 31 0 */\r
782 {0x000000FFu},\r
783 \r
784 /* ownTccs */\r
785 /* 31 0 63 32 */\r
786 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
787 \r
788 /* resvdPaRAMSets */\r
789 /* 31 0 63 32 95 64 127 96 */\r
790 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
791 /* 159 128 191 160 223 192 255 224 */\r
792 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
793 /* 287 256 319 288 351 320 383 352 */\r
794 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
795 /* 415 384 447 416 479 448 511 480 */\r
796 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
797 \r
798 /* resvdDmaChannels */\r
799 /* 31 0 63 32 */\r
800 {0x00u, 0x00u},\r
801 \r
802 /* resvdQdmaChannels */\r
803 /* 31 0 */\r
804 {0x00u},\r
805 \r
806 /* resvdTccs */\r
807 /* 31 0 63 32 */\r
808 {0x00u, 0x00u},\r
809 },\r
810 \r
811 /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
812 {\r
813 /* ownPaRAMSets */\r
814 /* 31 0 63 32 95 64 127 96 */\r
815 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
816 /* 159 128 191 160 223 192 255 224 */\r
817 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
818 /* 287 256 319 288 351 320 383 352 */\r
819 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
820 /* 415 384 447 416 479 448 511 480 */\r
821 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
822 \r
823 /* ownDmaChannels */\r
824 /* 31 0 63 32 */\r
825 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
826 \r
827 /* ownQdmaChannels */\r
828 /* 31 0 */\r
829 {0x000000FFu},\r
830 \r
831 /* ownTccs */\r
832 /* 31 0 63 32 */\r
833 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
834 \r
835 /* resvdPaRAMSets */\r
836 /* 31 0 63 32 95 64 127 96 */\r
837 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
838 /* 159 128 191 160 223 192 255 224 */\r
839 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
840 /* 287 256 319 288 351 320 383 352 */\r
841 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
842 /* 415 384 447 416 479 448 511 480 */\r
843 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
844 \r
845 /* resvdDmaChannels */\r
846 /* 31 0 63 32 */\r
847 {0x00u, 0x00u},\r
848 \r
849 /* resvdQdmaChannels */\r
850 /* 31 0 */\r
851 {0x00u},\r
852 \r
853 /* resvdTccs */\r
854 /* 31 0 63 32 */\r
855 {0x00u, 0x00u},\r
856 },\r
857 \r
858 /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
859 {\r
860 /* ownPaRAMSets */\r
861 /* 31 0 63 32 95 64 127 96 */\r
862 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
863 /* 159 128 191 160 223 192 255 224 */\r
864 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
865 /* 287 256 319 288 351 320 383 352 */\r
866 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
867 /* 415 384 447 416 479 448 511 480 */\r
868 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
869 \r
870 /* ownDmaChannels */\r
871 /* 31 0 63 32 */\r
872 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
873 \r
874 /* ownQdmaChannels */\r
875 /* 31 0 */\r
876 {0x000000FFu},\r
877 \r
878 /* ownTccs */\r
879 /* 31 0 63 32 */\r
880 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
881 \r
882 /* resvdPaRAMSets */\r
883 /* 31 0 63 32 95 64 127 96 */\r
884 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
885 /* 159 128 191 160 223 192 255 224 */\r
886 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
887 /* 287 256 319 288 351 320 383 352 */\r
888 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
889 /* 415 384 447 416 479 448 511 480 */\r
890 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
891 \r
892 /* resvdDmaChannels */\r
893 /* 31 0 63 32 */\r
894 {0x00u, 0x00u},\r
895 \r
896 /* resvdQdmaChannels */\r
897 /* 31 0 */\r
898 {0x00u},\r
899 \r
900 /* resvdTccs */\r
901 /* 31 0 63 32 */\r
902 {0x00u, 0x00u},\r
903 },\r
904 \r
905 /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
906 {\r
907 /* ownPaRAMSets */\r
908 /* 31 0 63 32 95 64 127 96 */\r
909 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
910 /* 159 128 191 160 223 192 255 224 */\r
911 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
912 /* 287 256 319 288 351 320 383 352 */\r
913 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
914 /* 415 384 447 416 479 448 511 480 */\r
915 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
916 \r
917 /* ownDmaChannels */\r
918 /* 31 0 63 32 */\r
919 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
920 \r
921 /* ownQdmaChannels */\r
922 /* 31 0 */\r
923 {0x000000FFu},\r
924 \r
925 /* ownTccs */\r
926 /* 31 0 63 32 */\r
927 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
928 \r
929 /* resvdPaRAMSets */\r
930 /* 31 0 63 32 95 64 127 96 */\r
931 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
932 /* 159 128 191 160 223 192 255 224 */\r
933 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
934 /* 287 256 319 288 351 320 383 352 */\r
935 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
936 /* 415 384 447 416 479 448 511 480 */\r
937 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
938 \r
939 /* resvdDmaChannels */\r
940 /* 31 0 63 32 */\r
941 {0x00u, 0x00u},\r
942 \r
943 /* resvdQdmaChannels */\r
944 /* 31 0 */\r
945 {0x00u},\r
946 \r
947 /* resvdTccs */\r
948 /* 31 0 63 32 */\r
949 {0x00u, 0x00u},\r
950 },\r
951 \r
952 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
953 {\r
954 /* ownPaRAMSets */\r
955 /* 31 0 63 32 95 64 127 96 */\r
956 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
957 /* 159 128 191 160 223 192 255 224 */\r
958 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
959 /* 287 256 319 288 351 320 383 352 */\r
960 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
961 /* 415 384 447 416 479 448 511 480 */\r
962 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
963 \r
964 /* ownDmaChannels */\r
965 /* 31 0 63 32 */\r
966 {0x00000000u, 0x00000000u},\r
967 \r
968 /* ownQdmaChannels */\r
969 /* 31 0 */\r
970 {0x00000000u},\r
971 \r
972 /* ownTccs */\r
973 /* 31 0 63 32 */\r
974 {0x00000000u, 0x00000000u},\r
975 \r
976 /* resvdPaRAMSets */\r
977 /* 31 0 63 32 95 64 127 96 */\r
978 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
979 /* 159 128 191 160 223 192 255 224 */\r
980 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
981 /* 287 256 319 288 351 320 383 352 */\r
982 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
983 /* 415 384 447 416 479 448 511 480 */\r
984 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
985 \r
986 /* resvdDmaChannels */\r
987 /* 31 0 63 32 */\r
988 {0x00000000u, 0x00000000u},\r
989 \r
990 /* resvdQdmaChannels */\r
991 /* 31 0 */\r
992 {0x00000000u},\r
993 \r
994 /* resvdTccs */\r
995 /* 31 0 63 32 */\r
996 {0x00000000u, 0x00000000u},\r
997 },\r
998 \r
999 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1000 {\r
1001 /* ownPaRAMSets */\r
1002 /* 31 0 63 32 95 64 127 96 */\r
1003 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1004 /* 159 128 191 160 223 192 255 224 */\r
1005 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1006 /* 287 256 319 288 351 320 383 352 */\r
1007 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1008 /* 415 384 447 416 479 448 511 480 */\r
1009 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1010 \r
1011 /* ownDmaChannels */\r
1012 /* 31 0 63 32 */\r
1013 {0x00000000u, 0x00000000u},\r
1014 \r
1015 /* ownQdmaChannels */\r
1016 /* 31 0 */\r
1017 {0x00000000u},\r
1018 \r
1019 /* ownTccs */\r
1020 /* 31 0 63 32 */\r
1021 {0x00000000u, 0x00000000u},\r
1022 \r
1023 /* resvdPaRAMSets */\r
1024 /* 31 0 63 32 95 64 127 96 */\r
1025 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1026 /* 159 128 191 160 223 192 255 224 */\r
1027 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1028 /* 287 256 319 288 351 320 383 352 */\r
1029 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1030 /* 415 384 447 416 479 448 511 480 */\r
1031 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1032 \r
1033 /* resvdDmaChannels */\r
1034 /* 31 0 63 32 */\r
1035 {0x00000000u, 0x00000000u},\r
1036 \r
1037 /* resvdQdmaChannels */\r
1038 /* 31 0 */\r
1039 {0x00000000u},\r
1040 \r
1041 /* resvdTccs */\r
1042 /* 31 0 63 32 */\r
1043 {0x00000000u, 0x00000000u},\r
1044 },\r
1045 \r
1046 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1047 {\r
1048 /* ownPaRAMSets */\r
1049 /* 31 0 63 32 95 64 127 96 */\r
1050 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1051 /* 159 128 191 160 223 192 255 224 */\r
1052 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1053 /* 287 256 319 288 351 320 383 352 */\r
1054 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1055 /* 415 384 447 416 479 448 511 480 */\r
1056 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1057 \r
1058 /* ownDmaChannels */\r
1059 /* 31 0 63 32 */\r
1060 {0x00000000u, 0x00000000u},\r
1061 \r
1062 /* ownQdmaChannels */\r
1063 /* 31 0 */\r
1064 {0x00000000u},\r
1065 \r
1066 /* ownTccs */\r
1067 /* 31 0 63 32 */\r
1068 {0x00000000u, 0x00000000u},\r
1069 \r
1070 /* resvdPaRAMSets */\r
1071 /* 31 0 63 32 95 64 127 96 */\r
1072 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1073 /* 159 128 191 160 223 192 255 224 */\r
1074 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1075 /* 287 256 319 288 351 320 383 352 */\r
1076 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1077 /* 415 384 447 416 479 448 511 480 */\r
1078 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1079 \r
1080 /* resvdDmaChannels */\r
1081 /* 31 0 63 32 */\r
1082 {0x00000000u, 0x00000000u},\r
1083 \r
1084 /* resvdQdmaChannels */\r
1085 /* 31 0 */\r
1086 {0x00000000u},\r
1087 \r
1088 /* resvdTccs */\r
1089 /* 31 0 63 32 */\r
1090 {0x00000000u, 0x00000000u},\r
1091 },\r
1092 \r
1093 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1094 {\r
1095 /* ownPaRAMSets */\r
1096 /* 31 0 63 32 95 64 127 96 */\r
1097 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1098 /* 159 128 191 160 223 192 255 224 */\r
1099 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1100 /* 287 256 319 288 351 320 383 352 */\r
1101 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1102 /* 415 384 447 416 479 448 511 480 */\r
1103 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1104 \r
1105 /* ownDmaChannels */\r
1106 /* 31 0 63 32 */\r
1107 {0x00000000u, 0x00000000u},\r
1108 \r
1109 /* ownQdmaChannels */\r
1110 /* 31 0 */\r
1111 {0x00000000u},\r
1112 \r
1113 /* ownTccs */\r
1114 /* 31 0 63 32 */\r
1115 {0x00000000u, 0x00000000u},\r
1116 \r
1117 /* resvdPaRAMSets */\r
1118 /* 31 0 63 32 95 64 127 96 */\r
1119 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1120 /* 159 128 191 160 223 192 255 224 */\r
1121 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1122 /* 287 256 319 288 351 320 383 352 */\r
1123 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1124 /* 415 384 447 416 479 448 511 480 */\r
1125 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1126 \r
1127 /* resvdDmaChannels */\r
1128 /* 31 0 63 32 */\r
1129 {0x00000000u, 0x00000000u},\r
1130 \r
1131 /* resvdQdmaChannels */\r
1132 /* 31 0 */\r
1133 {0x00000000u},\r
1134 \r
1135 /* resvdTccs */\r
1136 /* 31 0 63 32 */\r
1137 {0x00000000u, 0x00000000u},\r
1138 },\r
1139 },\r
1140 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
1141 {\r
1142 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1143 {\r
1144 /* ownPaRAMSets */\r
1145 /* 31 0 63 32 95 64 127 96 */\r
1146 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1147 /* 159 128 191 160 223 192 255 224 */\r
1148 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1149 /* 287 256 319 288 351 320 383 352 */\r
1150 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1151 /* 415 384 447 416 479 448 511 480 */\r
1152 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1153 \r
1154 /* ownDmaChannels */\r
1155 /* 31 0 63 32 */\r
1156 {0x00000000u, 0x00000000u},\r
1157 \r
1158 /* ownQdmaChannels */\r
1159 /* 31 0 */\r
1160 {0x00000000u},\r
1161 \r
1162 /* ownTccs */\r
1163 /* 31 0 63 32 */\r
1164 {0x00000000u, 0x00000000u},\r
1165 \r
1166 /* resvdPaRAMSets */\r
1167 /* 31 0 63 32 95 64 127 96 */\r
1168 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1169 /* 159 128 191 160 223 192 255 224 */\r
1170 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1171 /* 287 256 319 288 351 320 383 352 */\r
1172 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1173 /* 415 384 447 416 479 448 511 480 */\r
1174 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1175 \r
1176 /* resvdDmaChannels */\r
1177 /* 31 0 63 32 */\r
1178 {0x00000000u, 0x00000000u},\r
1179 \r
1180 /* resvdQdmaChannels */\r
1181 /* 31 0 */\r
1182 {0x00000000u},\r
1183 \r
1184 /* resvdTccs */\r
1185 /* 31 0 63 32 */\r
1186 {0x00000000u, 0x00000000u},\r
1187 },\r
1188 \r
1189 /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
1190 {\r
1191 /* ownPaRAMSets */\r
1192 /* 31 0 63 32 95 64 127 96 */\r
1193 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1194 /* 159 128 191 160 223 192 255 224 */\r
1195 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1196 /* 287 256 319 288 351 320 383 352 */\r
1197 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1198 /* 415 384 447 416 479 448 511 480 */\r
1199 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
1200 \r
1201 /* ownDmaChannels */\r
1202 /* 31 0 63 32 */\r
1203 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1204 \r
1205 /* ownQdmaChannels */\r
1206 /* 31 0 */\r
1207 {0x000000FFu},\r
1208 \r
1209 /* ownTccs */\r
1210 /* 31 0 63 32 */\r
1211 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
1212 \r
1213 /* resvdPaRAMSets */\r
1214 /* 31 0 63 32 95 64 127 96 */\r
1215 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
1216 /* 159 128 191 160 223 192 255 224 */\r
1217 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1218 /* 287 256 319 288 351 320 383 352 */\r
1219 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1220 /* 415 384 447 416 479 448 511 480 */\r
1221 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1222 \r
1223 /* resvdDmaChannels */\r
1224 /* 31 0 63 32 */\r
1225 {0x00u, 0x00u},\r
1226 \r
1227 /* resvdQdmaChannels */\r
1228 /* 31 0 */\r
1229 {0x00u},\r
1230 \r
1231 /* resvdTccs */\r
1232 /* 31 0 63 32 */\r
1233 {0x00u, 0x00u},\r
1234 },\r
1235 \r
1236 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
1237 {\r
1238 /* ownPaRAMSets */\r
1239 /* 31 0 63 32 95 64 127 96 */\r
1240 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1241 /* 159 128 191 160 223 192 255 224 */\r
1242 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1243 /* 287 256 319 288 351 320 383 352 */\r
1244 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1245 /* 415 384 447 416 479 448 511 480 */\r
1246 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1247 \r
1248 /* ownDmaChannels */\r
1249 /* 31 0 63 32 */\r
1250 {0x00000000u, 0x00000000u},\r
1251 \r
1252 /* ownQdmaChannels */\r
1253 /* 31 0 */\r
1254 {0x00000000u},\r
1255 \r
1256 /* ownTccs */\r
1257 /* 31 0 63 32 */\r
1258 {0x00000000u, 0x00000000u},\r
1259 \r
1260 /* resvdPaRAMSets */\r
1261 /* 31 0 63 32 95 64 127 96 */\r
1262 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1263 /* 159 128 191 160 223 192 255 224 */\r
1264 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1265 /* 287 256 319 288 351 320 383 352 */\r
1266 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1267 /* 415 384 447 416 479 448 511 480 */\r
1268 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1269 \r
1270 /* resvdDmaChannels */\r
1271 /* 31 0 63 32 */\r
1272 {0x00000000u, 0x00000000u},\r
1273 \r
1274 /* resvdQdmaChannels */\r
1275 /* 31 0 */\r
1276 {0x00000000u},\r
1277 \r
1278 /* resvdTccs */\r
1279 /* 31 0 63 32 */\r
1280 {0x00000000u, 0x00000000u},\r
1281 },\r
1282 \r
1283 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
1284 {\r
1285 /* ownPaRAMSets */\r
1286 /* 31 0 63 32 95 64 127 96 */\r
1287 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1288 /* 159 128 191 160 223 192 255 224 */\r
1289 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1290 /* 287 256 319 288 351 320 383 352 */\r
1291 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1292 /* 415 384 447 416 479 448 511 480 */\r
1293 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1294 \r
1295 /* ownDmaChannels */\r
1296 /* 31 0 63 32 */\r
1297 {0x00000000u, 0x00000000u},\r
1298 \r
1299 /* ownQdmaChannels */\r
1300 /* 31 0 */\r
1301 {0x00000000u},\r
1302 \r
1303 /* ownTccs */\r
1304 /* 31 0 63 32 */\r
1305 {0x00000000u, 0x00000000u},\r
1306 \r
1307 /* resvdPaRAMSets */\r
1308 /* 31 0 63 32 95 64 127 96 */\r
1309 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1310 /* 159 128 191 160 223 192 255 224 */\r
1311 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1312 /* 287 256 319 288 351 320 383 352 */\r
1313 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1314 /* 415 384 447 416 479 448 511 480 */\r
1315 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1316 \r
1317 /* resvdDmaChannels */\r
1318 /* 31 0 63 32 */\r
1319 {0x00000000u, 0x00000000u},\r
1320 \r
1321 /* resvdQdmaChannels */\r
1322 /* 31 0 */\r
1323 {0x00000000u},\r
1324 \r
1325 /* resvdTccs */\r
1326 /* 31 0 63 32 */\r
1327 {0x00000000u, 0x00000000u},\r
1328 },\r
1329 \r
1330 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1331 {\r
1332 /* ownPaRAMSets */\r
1333 /* 31 0 63 32 95 64 127 96 */\r
1334 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1335 /* 159 128 191 160 223 192 255 224 */\r
1336 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1337 /* 287 256 319 288 351 320 383 352 */\r
1338 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1339 /* 415 384 447 416 479 448 511 480 */\r
1340 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1341 \r
1342 /* ownDmaChannels */\r
1343 /* 31 0 63 32 */\r
1344 {0x00000000u, 0x00000000u},\r
1345 \r
1346 /* ownQdmaChannels */\r
1347 /* 31 0 */\r
1348 {0x00000000u},\r
1349 \r
1350 /* ownTccs */\r
1351 /* 31 0 63 32 */\r
1352 {0x00000000u, 0x00000000u},\r
1353 \r
1354 /* resvdPaRAMSets */\r
1355 /* 31 0 63 32 95 64 127 96 */\r
1356 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1357 /* 159 128 191 160 223 192 255 224 */\r
1358 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1359 /* 287 256 319 288 351 320 383 352 */\r
1360 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1361 /* 415 384 447 416 479 448 511 480 */\r
1362 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1363 \r
1364 /* resvdDmaChannels */\r
1365 /* 31 0 63 32 */\r
1366 {0x00000000u, 0x00000000u},\r
1367 \r
1368 /* resvdQdmaChannels */\r
1369 /* 31 0 */\r
1370 {0x00000000u},\r
1371 \r
1372 /* resvdTccs */\r
1373 /* 31 0 63 32 */\r
1374 {0x00000000u, 0x00000000u},\r
1375 },\r
1376 \r
1377 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1378 {\r
1379 /* ownPaRAMSets */\r
1380 /* 31 0 63 32 95 64 127 96 */\r
1381 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1382 /* 159 128 191 160 223 192 255 224 */\r
1383 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1384 /* 287 256 319 288 351 320 383 352 */\r
1385 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1386 /* 415 384 447 416 479 448 511 480 */\r
1387 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1388 \r
1389 /* ownDmaChannels */\r
1390 /* 31 0 63 32 */\r
1391 {0x00000000u, 0x00000000u},\r
1392 \r
1393 /* ownQdmaChannels */\r
1394 /* 31 0 */\r
1395 {0x00000000u},\r
1396 \r
1397 /* ownTccs */\r
1398 /* 31 0 63 32 */\r
1399 {0x00000000u, 0x00000000u},\r
1400 \r
1401 /* resvdPaRAMSets */\r
1402 /* 31 0 63 32 95 64 127 96 */\r
1403 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1404 /* 159 128 191 160 223 192 255 224 */\r
1405 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1406 /* 287 256 319 288 351 320 383 352 */\r
1407 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1408 /* 415 384 447 416 479 448 511 480 */\r
1409 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1410 \r
1411 /* resvdDmaChannels */\r
1412 /* 31 0 63 32 */\r
1413 {0x00000000u, 0x00000000u},\r
1414 \r
1415 /* resvdQdmaChannels */\r
1416 /* 31 0 */\r
1417 {0x00000000u},\r
1418 \r
1419 /* resvdTccs */\r
1420 /* 31 0 63 32 */\r
1421 {0x00000000u, 0x00000000u},\r
1422 },\r
1423 \r
1424 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1425 {\r
1426 /* ownPaRAMSets */\r
1427 /* 31 0 63 32 95 64 127 96 */\r
1428 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1429 /* 159 128 191 160 223 192 255 224 */\r
1430 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1431 /* 287 256 319 288 351 320 383 352 */\r
1432 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1433 /* 415 384 447 416 479 448 511 480 */\r
1434 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1435 \r
1436 /* ownDmaChannels */\r
1437 /* 31 0 63 32 */\r
1438 {0x00000000u, 0x00000000u},\r
1439 \r
1440 /* ownQdmaChannels */\r
1441 /* 31 0 */\r
1442 {0x00000000u},\r
1443 \r
1444 /* ownTccs */\r
1445 /* 31 0 63 32 */\r
1446 {0x00000000u, 0x00000000u},\r
1447 \r
1448 /* resvdPaRAMSets */\r
1449 /* 31 0 63 32 95 64 127 96 */\r
1450 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1451 /* 159 128 191 160 223 192 255 224 */\r
1452 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1453 /* 287 256 319 288 351 320 383 352 */\r
1454 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1455 /* 415 384 447 416 479 448 511 480 */\r
1456 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1457 \r
1458 /* resvdDmaChannels */\r
1459 /* 31 0 63 32 */\r
1460 {0x00000000u, 0x00000000u},\r
1461 \r
1462 /* resvdQdmaChannels */\r
1463 /* 31 0 */\r
1464 {0x00000000u},\r
1465 \r
1466 /* resvdTccs */\r
1467 /* 31 0 63 32 */\r
1468 {0x00000000u, 0x00000000u},\r
1469 },\r
1470 \r
1471 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1472 {\r
1473 /* ownPaRAMSets */\r
1474 /* 31 0 63 32 95 64 127 96 */\r
1475 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1476 /* 159 128 191 160 223 192 255 224 */\r
1477 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1478 /* 287 256 319 288 351 320 383 352 */\r
1479 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1480 /* 415 384 447 416 479 448 511 480 */\r
1481 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1482 \r
1483 /* ownDmaChannels */\r
1484 /* 31 0 63 32 */\r
1485 {0x00000000u, 0x00000000u},\r
1486 \r
1487 /* ownQdmaChannels */\r
1488 /* 31 0 */\r
1489 {0x00000000u},\r
1490 \r
1491 /* ownTccs */\r
1492 /* 31 0 63 32 */\r
1493 {0x00000000u, 0x00000000u},\r
1494 \r
1495 /* resvdPaRAMSets */\r
1496 /* 31 0 63 32 95 64 127 96 */\r
1497 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1498 /* 159 128 191 160 223 192 255 224 */\r
1499 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1500 /* 287 256 319 288 351 320 383 352 */\r
1501 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1502 /* 415 384 447 416 479 448 511 480 */\r
1503 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1504 \r
1505 /* resvdDmaChannels */\r
1506 /* 31 0 63 32 */\r
1507 {0x00000000u, 0x00000000u},\r
1508 \r
1509 /* resvdQdmaChannels */\r
1510 /* 31 0 */\r
1511 {0x00000000u},\r
1512 \r
1513 /* resvdTccs */\r
1514 /* 31 0 63 32 */\r
1515 {0x00000000u, 0x00000000u},\r
1516 },\r
1517 },\r
1518 };\r
1519 \r
1520 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
1521 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
1522 {\r
1523 /* EDMA3 INSTANCE# 0 */\r
1524 {\r
1525 /* Event to channel map for region 0 */\r
1526 {\r
1527 -1, -1, -1, -1, -1, -1, -1, -1,\r
1528 -1, -1, -1, -1, -1, -1, -1, -1,\r
1529 -1, -1, -1, -1, -1, -1, -1, -1,\r
1530 -1, -1, -1, -1, -1, -1, -1, -1,\r
1531 -1, -1, -1, -1, -1, -1, -1, -1,\r
1532 -1, -1, -1, -1, -1, -1, -1, -1,\r
1533 -1, -1, -1, -1, -1, -1, -1, -1,\r
1534 -1, -1, -1, -1, -1, -1, -1\r
1535 },\r
1536 /* Event to channel map for region 1 */\r
1537 {\r
1538 -1, -1, -1, -1, -1, -1, -1, -1,\r
1539 -1, -1, -1, -1, -1, -1, -1, -1,\r
1540 -1, -1, -1, -1, -1, -1, -1, -1,\r
1541 -1, -1, -1, -1, -1, -1, -1, -1,\r
1542 -1, -1, -1, -1, -1, -1, -1, -1,\r
1543 -1, -1, -1, -1, -1, -1, -1, -1,\r
1544 -1, -1, -1, -1, -1, -1, -1, -1,\r
1545 -1, -1, -1, -1, -1, -1, -1\r
1546 },\r
1547 /* Event to channel map for region 2 */\r
1548 {\r
1549 -1, -1, -1, -1, -1, -1, -1, -1,\r
1550 -1, -1, -1, -1, -1, -1, -1, -1,\r
1551 -1, -1, -1, -1, -1, -1, -1, -1,\r
1552 -1, -1, -1, -1, -1, -1, -1, -1,\r
1553 -1, -1, -1, -1, -1, -1, -1, -1,\r
1554 -1, -1, -1, -1, -1, -1, -1, -1,\r
1555 -1, -1, -1, -1, -1, -1, -1, -1,\r
1556 -1, -1, -1, -1, -1, -1, -1\r
1557 },\r
1558 /* Event to channel map for region 3 */\r
1559 {\r
1560 -1, -1, -1, -1, -1, -1, -1, -1,\r
1561 -1, -1, -1, -1, -1, -1, -1, -1,\r
1562 -1, -1, -1, -1, -1, -1, -1, -1,\r
1563 -1, -1, -1, -1, -1, -1, -1, -1,\r
1564 -1, -1, -1, -1, -1, -1, -1, -1,\r
1565 -1, -1, -1, -1, -1, -1, -1, -1,\r
1566 -1, -1, -1, -1, -1, -1, -1, -1,\r
1567 -1, -1, -1, -1, -1, -1, -1\r
1568 },\r
1569 /* Event to channel map for region 4 */\r
1570 {\r
1571 -1, -1, -1, -1, -1, -1, -1, -1,\r
1572 -1, -1, -1, -1, -1, -1, -1, -1,\r
1573 -1, -1, -1, -1, -1, -1, -1, -1,\r
1574 -1, -1, -1, -1, -1, -1, -1, -1,\r
1575 -1, -1, -1, -1, -1, -1, -1, -1,\r
1576 -1, -1, -1, -1, -1, -1, -1, -1,\r
1577 -1, -1, -1, -1, -1, -1, -1, -1,\r
1578 -1, -1, -1, -1, -1, -1, -1\r
1579 },\r
1580 /* Event to channel map for region 5 */\r
1581 {\r
1582 -1, -1, -1, -1, -1, -1, -1, -1,\r
1583 -1, -1, -1, -1, -1, -1, -1, -1,\r
1584 -1, -1, -1, -1, -1, -1, -1, -1,\r
1585 -1, -1, -1, -1, -1, -1, -1, -1,\r
1586 -1, -1, -1, -1, -1, -1, -1, -1,\r
1587 -1, -1, -1, -1, -1, -1, -1, -1,\r
1588 -1, -1, -1, -1, -1, -1, -1, -1,\r
1589 -1, -1, -1, -1, -1, -1, -1\r
1590 },\r
1591 /* Event to channel map for region 6 */\r
1592 {\r
1593 -1, -1, -1, -1, -1, -1, -1, -1,\r
1594 -1, -1, -1, -1, -1, -1, -1, -1,\r
1595 -1, -1, -1, -1, -1, -1, -1, -1,\r
1596 -1, -1, -1, -1, -1, -1, -1, -1,\r
1597 -1, -1, -1, -1, -1, -1, -1, -1,\r
1598 -1, -1, -1, -1, -1, -1, -1, -1,\r
1599 -1, -1, -1, -1, -1, -1, -1, -1,\r
1600 -1, -1, -1, -1, -1, -1, -1\r
1601 },\r
1602 /* Event to channel map for region 7 */\r
1603 {\r
1604 -1, -1, -1, -1, -1, -1, -1, -1,\r
1605 -1, -1, -1, -1, -1, -1, -1, -1,\r
1606 -1, -1, -1, -1, -1, -1, -1, -1,\r
1607 -1, -1, -1, -1, -1, -1, -1, -1,\r
1608 -1, -1, -1, -1, -1, -1, -1, -1,\r
1609 -1, -1, -1, -1, -1, -1, -1, -1,\r
1610 -1, -1, -1, -1, -1, -1, -1, -1,\r
1611 -1, -1, -1, -1, -1, -1, -1\r
1612 },\r
1613 }\r
1614 };\r
1615 \r
1616 /* End of File */\r
1617 \r