[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_int_reg.c
1 /*
2 * sample_tda2xx_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/family/c64p/EventCombiner.h>
41 #include <ti/sysbios/family/c64p/Hwi.h>
42 #include <ti/sysbios/family/shared/vayu/IntXbar.h>
44 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
46 /**
47 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
48 * (Not all TC error ISRs need to be registered, register only for the
49 * available Transfer Controllers).
50 */
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
52 {
53 &lisrEdma3TC0ErrHandler0,
54 &lisrEdma3TC1ErrHandler0,
55 &lisrEdma3TC2ErrHandler0,
56 &lisrEdma3TC3ErrHandler0,
57 &lisrEdma3TC4ErrHandler0,
58 &lisrEdma3TC5ErrHandler0,
59 &lisrEdma3TC6ErrHandler0,
60 &lisrEdma3TC7ErrHandler0,
61 };
63 extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
64 extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
65 extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
66 extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
67 extern uint32_t ccXferCompIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
68 extern uint32_t ccCompEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
69 extern uint32_t ccErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES];
70 extern uint32_t ccErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES];
71 extern uint32_t tcErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
72 extern uint32_t tcErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
74 /**
75 * Variables which will be used internally for referring the hardware interrupt
76 * for various EDMA3 interrupts.
77 */
78 extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
79 extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
80 extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
82 extern uint32_t dsp_num;
84 /* External Instance Specific Configuration Structure */
85 extern EDMA3_DRV_GblXbarToChanConfigParams
86 sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
88 typedef struct {
89 volatile Uint32 TPCC_EVTMUX[32];
90 } CSL_IntmuxRegs;
92 typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;
94 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
95 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
96 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
98 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
100 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
103 #define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127U)
104 #define EDMA3_NUM_TCC (64U)
106 #define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)
108 /*
109 * Forward decleration
110 */
111 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
112 uint32_t *chanNum,
113 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
114 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
115 uint32_t chanNum);
117 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
118 uint32_t edma3Id);
120 /** To Register the ISRs with the underlying OS, if required. */
121 void registerEdma3Interrupts (uint32_t edma3Id);
122 /** To Unregister the ISRs with the underlying OS, if previously registered. */
123 void unregisterEdma3Interrupts (uint32_t edma3Id);
126 /** To Register the ISRs with the underlying OS, if required. */
127 void registerEdma3Interrupts (uint32_t edma3Id)
128 {
129 static UInt32 cookie = 0;
130 uint32_t numTc = 0;
131 /* Do the xbar configuration only for edma inst 0 */
132 /* EDMA inst 1 is for DSP1 EDMA which has direct interrupt mapping */
133 if(edma3Id == 0)
134 {
135 IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
136 IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
137 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
138 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
139 }
141 /* Disabling the global interrupts */
142 cookie = Hwi_disable();
144 /* Enable the Xfer Completion Event Interrupt */
145 EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
146 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
147 edma3Id, (Bool)1);
148 EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
150 /* Enable the CC Error Event Interrupt */
151 EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
152 (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
153 edma3Id, (Bool)1);
154 EventCombiner_enableEvent(ccErrorInt[edma3Id]);
156 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
157 while (numTc < numEdma3Tc[edma3Id])
158 {
159 EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
160 (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
161 edma3Id, (Bool)1);
162 EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
163 numTc++;
164 }
166 /**
167 * Enabling the HWI_ID.
168 * EDMA3 interrupts (transfer completion, CC error etc.)
169 * correspond to different ECM events (SoC specific). These ECM events come
170 * under ECM block XXX (handling those specific ECM events). Normally, block
171 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
172 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
173 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
174 * mapped HWI_INT YYY, one should use the corresponding bitmask in the
175 * API C64_enableIER(), in which the YYY bit is SET.
176 */
177 if(edma3Id == 0)
178 {
179 Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
180 Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
181 Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
182 }
184 /* Restore interrupts */
185 Hwi_restore(cookie);
186 }
188 /** To Unregister the ISRs with the underlying OS, if previously registered. */
189 void unregisterEdma3Interrupts (uint32_t edma3Id)
190 {
191 static UInt32 cookiee = 0;
192 uint32_t numTc = 0;
194 /* Disabling the global interrupts */
195 cookiee = Hwi_disable();
197 /* Disable the Xfer Completion Event Interrupt */
198 EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
200 /* Disable the CC Error Event Interrupt */
201 EventCombiner_disableEvent(ccErrorInt[edma3Id]);
203 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
204 while (numTc < numEdma3Tc[edma3Id])
205 {
206 EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
207 numTc++;
208 }
210 /* Restore interrupts */
211 Hwi_restore(cookiee);
212 }
214 /**
215 * \brief sampleMapXbarEvtToChan
216 *
217 * This function reads from the sample configuration structure which specifies
218 * cross bar events mapped to DMA channel.
219 *
220 * \return EDMA3_DRV_SOK if success, else error code
221 */
222 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
223 uint32_t *chanNum,
224 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
225 {
226 EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
227 uint32_t xbarEvtNum = 0;
228 int32_t edmaChanNum = 0;
230 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&
231 (chanNum != NULL) &&
232 (edmaGblXbarConfig != NULL))
233 {
234 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
235 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
236 if (edmaChanNum != -1)
237 {
238 *chanNum = edmaChanNum;
239 edma3Result = EDMA3_DRV_SOK;
240 }
241 }
242 return (edma3Result);
243 }
246 /**
247 * \brief sampleConfigScr
248 *
249 * This function configures control config registers for the cross bar events
250 * mapped to the EDMA channel.
251 *
252 * \return EDMA3_DRV_SOK if success, else error code
253 */
254 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
255 uint32_t chanNum)
256 {
257 EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
258 uint32_t scrChanOffset = 0;
259 uint32_t scrRegOffset = 0;
260 uint32_t xBarEvtNum = 0;
261 CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
264 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&
265 (chanNum < EDMA3_NUM_TCC))
266 {
267 scrRegOffset = chanNum / 2U;
268 scrChanOffset = chanNum - (scrRegOffset * 2U);
269 xBarEvtNum = eventNum + 1U;
271 switch(scrChanOffset)
272 {
273 case 0:
274 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
275 (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
276 break;
277 case 1U:
278 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
279 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
280 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
281 break;
282 default:
283 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
284 break;
285 }
286 }
287 else
288 {
289 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
290 }
291 return edma3Result;
292 }
294 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
295 uint32_t edma3Id)
296 {
297 EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
298 const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
299 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
300 if (hEdma != NULL)
301 {
302 retVal = EDMA3_DRV_initXbarEventMap(hEdma,
303 sampleXbarToChanConfig,
304 &sampleMapXbarEvtToChan,
305 &sampleConfigScr);
306 }
308 return retVal;
309 }
311 /**
312 * \brief enableXferCompInterrupt
313 *
314 * This function enables the tranfer completion interrupt of EDMA3.
315 *
316 * \return nil
317 */
318 void enableXferCompInterrupt(uint32_t edma3Id)
319 {
320 EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
321 }
323 /**
324 * \brief disableXferCompInterrupt
325 *
326 * This function disables the tranfer completion interrupt of EDMA3.
327 *
328 * \return nil
329 */
330 void disableXferCompInterrupt(uint32_t edma3Id)
331 {
332 EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
333 }
335 /**
336 * \brief enableErrorInterrupt
337 *
338 * This function enables the error interrupt of EDMA3.
339 *
340 * \return nil
341 */
342 void enableErrorInterrupt(uint32_t edma3Id)
343 {
344 EventCombiner_enableEvent(ccErrorInt[edma3Id]);
345 }
347 /**
348 * \brief disableErrorInterrupt
349 *
350 * This function disables the error interrupt of EDMA3.
351 *
352 * \return nil
353 */
354 void disableErrorInterrupt(uint32_t edma3Id)
355 {
356 EventCombiner_disableEvent(ccErrorInt[edma3Id]);
357 }