[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda3xx_arm_int_reg.c
1 /*
2 * sample_tda3xx_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/hal/Hwi.h>
41 #include <ti/sysbios/family/shared/vayu/IntXbar.h>
42 #include <ti/sysbios/family/arm/a15/Mmu.h>
43 #include <xdc/runtime/Error.h>
44 #include <xdc/runtime/System.h>
46 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
48 /**
49 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
50 * (Not all TC error ISRs need to be registered, register only for the
51 * available Transfer Controllers).
52 */
53 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
54 {
55 &lisrEdma3TC0ErrHandler0,
56 &lisrEdma3TC1ErrHandler0,
57 &lisrEdma3TC2ErrHandler0,
58 &lisrEdma3TC3ErrHandler0,
59 &lisrEdma3TC4ErrHandler0,
60 &lisrEdma3TC5ErrHandler0,
61 &lisrEdma3TC6ErrHandler0,
62 &lisrEdma3TC7ErrHandler0,
63 };
65 extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
66 extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
67 extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
68 extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
69 extern uint32_t ccXferCompIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
70 extern uint32_t ccCompEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
71 extern uint32_t ccErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES];
72 extern uint32_t ccErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES];
73 extern uint32_t tcErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
74 extern uint32_t tcErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
76 /**
77 * Variables which will be used internally for referring the hardware interrupt
78 * for various EDMA3 interrupts.
79 */
80 extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
81 extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
82 extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
84 extern uint32_t dsp_num;
85 /* This variable has to be used as an extern */
86 uint32_t gpp_num = 0;
88 Hwi_Handle hwiCCXferCompInt;
89 Hwi_Handle hwiCCErrInt;
90 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
92 /* External Instance Specific Configuration Structure */
93 extern EDMA3_DRV_GblXbarToChanConfigParams
94 sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
96 typedef struct {
97 volatile Uint32 TPCC_EVTMUX[32];
98 } CSL_IntmuxRegs;
100 typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;
102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
111 #define EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX (127U)
112 #define EDMA3_NUM_TCC (64U)
114 #define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)
115 /*
116 * Forward decleration
117 */
118 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
119 uint32_t *chanNum,
120 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
121 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
122 uint32_t chanNum);
124 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
126 /** To Register the ISRs with the underlying OS, if required. */
127 void registerEdma3Interrupts (uint32_t edma3Id);
129 /** To Unregister the ISRs with the underlying OS, if previously registered. */
130 void unregisterEdma3Interrupts (uint32_t edma3Id);
132 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
133 uint32_t edma3Id);
135 /** To Register the ISRs with the underlying OS, if required. */
136 void registerEdma3Interrupts (uint32_t edma3Id)
137 {
138 static UInt32 cookie = 0;
139 uint32_t numTc = 0;
141 /*
142 * Skip these interrupt xbar configuration.
143 * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.
144 */
145 if ((edma3Id != 2U) && (dsp_num != 1U))
146 {
147 IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
148 IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
149 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
150 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
151 }
153 Hwi_Params hwiParams;
154 Error_Block eb;
156 /* Initialize the Error Block */
157 Error_init(&eb);
159 /* Disabling the global interrupts */
160 cookie = Hwi_disable();
162 /* Initialize the HWI parameters with user specified values */
163 Hwi_Params_init(&hwiParams);
165 /* argument for the ISR */
166 hwiParams.arg = edma3Id;
167 /* set the priority ID */
168 /* hwiParams.priority = hwIntXferComp[edma3Id]; */
170 hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
171 ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
172 (const Hwi_Params *) (&hwiParams),
173 &eb);
174 if ((bool)TRUE == Error_check(&eb))
175 {
176 System_printf("HWI Create Failed\n",Error_getCode(&eb));
177 }
179 /* Initialize the HWI parameters with user specified values */
180 Hwi_Params_init(&hwiParams);
181 /* argument for the ISR */
182 hwiParams.arg = edma3Id;
183 /* set the priority ID */
184 /* hwiParams.priority = hwIntCcErr[edma3Id]; */
186 hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
187 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
188 (const Hwi_Params *) (&hwiParams),
189 &eb);
191 if ((bool)TRUE == Error_check(&eb))
192 {
193 System_printf("HWI Create Failed\n",Error_getCode(&eb));
194 }
196 while (numTc < numEdma3Tc[edma3Id])
197 {
198 /* Initialize the HWI parameters with user specified values */
199 Hwi_Params_init(&hwiParams);
200 /* argument for the ISR */
201 hwiParams.arg = edma3Id;
202 /* set the priority ID */
203 /* hwiParams.priority = hwIntTcErr[edma3Id]; */
205 hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
206 (ptrEdma3TcIsrHandler[numTc]),
207 (const Hwi_Params *) (&hwiParams),
208 &eb);
209 if ((bool)TRUE == Error_check(&eb))
210 {
211 System_printf("HWI Create Failed\n",Error_getCode(&eb));
212 }
213 numTc++;
214 }
216 Hwi_enableInterrupt(ccErrorInt[edma3Id]);
217 Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
218 numTc = 0;
219 while (numTc < numEdma3Tc[edma3Id])
220 {
221 Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
222 numTc++;
223 }
224 /* Restore interrupts */
225 Hwi_restore(cookie);
226 }
228 /** To Unregister the ISRs with the underlying OS, if previously registered. */
229 void unregisterEdma3Interrupts (uint32_t edma3Id)
230 {
231 static UInt32 cookiee = 0;
232 uint32_t numTc = 0;
234 /* Disabling the global interrupts */
235 cookiee = Hwi_disable();
237 Hwi_delete(&hwiCCXferCompInt);
238 Hwi_delete(&hwiCCErrInt);
239 while (numTc < numEdma3Tc[edma3Id])
240 {
241 Hwi_delete(&hwiTCErrInt[numTc]);
242 numTc++;
243 }
244 /* Restore interrupts */
245 Hwi_restore(cookiee);
246 }
248 /**
249 * \brief sampleMapXbarEvtToChan
250 *
251 * This function reads from the sample configuration structure which specifies
252 * cross bar events mapped to DMA channel.
253 *
254 * \return EDMA3_DRV_SOK if success, else error code
255 */
256 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
257 uint32_t *chanNum,
258 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
259 {
260 EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
261 uint32_t xbarEvtNum = 0;
262 int32_t edmaChanNum = 0;
264 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX) &&
265 (chanNum != NULL) &&
266 (edmaGblXbarConfig != NULL))
267 {
268 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
269 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
270 if (edmaChanNum != -1)
271 {
272 *chanNum = edmaChanNum;
273 edma3Result = EDMA3_DRV_SOK;
274 }
275 }
276 return (edma3Result);
277 }
280 /**
281 * \brief sampleConfigScr
282 *
283 * This function configures control config registers for the cross bar events
284 * mapped to the EDMA channel.
285 *
286 * \return EDMA3_DRV_SOK if success, else error code
287 */
288 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
289 uint32_t chanNum)
290 {
291 EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
292 uint32_t scrChanOffset = 0;
293 uint32_t scrRegOffset = 0;
294 uint32_t xBarEvtNum = 0;
295 CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
298 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX) &&
299 (chanNum < EDMA3_NUM_TCC))
300 {
301 scrRegOffset = chanNum / 2U;
302 scrChanOffset = chanNum - (scrRegOffset * 2U);
303 xBarEvtNum = eventNum + 1U;
305 switch(scrChanOffset)
306 {
307 case 0:
308 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
309 (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
310 break;
311 case 1U:
312 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
313 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
314 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
315 break;
316 default:
317 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
318 break;
319 }
320 }
321 else
322 {
323 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
324 }
325 return edma3Result;
326 }
328 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
329 uint32_t edma3Id)
330 {
331 EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
332 const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
333 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
334 if (hEdma != NULL)
335 {
336 retVal = EDMA3_DRV_initXbarEventMap(hEdma,
337 sampleXbarToChanConfig,
338 (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan,
339 (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);
340 }
342 return retVal;
343 }
345 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
346 {
347 #ifdef EDMA3_DRV_DEBUG
348 /* Added to fix Misra C error */
349 printf("memory Protection error");
350 #endif
351 }