[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda3xx_int_reg.c
1 /*
2 * sample_tda2xx_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/family/c64p/EventCombiner.h>
41 #include <ti/sysbios/family/c64p/Hwi.h>
42 #include <ti/sysbios/family/shared/vayu/IntXbar.h>
44 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
46 /**
47 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
48 * (Not all TC error ISRs need to be registered, register only for the
49 * available Transfer Controllers).
50 */
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
52 {
53 &lisrEdma3TC0ErrHandler0,
54 &lisrEdma3TC1ErrHandler0,
55 &lisrEdma3TC2ErrHandler0,
56 &lisrEdma3TC3ErrHandler0,
57 &lisrEdma3TC4ErrHandler0,
58 &lisrEdma3TC5ErrHandler0,
59 &lisrEdma3TC6ErrHandler0,
60 &lisrEdma3TC7ErrHandler0,
61 };
63 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
64 extern unsigned int ccErrorInt[];
65 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
66 extern unsigned int numEdma3Tc[];
67 extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
68 extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
69 extern unsigned int ccErrorIntXbarInstNo[];
70 extern unsigned int ccErrEdmaXbarIndex[];
71 extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
72 extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
74 /**
75 * Variables which will be used internally for referring the hardware interrupt
76 * for various EDMA3 interrupts.
77 */
78 extern unsigned int hwIntXferComp[];
79 extern unsigned int hwIntCcErr[];
80 extern unsigned int hwIntTcErr[];
82 extern unsigned int dsp_num;
84 /* External Instance Specific Configuration Structure */
85 extern EDMA3_DRV_GblXbarToChanConfigParams
86 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
88 typedef struct {
89 volatile Uint32 TPCC_EVTMUX[32];
90 } CSL_IntmuxRegs;
92 typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;
94 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
95 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
96 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
98 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
100 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
103 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)
104 #define EDMA3_NUM_TCC (64u)
106 #define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)
108 /*
109 * Forward decleration
110 */
111 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
112 unsigned int *chanNum,
113 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
114 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
115 unsigned int chanNum);
118 /** To Register the ISRs with the underlying OS, if required. */
119 void registerEdma3Interrupts (unsigned int edma3Id)
120 {
121 static UInt32 cookie = 0;
122 unsigned int numTc = 0;
123 /* Do the xbar configuration only for edma inst 0 */
124 /* EDMA inst 1 is for DSP1 EDMA which has direct interrupt mapping */
125 if(edma3Id == 0)
126 {
127 IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
128 IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
129 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
130 IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
131 }
133 /* Disabling the global interrupts */
134 cookie = Hwi_disable();
136 /* Enable the Xfer Completion Event Interrupt */
137 EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
138 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
139 edma3Id, 1);
140 EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
142 /* Enable the CC Error Event Interrupt */
143 EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
144 (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
145 edma3Id, 1);
146 EventCombiner_enableEvent(ccErrorInt[edma3Id]);
148 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
149 while (numTc < numEdma3Tc[edma3Id])
150 {
151 EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
152 (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
153 edma3Id, 1);
154 EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
155 numTc++;
156 }
158 /**
159 * Enabling the HWI_ID.
160 * EDMA3 interrupts (transfer completion, CC error etc.)
161 * correspond to different ECM events (SoC specific). These ECM events come
162 * under ECM block XXX (handling those specific ECM events). Normally, block
163 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
164 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
165 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
166 * mapped HWI_INT YYY, one should use the corresponding bitmask in the
167 * API C64_enableIER(), in which the YYY bit is SET.
168 */
169 if(edma3Id == 0)
170 {
171 Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
172 Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
173 Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
174 }
176 /* Restore interrupts */
177 Hwi_restore(cookie);
178 }
180 /** To Unregister the ISRs with the underlying OS, if previously registered. */
181 void unregisterEdma3Interrupts (unsigned int edma3Id)
182 {
183 static UInt32 cookie = 0;
184 unsigned int numTc = 0;
186 /* Disabling the global interrupts */
187 cookie = Hwi_disable();
189 /* Disable the Xfer Completion Event Interrupt */
190 EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
192 /* Disable the CC Error Event Interrupt */
193 EventCombiner_disableEvent(ccErrorInt[edma3Id]);
195 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
196 while (numTc < numEdma3Tc[edma3Id])
197 {
198 EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
199 numTc++;
200 }
202 /* Restore interrupts */
203 Hwi_restore(cookie);
204 }
206 /**
207 * \brief sampleMapXbarEvtToChan
208 *
209 * This function reads from the sample configuration structure which specifies
210 * cross bar events mapped to DMA channel.
211 *
212 * \return EDMA3_DRV_SOK if success, else error code
213 */
214 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
215 unsigned int *chanNum,
216 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
217 {
218 EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
219 unsigned int xbarEvtNum = 0;
220 int edmaChanNum = 0;
222 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
223 (chanNum != NULL) &&
224 (edmaGblXbarConfig != NULL))
225 {
226 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
227 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
228 if (edmaChanNum != -1)
229 {
230 *chanNum = edmaChanNum;
231 edma3Result = EDMA3_DRV_SOK;
232 }
233 }
234 return (edma3Result);
235 }
238 /**
239 * \brief sampleConfigScr
240 *
241 * This function configures control config registers for the cross bar events
242 * mapped to the EDMA channel.
243 *
244 * \return EDMA3_DRV_SOK if success, else error code
245 */
246 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
247 unsigned int chanNum)
248 {
249 EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
250 unsigned int scrChanOffset = 0;
251 unsigned int scrRegOffset = 0;
252 unsigned int xBarEvtNum = 0;
253 CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
256 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
257 (chanNum < EDMA3_NUM_TCC))
258 {
259 scrRegOffset = chanNum / 2;
260 scrChanOffset = chanNum - (scrRegOffset * 2);
261 xBarEvtNum = (eventNum + 1);
263 switch(scrChanOffset)
264 {
265 case 0:
266 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
267 (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
268 break;
269 case 1:
270 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
271 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
272 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
273 break;
274 default:
275 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
276 break;
277 }
278 }
279 else
280 {
281 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
282 }
283 return edma3Result;
284 }
286 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
287 unsigned int edma3Id)
288 {
289 EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
290 const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
291 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
292 if (hEdma != NULL)
293 {
294 retVal = EDMA3_DRV_initXbarEventMap(hEdma,
295 sampleXbarToChanConfig,
296 &sampleMapXbarEvtToChan,
297 &sampleConfigScr);
298 }
300 return retVal;
301 }