packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_cfg.c

   1 /*
   2  * sample_ti814x_cfg.c
   3  *
   4  * SoC specific EDMA3 hardware related information like number of transfer
   5  * controllers, various interrupt ids etc. It is used while interrupts
   6  * enabling / disabling. It needs to be ported for different SoCs.
   7  *
   8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   9  *
  10  *
  11  *  Redistribution and use in source and binary forms, with or without
  12  *  modification, are permitted provided that the following conditions
  13  *  are met:
  14  *
  15  *    Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  *
  18  *    Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the
  21  *    distribution.
  22  *
  23  *    Neither the name of Texas Instruments Incorporated nor the names of
  24  *    its contributors may be used to endorse or promote products derived
  25  *    from this software without specific prior written permission.
  26  *
  27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39 */
  40
  41 #include <ti/sdo/edma3/drv/edma3_drv.h>
  42
  43 /* Number of EDMA3 controllers present in the system */
  44 #define NUM_EDMA3_INSTANCES         1u
  45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
  46
  47 /* Number of DSPs present in the system */
  48 #define NUM_DSPS                    0u
  49 const unsigned int numDsps = NUM_DSPS;
  50
  51 /* Determine the processor id by reading DNUM register. */
  52 unsigned short determineProcId()
  53 {
  54     return 0;
  55 }
  56
  57 signed char*  getGlobalAddr(signed char* addr)
  58 {
  59      return (addr); /* The address is already a global address */
  60 }
  61 unsigned short isGblConfigRequired(unsigned int dspNum)
  62 {
  63     (void) dspNum;
  64     return 0;
  65 }
  66
  67 /* Semaphore handles */
  68 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  69
  70 /** Number of PaRAM Sets available                                            */
  71 #define EDMA3_NUM_PARAMSET                              (512u)
  72
  73 /** Number of TCCS available                                                  */
  74 #define EDMA3_NUM_TCC                                   (64u)
  75
  76 /** Number of DMA Channels available                                          */
  77 #define EDMA3_NUM_DMA_CHANNELS                          (64u)
  78
  79 /** Number of QDMA Channels available                                         */
  80 #define EDMA3_NUM_QDMA_CHANNELS                         (8u)
  81
  82 /** Number of Event Queues available                                          */
  83 #define EDMA3_0_NUM_EVTQUE                              (4u)
  84
  85 /** Number of Transfer Controllers available                                  */
  86 #define EDMA3_0_NUM_TC                                  (4u)
  87
  88 /** Number of Regions                                                         */
  89 #define EDMA3_0_NUM_REGIONS                             (4u)
  90
  91
  92 /** Interrupt no. for Transfer Completion                                     */
  93 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (12u)
  94 /** Interrupt no. for CC Error                                                */
  95 #define EDMA3_0_CC_ERROR_INT                            (14u)
  96 /** Interrupt no. for TCs Error                                               */
  97 #define EDMA3_0_TC0_ERROR_INT                           (112u)
  98 #define EDMA3_0_TC1_ERROR_INT                           (113u)
  99 #define EDMA3_0_TC2_ERROR_INT                           (114u)
 100 #define EDMA3_0_TC3_ERROR_INT                           (115u)
 101 #define EDMA3_0_TC4_ERROR_INT                           (0u)
 102 #define EDMA3_0_TC5_ERROR_INT                           (0u)
 103 #define EDMA3_0_TC6_ERROR_INT                           (0u)
 104 #define EDMA3_0_TC7_ERROR_INT                           (0u)
 105
 106 /**
 107  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
 108  * ECM events (SoC specific). These ECM events come
 109  * under ECM block XXX (handling those specific ECM events). Normally, block
 110  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
 111  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
 112  * is mapped to a specific HWI_INT YYY in the tcf file.
 113  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
 114  * to transfer completion interrupt.
 115  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
 116  * to CC error interrupts.
 117  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
 118  * to TC error interrupts.
 119  */
 120 /* EDMA 0 */
 121
 122 #define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
 123 #define EDMA3_0_HWI_INT_CC_ERR                              (7u)
 124 #define EDMA3_0_HWI_INT_TC0_ERR                             (10u)
 125 #define EDMA3_0_HWI_INT_TC1_ERR                             (10u)
 126 #define EDMA3_0_HWI_INT_TC2_ERR                             (10u)
 127 #define EDMA3_0_HWI_INT_TC3_ERR                             (10u)
 128
 129
 130 /**
 131  * \brief Mapping of DMA channels 0-31 to Hardware Events from
 132  * various peripherals, which use EDMA for data transfer.
 133  * All channels need not be mapped, some can be free also.
 134  * 1: Mapped
 135  * 0: Not mapped
 136  *
 137  * This mapping will be used to allocate DMA channels when user passes
 138  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 139  * copy). The same mapping is used to allocate the TCC when user passes
 140  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 141  *
 142  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 143  */
 144                                                       /* 31     0 */
 145 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00u)  /* TBD */
 146
 147
 148 /**
 149  * \brief Mapping of DMA channels 32-63 to Hardware Events from
 150  * various peripherals, which use EDMA for data transfer.
 151  * All channels need not be mapped, some can be free also.
 152  * 1: Mapped
 153  * 0: Not mapped
 154  *
 155  * This mapping will be used to allocate DMA channels when user passes
 156  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 157  * copy). The same mapping is used to allocate the TCC when user passes
 158  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 159  *
 160  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 161  */
 162 /* DMA channels 32-63 DOES NOT exist in omapl138. */
 163 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF003C00u) /* TBD */
 164
 165
 166 /* Variable which will be used internally for referring number of Event Queues*/
 167 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
 168                                                         EDMA3_0_NUM_EVTQUE,
 169                                                     };
 170
 171 /* Variable which will be used internally for referring number of TCs.        */
 172 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
 173                                                     EDMA3_0_NUM_TC,
 174                                                 };
 175
 176 /**
 177  * Variable which will be used internally for referring transfer completion
 178  * interrupt.
 179  */
 180 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 181 {
 182     {
 183         EDMA3_0_CC_XFER_COMPLETION_INT, 0, 0u, 0u, 0u, 0u, 0u, 0u,
 184     },
 185 };
 186
 187 /**
 188  * Variable which will be used internally for referring channel controller's
 189  * error interrupt.
 190  */
 191 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
 192                                                     EDMA3_0_CC_ERROR_INT,
 193                                                };
 194
 195 /**
 196  * Variable which will be used internally for referring transfer controllers'
 197  * error interrupts.
 198  */
 199 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
 200 {
 201    {
 202        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
 203        EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
 204        EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
 205        EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
 206    }
 207 };
 208
 209 /**
 210  * Variables which will be used internally for referring the hardware interrupt
 211  * for various EDMA3 interrupts.
 212  */
 213 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
 214                                                     EDMA3_0_HWI_INT_XFER_COMP
 215                                                   };
 216
 217 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
 218                                                    EDMA3_0_HWI_INT_CC_ERR
 219                                                };
 220
 221 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
 222                                                      {
 223                                                         EDMA3_0_HWI_INT_TC0_ERR,
 224                                                         EDMA3_0_HWI_INT_TC1_ERR,
 225                                                         EDMA3_0_HWI_INT_TC2_ERR,
 226                                                         EDMA3_0_HWI_INT_TC3_ERR
 227                                                      }
 228                                                };
 229
 230 /* Driver Object Initialization Configuration */
 231 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
 232 {
 233     {
 234         /* EDMA3 INSTANCE# 0 */
 235         /** Total number of DMA Channels supported by the EDMA3 Controller    */
 236         EDMA3_NUM_DMA_CHANNELS,
 237         /** Total number of QDMA Channels supported by the EDMA3 Controller   */
 238         EDMA3_NUM_QDMA_CHANNELS,
 239         /** Total number of TCCs supported by the EDMA3 Controller            */
 240         EDMA3_NUM_TCC,
 241         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
 242         EDMA3_NUM_PARAMSET,
 243         /** Total number of Event Queues in the EDMA3 Controller              */
 244         EDMA3_0_NUM_EVTQUE,
 245         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
 246         EDMA3_0_NUM_TC,
 247         /** Number of Regions on this EDMA3 controller                        */
 248         EDMA3_0_NUM_REGIONS,
 249
 250         /**
 251          * \brief Channel mapping existence
 252          * A value of 0 (No channel mapping) implies that there is fixed association
 253          * for a channel number to a parameter entry number or, in other words,
 254          * PaRAM entry n corresponds to channel n.
 255          */
 256         1u,
 257
 258         /** Existence of memory protection feature */
 259         0u,
 260
 261         /** Global Register Region of CC Registers */
 262         (void *)0x49000000u,
 263         /** Transfer Controller (TC) Registers */
 264         {
 265             (void *)0x49800000u,
 266             (void *)0x49900000u,
 267             (void *)0x49A00000u,
 268             (void *)0x49B00000u,
 269             (void *)NULL,
 270             (void *)NULL,
 271             (void *)NULL,
 272             (void *)NULL
 273         },
 274         /** Interrupt no. for Transfer Completion */
 275         EDMA3_0_CC_XFER_COMPLETION_INT,
 276         /** Interrupt no. for CC Error */
 277         EDMA3_0_CC_ERROR_INT,
 278         /** Interrupt no. for TCs Error */
 279         {
 280             EDMA3_0_TC0_ERROR_INT,
 281             EDMA3_0_TC1_ERROR_INT,
 282             EDMA3_0_TC2_ERROR_INT,
 283             EDMA3_0_TC3_ERROR_INT,
 284             EDMA3_0_TC4_ERROR_INT,
 285             EDMA3_0_TC5_ERROR_INT,
 286             EDMA3_0_TC6_ERROR_INT,
 287             EDMA3_0_TC7_ERROR_INT
 288         },
 289
 290         /**
 291          * \brief EDMA3 TC priority setting
 292          *
 293          * User can program the priority of the Event Queues
 294          * at a system-wide level.  This means that the user can set the
 295          * priority of an IO initiated by either of the TCs (Transfer Controllers)
 296          * relative to IO initiated by the other bus masters on the
 297          * device (ARM, DSP, USB, etc)
 298          */
 299         {
 300             0u,
 301             1u,
 302             2u,
 303             3u,
 304             0u,
 305             0u,
 306             0u,
 307             0u
 308         },
 309         /**
 310          * \brief To Configure the Threshold level of number of events
 311          * that can be queued up in the Event queues. EDMA3CC error register
 312          * (CCERR) will indicate whether or not at any instant of time the
 313          * number of events queued up in any of the event queues exceeds
 314          * or equals the threshold/watermark value that is set
 315          * in the queue watermark threshold register (QWMTHRA).
 316          */
 317         {
 318             16u,
 319             16u,
 320             16u,
 321             16u,
 322             0u,
 323             0u,
 324             0u,
 325             0u
 326         },
 327
 328         /**
 329          * \brief To Configure the Default Burst Size (DBS) of TCs.
 330          * An optimally-sized command is defined by the transfer controller
 331          * default burst size (DBS). Different TCs can have different
 332          * DBS values. It is defined in Bytes.
 333          */
 334             {
 335             16u,
 336             16u,
 337             0u,
 338             0u,
 339             0u,
 340             0u,
 341             0u,
 342             0u
 343             },
 344
 345         /**
 346          * \brief Mapping from each DMA channel to a Parameter RAM set,
 347          * if it exists, otherwise of no use.
 348          */
 349             {
 350             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
 351             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
 352             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
 353             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
 354             32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
 355             40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
 356             48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
 357             56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
 358             },
 359
 360          /**
 361           * \brief Mapping from each DMA channel to a TCC. This specific
 362           * TCC code will be returned when the transfer is completed
 363           * on the mapped channel.
 364           */
 365             {
 366             0u, 1u, 2u, 3u,
 367             4u, 5u, 6u, 7u,
 368             8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 369             12u, 13u, 14u, 15u,
 370             16u, 17u, 18u, 19u,
 371             20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 372             24u, 25u, 26u, 27u,
 373             28u, 29u, 30u, 31u,
 374             32u, 33u, 34u, 35u,
 375             36u, 37u, 38u, 39u,
 376             40u, 41u, 42u, 43u,
 377             44u, 45u, 46u, 47u,
 378             48u, 49u, 50u, 51u,
 379             52u, 53u, 54u, 55u,
 380             56u, 57u, 58u, 59u,
 381             60u, 61u, 62u, 63u
 382             },
 383
 384         /**
 385          * \brief Mapping of DMA channels to Hardware Events from
 386          * various peripherals, which use EDMA for data transfer.
 387          * All channels need not be mapped, some can be free also.
 388          */
 389             {
 390             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
 391             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
 392             }
 393         },
 394 };
 395
 396
 397 /* Driver Instance Initialization Configuration */
 398 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 399 {
 400     /* EDMA3 INSTANCE# 0 */
 401     {
 402         /* Resources owned/reserved by region 0 */
 403         {
 404             /* ownPaRAMSets */
 405             /* 31     0     63    32     95    64     127   96 */
 406             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 407             /* 159  128     191  160     223  192     255  224 */
 408              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 409             /* 287  256     319  288     351  320     383  352 */
 410              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 411             /* 415  384     447  416     479  448     511  480 */
 412              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 413
 414             /* ownDmaChannels */
 415             /* 31     0     63    32 */
 416             {0xFFFFFFFFu, 0xFFFFFFFFu},
 417
 418             /* ownQdmaChannels */
 419             /* 31     0 */
 420             {0x000000FFu},
 421
 422             /* ownTccs */
 423             /* 31     0     63    32 */
 424             {0xFFFFFFFFu, 0xFFFFFFFFu},
 425
 426             /* Resources reserved by Region 1 */
 427             /* resvdPaRAMSets */
 428             /* 31     0     63    32     95    64     127   96 */
 429             {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 430             /* 159  128     191  160     223  192     255  224 */
 431              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 432             /* 287  256     319  288     351  320     383  352 */
 433              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 434             /* 415  384     447  416     479  448     511  480 */
 435              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 436
 437             /* resvdDmaChannels */
 438             /* 31       0 */
 439             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
 440             /* 63..32 */
 441             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
 442
 443             /* resvdQdmaChannels */
 444             /* 31     0 */
 445             {0x00000000u},
 446
 447             /* resvdTccs */
 448             /* 31       0 */
 449             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
 450             /* 63..32 */
 451             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
 452         },
 453         /* Resources owned/reserved by region 1 */
 454         {
 455             /* ownPaRAMSets */
 456             /* 31     0     63    32     95    64     127   96 */
 457             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 458             /* 159  128     191  160     223  192     255  224 */
 459              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 460             /* 287  256     319  288     351  320     383  352 */
 461              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 462             /* 415  384     447  416     479  448     511  480 */
 463              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 464
 465             /* ownDmaChannels */
 466             /* 31     0     63    32 */
 467             {0xFFFFFFFFu, 0x00000000u},
 468
 469             /* ownQdmaChannels */
 470             /* 31     0 */
 471             {0x000000FFu},
 472
 473             /* ownTccs */
 474             /* 31     0     63    32 */
 475             {0xFFFFFFFFu, 0x00000000u},
 476
 477             /* Resources reserved by Region 1 */
 478             /* resvdPaRAMSets */
 479             /* 31     0     63    32     95    64     127   96 */
 480             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
 481             /* 159  128     191  160     223  192     255  224 */
 482              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 483             /* 287  256     319  288     351  320     383  352 */
 484              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 485             /* 415  384     447  416     479  448     511  480 */
 486              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 487
 488             /* resvdDmaChannels */
 489             /* 31       0 */
 490             {0xFF3FF3FFu,
 491             /* 63..32 */
 492             0x00000000u},
 493
 494             /* resvdQdmaChannels */
 495             /* 31     0 */
 496             {0x00000000u},
 497
 498             /* resvdTccs */
 499             /* 31       0 */
 500             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
 501             /* 63..32 */
 502             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
 503         },
 504         /* Resources owned/reserved by region 2 */
 505         {
 506             /* ownPaRAMSets */
 507             /* 31     0     63    32     95    64     127   96 */
 508             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 509             /* 159  128     191  160     223  192     255  224 */
 510              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 511             /* 287  256     319  288     351  320     383  352 */
 512              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 513             /* 415  384     447  416     479  448     511  480 */
 514              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 515
 516             /* ownDmaChannels */
 517             /* 31     0     63    32 */
 518             {0xFFFFFFFFu, 0x00000000u},
 519
 520             /* ownQdmaChannels */
 521             /* 31     0 */
 522             {0x000000FFu},
 523
 524             /* ownTccs */
 525             /* 31     0     63    32 */
 526             {0xFFFFFFFFu, 0x00000000u},
 527
 528             /* Resources reserved by Region 1 */
 529             /* resvdPaRAMSets */
 530             /* 31     0     63    32     95    64     127   96 */
 531             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
 532             /* 159  128     191  160     223  192     255  224 */
 533              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 534             /* 287  256     319  288     351  320     383  352 */
 535              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 536             /* 415  384     447  416     479  448     511  480 */
 537              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 538
 539             /* resvdDmaChannels */
 540             /* 31       0 */
 541             {0xFF3FF3FFu,
 542             /* 63..32 */
 543             0x00000000u},
 544
 545             /* resvdQdmaChannels */
 546             /* 31     0 */
 547             {0x00000000u},
 548
 549             /* resvdTccs */
 550             /* 31       0 */
 551             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
 552             /* 63..32 */
 553             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
 554         },
 555
 556         /* Resources owned/reserved by region 3 */
 557         {
 558             /* ownPaRAMSets */
 559             /* 31     0     63    32     95    64     127   96 */
 560             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
 561             /* 159  128     191  160     223  192     255  224 */
 562              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 563             /* 287  256     319  288     351  320     383  352 */
 564              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 565             /* 415  384     447  416     479  448     511  480 */
 566              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 567
 568             /* ownDmaChannels */
 569             /* 31     0     63    32 */
 570             {0x00000000u, 0x00000000u},
 571
 572             /* ownQdmaChannels */
 573             /* 31     0 */
 574             {0x00000000u},
 575
 576             /* ownTccs */
 577             /* 31     0     63    32 */
 578             {0x00000000u, 0x00000000u},
 579
 580             /* resvdPaRAMSets */
 581             /* 31     0     63    32     95    64     127   96 */
 582             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 583             /* 159  128     191  160     223  192     255  224 */
 584              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 585             /* 287  256     319  288     351  320     383  352 */
 586              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 587             /* 415  384     447  416     479  448     511  480 */
 588              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 589
 590             /* resvdDmaChannels */
 591             /* 31     0     63    32 */
 592             {0x00000000u, 0x00000000u},
 593
 594             /* resvdQdmaChannels */
 595             /* 31     0 */
 596             {0x00000000u},
 597
 598             /* resvdTccs */
 599             /* 31     0     63    32 */
 600             {0x00000000u, 0x00000000u},
 601         },
 602
 603         /* Resources owned/reserved by region 4 */
 604         {
 605             /* ownPaRAMSets */
 606             /* 31     0     63    32     95    64     127   96 */
 607             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
 608             /* 159  128     191  160     223  192     255  224 */
 609              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 610             /* 287  256     319  288     351  320     383  352 */
 611              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 612             /* 415  384     447  416     479  448     511  480 */
 613              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 614
 615             /* ownDmaChannels */
 616             /* 31     0     63    32 */
 617             {0x00000000u, 0x00000000u},
 618
 619             /* ownQdmaChannels */
 620             /* 31     0 */
 621             {0x00000000u},
 622
 623             /* ownTccs */
 624             /* 31     0     63    32 */
 625             {0x00000000u, 0x00000000u},
 626
 627             /* resvdPaRAMSets */
 628             /* 31     0     63    32     95    64     127   96 */
 629             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 630             /* 159  128     191  160     223  192     255  224 */
 631              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 632             /* 287  256     319  288     351  320     383  352 */
 633              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 634             /* 415  384     447  416     479  448     511  480 */
 635              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 636
 637             /* resvdDmaChannels */
 638             /* 31     0     63    32 */
 639             {0x00000000u, 0x00000000u},
 640
 641             /* resvdQdmaChannels */
 642             /* 31     0 */
 643             {0x00000000u},
 644
 645             /* resvdTccs */
 646             /* 31     0     63    32 */
 647             {0x00000000u, 0x00000000u},
 648         },
 649
 650         /* Resources owned/reserved by region 5 */
 651         {
 652             /* ownPaRAMSets */
 653             /* 31     0     63    32     95    64     127   96 */
 654             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 655             /* 159  128     191  160     223  192     255  224 */
 656              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 657             /* 287  256     319  288     351  320     383  352 */
 658              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 659             /* 415  384     447  416     479  448     511  480 */
 660              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 661
 662             /* ownDmaChannels */
 663             /* 31     0     63    32 */
 664             {0x00000000u, 0x00000000u},
 665
 666             /* ownQdmaChannels */
 667             /* 31     0 */
 668             {0x00000000u},
 669
 670             /* ownTccs */
 671             /* 31     0     63    32 */
 672             {0x00000000u, 0x00000000u},
 673
 674             /* resvdPaRAMSets */
 675             /* 31     0     63    32     95    64     127   96 */
 676             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 677             /* 159  128     191  160     223  192     255  224 */
 678              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 679             /* 287  256     319  288     351  320     383  352 */
 680              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 681             /* 415  384     447  416     479  448     511  480 */
 682              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 683
 684             /* resvdDmaChannels */
 685             /* 31     0     63    32 */
 686             {0x00000000u, 0x00000000u},
 687
 688             /* resvdQdmaChannels */
 689             /* 31     0 */
 690             {0x00000000u},
 691
 692             /* resvdTccs */
 693             /* 31     0     63    32 */
 694             {0x00000000u, 0x00000000u},
 695         },
 696
 697         /* Resources owned/reserved by region 6 */
 698         {
 699             /* ownPaRAMSets */
 700             /* 31     0     63    32     95    64     127   96 */
 701             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 702             /* 159  128     191  160     223  192     255  224 */
 703              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 704             /* 287  256     319  288     351  320     383  352 */
 705              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 706             /* 415  384     447  416     479  448     511  480 */
 707              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 708
 709             /* ownDmaChannels */
 710             /* 31     0     63    32 */
 711             {0x00000000u, 0x00000000u},
 712
 713             /* ownQdmaChannels */
 714             /* 31     0 */
 715             {0x00000000u},
 716
 717             /* ownTccs */
 718             /* 31     0     63    32 */
 719             {0x00000000u, 0x00000000u},
 720
 721             /* resvdPaRAMSets */
 722             /* 31     0     63    32     95    64     127   96 */
 723             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 724             /* 159  128     191  160     223  192     255  224 */
 725              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 726             /* 287  256     319  288     351  320     383  352 */
 727              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 728             /* 415  384     447  416     479  448     511  480 */
 729              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 730
 731             /* resvdDmaChannels */
 732             /* 31     0     63    32 */
 733             {0x00000000u, 0x00000000u},
 734
 735             /* resvdQdmaChannels */
 736             /* 31     0 */
 737             {0x00000000u},
 738
 739             /* resvdTccs */
 740             /* 31     0     63    32 */
 741             {0x00000000u, 0x00000000u},
 742         },
 743
 744         /* Resources owned/reserved by region 7 */
 745         {
 746             /* ownPaRAMSets */
 747             /* 31     0     63    32     95    64     127   96 */
 748             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 749             /* 159  128     191  160     223  192     255  224 */
 750              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 751             /* 287  256     319  288     351  320     383  352 */
 752              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 753             /* 415  384     447  416     479  448     511  480 */
 754              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 755
 756             /* ownDmaChannels */
 757             /* 31     0     63    32 */
 758             {0x00000000u, 0x00000000u},
 759
 760             /* ownQdmaChannels */
 761             /* 31     0 */
 762             {0x00000000u},
 763
 764             /* ownTccs */
 765             /* 31     0     63    32 */
 766             {0x00000000u, 0x00000000u},
 767
 768             /* resvdPaRAMSets */
 769             /* 31     0     63    32     95    64     127   96 */
 770             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 771             /* 159  128     191  160     223  192     255  224 */
 772              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 773             /* 287  256     319  288     351  320     383  352 */
 774              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 775             /* 415  384     447  416     479  448     511  480 */
 776              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 777
 778             /* resvdDmaChannels */
 779             /* 31     0     63    32 */
 780             {0x00000000u, 0x00000000u},
 781
 782             /* resvdQdmaChannels */
 783             /* 31     0 */
 784             {0x00000000u},
 785
 786             /* resvdTccs */
 787             /* 31     0     63    32 */
 788             {0x00000000u, 0x00000000u},
 789         },
 790     }
 791 };
 792
 793 /* Driver Instance Cross bar event to channel map Initialization Configuration */
 794 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 795 {
 796     /* EDMA3 INSTANCE# 0 */
 797     {
 798         /* Event to channel map for region 0 */
 799         {
 800             -1, -1, -1, -1, -1, -1, -1, -1,
 801             -1, -1, -1, -1, -1, -1, -1, -1,
 802             -1, -1, -1, -1, -1, -1, -1, -1,
 803             -1, 26, 27, -1, -1, -1, -1
 804         },
 805         /* Event to channel map for region 1 */
 806         {
 807             -1, -1, -1, -1, -1, -1, -1, -1,
 808             -1, -1, -1, -1, -1, -1, -1, -1,
 809             -1, -1, -1, -1, -1, -1, -1, -1,
 810             -1, -1, -1, -1, -1, -1, -1
 811         },
 812         /* Event to channel map for region 2 */
 813         {
 814             -1, -1, -1, -1, -1, -1, -1, -1,
 815             -1, -1, -1, -1, -1, -1, -1, -1,
 816             -1, -1, -1, -1, -1, -1, -1, -1,
 817             -1, -1, -1, -1, -1, -1, -1
 818         },
 819         /* Event to channel map for region 3 */
 820         {
 821             -1, -1, -1, -1, -1, -1, -1, -1,
 822             -1, -1, -1, -1, -1, -1, -1, -1,
 823             -1, -1, -1, -1, -1, -1, -1, -1,
 824             -1, -1, -1, -1, -1, -1, -1
 825         },
 826         /* Event to channel map for region 4 */
 827         {
 828             -1, -1, -1, -1, -1, -1, -1, -1,
 829             -1, -1, -1, -1, -1, -1, -1, -1,
 830             -1, -1, -1, -1, -1, -1, -1, -1,
 831             -1, -1, -1, -1, -1, -1, -1
 832         },
 833         /* Event to channel map for region 5 */
 834         {
 835             -1, -1, -1, -1, -1, -1, -1, -1,
 836             -1, -1, -1, -1, -1, -1, -1, -1,
 837             -1, -1, -1, -1, -1, -1, -1, -1,
 838             -1, -1, -1, -1, -1, -1, -1
 839         },
 840         /* Event to channel map for region 6 */
 841         {
 842             -1, -1, -1, -1, -1, -1, -1, -1,
 843             -1, -1, -1, -1, -1, -1, -1, -1,
 844             -1, -1, -1, -1, -1, -1, -1, -1,
 845             -1, -1, -1, -1, -1, -1, -1
 846         },
 847         /* Event to channel map for region 7 */
 848         {
 849             -1, -1, -1, -1, -1, -1, -1, -1,
 850             -1, -1, -1, -1, -1, -1, -1, -1,
 851             -1, -1, -1, -1, -1, -1, -1, -1,
 852             -1, -1, -1, -1, -1, -1, -1
 853         },
 854     }
 855 };
 856
 857 /* End of File */
 858