Fix for multi-core execution of examples.
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_ti814x_cfg.c
1 /*
2  * sample_ti814x_cfg.c
3  *
4  * SoC specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES         1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                    1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54     return 1;
55 }
57 signed char*  getGlobalAddr(signed char* addr)
58 {
59      return (addr); /* The address is already a global address */
60 }
61 unsigned short isGblConfigRequired(unsigned int dspNum)
62 {
63     (void) dspNum;
65     return 1;
66 }
68 /* Semaphore handles */
69 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
71 /** Number of PaRAM Sets available                                            */
72 #define EDMA3_NUM_PARAMSET                              (512u)
74 /** Number of TCCS available                                                  */
75 #define EDMA3_NUM_TCC                                   (64u)
77 /** Number of DMA Channels available                                          */
78 #define EDMA3_NUM_DMA_CHANNELS                          (64u)
80 /** Number of QDMA Channels available                                         */
81 #define EDMA3_NUM_QDMA_CHANNELS                         (8u)
83 /** Number of Event Queues available                                          */
84 #define EDMA3_0_NUM_EVTQUE                              (4u)
86 /** Number of Transfer Controllers available                                  */
87 #define EDMA3_0_NUM_TC                                  (4u)
89 /** Number of Regions                                                         */
90 #define EDMA3_0_NUM_REGIONS                             (2u)
93 /** Interrupt no. for Transfer Completion                                     */
94 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (20u)
95 /** Interrupt no. for CC Error                                                */
96 #define EDMA3_0_CC_ERROR_INT                            (21u)
97 /** Interrupt no. for TCs Error                                               */
98 #define EDMA3_0_TC0_ERROR_INT                           (22u)
99 #define EDMA3_0_TC1_ERROR_INT                           (27u)
100 #define EDMA3_0_TC2_ERROR_INT                           (28u)
101 #define EDMA3_0_TC3_ERROR_INT                           (29u)
102 #define EDMA3_0_TC4_ERROR_INT                           (0u)
103 #define EDMA3_0_TC5_ERROR_INT                           (0u)
104 #define EDMA3_0_TC6_ERROR_INT                           (0u)
105 #define EDMA3_0_TC7_ERROR_INT                           (0u)
107 /**
108  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
109  * ECM events (SoC specific). These ECM events come
110  * under ECM block XXX (handling those specific ECM events). Normally, block
111  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
112  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
113  * is mapped to a specific HWI_INT YYY in the tcf file.
114  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
115  * to transfer completion interrupt.
116  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
117  * to CC error interrupts.
118  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
119  * to TC error interrupts.
120  */
121 /* EDMA 0 */
123 #define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
124 #define EDMA3_0_HWI_INT_CC_ERR                              (7u)
125 #define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
126 #define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
127 #define EDMA3_0_HWI_INT_TC2_ERR                             (7u)
128 #define EDMA3_0_HWI_INT_TC3_ERR                             (7u)
131 /**
132  * \brief Mapping of DMA channels 0-31 to Hardware Events from
133  * various peripherals, which use EDMA for data transfer.
134  * All channels need not be mapped, some can be free also.
135  * 1: Mapped
136  * 0: Not mapped
137  *
138  * This mapping will be used to allocate DMA channels when user passes
139  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
140  * copy). The same mapping is used to allocate the TCC when user passes
141  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
142  *
143  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
144  */
145                                                       /* 31     0 */
146 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00u)  /* TBD */
149 /**
150  * \brief Mapping of DMA channels 32-63 to Hardware Events from
151  * various peripherals, which use EDMA for data transfer.
152  * All channels need not be mapped, some can be free also.
153  * 1: Mapped
154  * 0: Not mapped
155  *
156  * This mapping will be used to allocate DMA channels when user passes
157  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
158  * copy). The same mapping is used to allocate the TCC when user passes
159  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
160  *
161  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
162  */
163 /* DMA channels 32-63 DOES NOT exist in omapl138. */
164 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF033C00u) /* TBD */
167 /* Variable which will be used internally for referring number of Event Queues*/
168 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
169                                                         EDMA3_0_NUM_EVTQUE,
170                                                     };
172 /* Variable which will be used internally for referring number of TCs.        */
173 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
174                                                     EDMA3_0_NUM_TC,
175                                                 };
177 /**
178  * Variable which will be used internally for referring transfer completion
179  * interrupt.
180  */
181 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
183     {
184         0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
185     },
186 };
188 /**
189  * Variable which will be used internally for referring channel controller's
190  * error interrupt.
191  */
192 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
193                                                     EDMA3_0_CC_ERROR_INT,
194                                                };
196 /**
197  * Variable which will be used internally for referring transfer controllers'
198  * error interrupts.
199  */
200 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
202    {
203        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
204        EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
205        EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
206        EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
207    }
208 };
210 /**
211  * Variables which will be used internally for referring the hardware interrupt
212  * for various EDMA3 interrupts.
213  */
214 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
215                                                     EDMA3_0_HWI_INT_XFER_COMP
216                                                   };
218 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
219                                                    EDMA3_0_HWI_INT_CC_ERR
220                                                };
222 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
223                                                      {
224                                                         EDMA3_0_HWI_INT_TC0_ERR,
225                                                         EDMA3_0_HWI_INT_TC1_ERR,
226                                                         EDMA3_0_HWI_INT_TC2_ERR,
227                                                         EDMA3_0_HWI_INT_TC3_ERR
228                                                      }
229                                                };
231 /* Driver Object Initialization Configuration */
232 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
234     {
235         /* EDMA3 INSTANCE# 0 */
236         /** Total number of DMA Channels supported by the EDMA3 Controller    */
237         EDMA3_NUM_DMA_CHANNELS,
238         /** Total number of QDMA Channels supported by the EDMA3 Controller   */
239         EDMA3_NUM_QDMA_CHANNELS,
240         /** Total number of TCCs supported by the EDMA3 Controller            */
241         EDMA3_NUM_TCC,
242         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
243         EDMA3_NUM_PARAMSET,
244         /** Total number of Event Queues in the EDMA3 Controller              */
245         EDMA3_0_NUM_EVTQUE,
246         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
247         EDMA3_0_NUM_TC,
248         /** Number of Regions on this EDMA3 controller                        */
249         EDMA3_0_NUM_REGIONS,
251         /**
252          * \brief Channel mapping existence
253          * A value of 0 (No channel mapping) implies that there is fixed association
254          * for a channel number to a parameter entry number or, in other words,
255          * PaRAM entry n corresponds to channel n.
256          */
257         1u,
259         /** Existence of memory protection feature */
260         0u,
262         /** Global Register Region of CC Registers */
263         (void *)0x09000000u,
264         /** Transfer Controller (TC) Registers */
265         {
266             (void *)0x09800000u,
267             (void *)0x09900000u,
268             (void *)0x09A00000u,
269             (void *)0x09B00000u,
270             (void *)NULL,
271             (void *)NULL,
272             (void *)NULL,
273             (void *)NULL
274         },
275         /** Interrupt no. for Transfer Completion */
276         EDMA3_0_CC_XFER_COMPLETION_INT,
277         /** Interrupt no. for CC Error */
278         EDMA3_0_CC_ERROR_INT,
279         /** Interrupt no. for TCs Error */
280         {
281             EDMA3_0_TC0_ERROR_INT,
282             EDMA3_0_TC1_ERROR_INT,
283             EDMA3_0_TC2_ERROR_INT,
284             EDMA3_0_TC3_ERROR_INT,
285             EDMA3_0_TC4_ERROR_INT,
286             EDMA3_0_TC5_ERROR_INT,
287             EDMA3_0_TC6_ERROR_INT,
288             EDMA3_0_TC7_ERROR_INT
289         },
291         /**
292          * \brief EDMA3 TC priority setting
293          *
294          * User can program the priority of the Event Queues
295          * at a system-wide level.  This means that the user can set the
296          * priority of an IO initiated by either of the TCs (Transfer Controllers)
297          * relative to IO initiated by the other bus masters on the
298          * device (ARM, DSP, USB, etc)
299          */
300         {
301             0u,
302             1u,
303             2u,
304             3u,
305             0u,
306             0u,
307             0u,
308             0u
309         },
310         /**
311          * \brief To Configure the Threshold level of number of events
312          * that can be queued up in the Event queues. EDMA3CC error register
313          * (CCERR) will indicate whether or not at any instant of time the
314          * number of events queued up in any of the event queues exceeds
315          * or equals the threshold/watermark value that is set
316          * in the queue watermark threshold register (QWMTHRA).
317          */
318         {
319             16u,
320             16u,
321             16u,
322             16u,
323             0u,
324             0u,
325             0u,
326             0u
327         },
329         /**
330          * \brief To Configure the Default Burst Size (DBS) of TCs.
331          * An optimally-sized command is defined by the transfer controller
332          * default burst size (DBS). Different TCs can have different
333          * DBS values. It is defined in Bytes.
334          */
335             {
336             16u,
337             16u,
338             0u,
339             0u,
340             0u,
341             0u,
342             0u,
343             0u
344             },
346         /**
347          * \brief Mapping from each DMA channel to a Parameter RAM set,
348          * if it exists, otherwise of no use.
349          */
350             {
351             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
352             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
353             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
354             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
355             32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
356             40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
357             48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
358             56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
359             },
361          /**
362           * \brief Mapping from each DMA channel to a TCC. This specific
363           * TCC code will be returned when the transfer is completed
364           * on the mapped channel.
365           */
366             {
367             0u, 1u, 2u, 3u,
368             4u, 5u, 6u, 7u,
369             8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
370             12u, 13u, 14u, 15u,
371             16u, 17u, 18u, 19u,
372             20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
373             24u, 25u, 26u, 27u,
374             28u, 29u, 30u, 31u,
375             32u, 33u, 34u, 35u,
376             36u, 37u, 38u, 39u,
377             40u, 41u, 42u, 43u,
378             44u, 45u, 46u, 47u,
379             48u, 49u, 50u, 51u,
380             52u, 53u, 54u, 55u,
381             56u, 57u, 58u, 59u,
382             60u, 61u, 62u, 63u
383             },
385         /**
386          * \brief Mapping of DMA channels to Hardware Events from
387          * various peripherals, which use EDMA for data transfer.
388          * All channels need not be mapped, some can be free also.
389          */
390             {
391             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
392             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
393             }
394         },
395 };
398 /* Driver Instance Initialization Configuration */
399 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
401     /* EDMA3 INSTANCE# 0 */
402     {
403         /* Resources owned/reserved by region 0 */
404         {
405             /* ownPaRAMSets */
406             /* 31     0     63    32     95    64     127   96 */
407             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
408             /* 159  128     191  160     223  192     255  224 */
409              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
410             /* 287  256     319  288     351  320     383  352 */
411              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
412             /* 415  384     447  416     479  448     511  480 */
413              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
415             /* ownDmaChannels */
416             /* 31     0     63    32 */
417             {0xFFFFFFFFu, 0x00000000u},
419             /* ownQdmaChannels */
420             /* 31     0 */
421             {0x000000FFu},
423             /* ownTccs */
424             /* 31     0     63    32 */
425             {0xFFFFFFFFu, 0x00000000u},
427             /* Resources reserved by Region 1 */
428             /* resvdPaRAMSets */
429             /* 31     0     63    32     95    64     127   96 */
430             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
431             /* 159  128     191  160     223  192     255  224 */
432              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
433             /* 287  256     319  288     351  320     383  352 */
434              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
435             /* 415  384     447  416     479  448     511  480 */
436              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
438             /* resvdDmaChannels */
439             /* 31       0 */
440             {0xFF3FF3FFu,
441             /* 63..32 */
442             0x00000000u},
444             /* resvdQdmaChannels */
445             /* 31     0 */
446             {0x00000000u},
448             /* resvdTccs */
449             /* 31       0 */
450             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
451             /* 63..32 */
452             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
453         },
454         /* Resources owned/reserved by region 1 */
455         {
456             /* ownPaRAMSets */
457             /* 31     0     63    32     95    64     127   96 */
458             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
459             /* 159  128     191  160     223  192     255  224 */
460              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
461             /* 287  256     319  288     351  320     383  352 */
462              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
463             /* 415  384     447  416     479  448     511  480 */
464              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
466             /* ownDmaChannels */
467             /* 31     0     63    32 */
468             {0xFFFFFFFFu, 0xFFFFFFFFu},
470             /* ownQdmaChannels */
471             /* 31     0 */
472             {0x000000FFu},
474             /* ownTccs */
475             /* 31     0     63    32 */
476             {0xFFFFFFFFu, 0xFFFFFFFFu},
478             /* Resources reserved by Region 1 */
479             /* resvdPaRAMSets */
480             /* 31     0     63    32     95    64     127   96 */
481             {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
482             /* 159  128     191  160     223  192     255  224 */
483              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
484             /* 287  256     319  288     351  320     383  352 */
485              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
486             /* 415  384     447  416     479  448     511  480 */
487              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
489             /* resvdDmaChannels */
490             /* 31       0 */
491             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
492             /* 63..32 */
493             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
495             /* resvdQdmaChannels */
496             /* 31     0 */
497             {0x00000000u},
499             /* resvdTccs */
500             /* 31       0 */
501             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
502             /* 63..32 */
503             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
504         },
505         /* Resources owned/reserved by region 2 */
506         {
507             /* ownPaRAMSets */
508             /* 31     0     63    32     95    64     127   96 */
509             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
510             /* 159  128     191  160     223  192     255  224 */
511              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
512             /* 287  256     319  288     351  320     383  352 */
513              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
514             /* 415  384     447  416     479  448     511  480 */
515              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
517             /* ownDmaChannels */
518             /* 31     0     63    32 */
519             {0x00000000u, 0x00000000u},
521             /* ownQdmaChannels */
522             /* 31     0 */
523             {0x00000000u},
525             /* ownTccs */
526             /* 31     0     63    32 */
527             {0x00000000u, 0x00000000u},
529             /* resvdPaRAMSets */
530             /* 31     0     63    32     95    64     127   96 */
531             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
532             /* 159  128     191  160     223  192     255  224 */
533              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
534             /* 287  256     319  288     351  320     383  352 */
535              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
536             /* 415  384     447  416     479  448     511  480 */
537              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
539             /* resvdDmaChannels */
540             /* 31     0     63    32 */
541             {0x00000000u, 0x00000000u},
543             /* resvdQdmaChannels */
544             /* 31     0 */
545             {0x00000000u},
547             /* resvdTccs */
548             /* 31     0     63    32 */
549             {0x00000000u, 0x00000000u},
550         },
552         /* Resources owned/reserved by region 3 */
553         {
554             /* ownPaRAMSets */
555             /* 31     0     63    32     95    64     127   96 */
556             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
557             /* 159  128     191  160     223  192     255  224 */
558              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
559             /* 287  256     319  288     351  320     383  352 */
560              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
561             /* 415  384     447  416     479  448     511  480 */
562              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
564             /* ownDmaChannels */
565             /* 31     0     63    32 */
566             {0x00000000u, 0x00000000u},
568             /* ownQdmaChannels */
569             /* 31     0 */
570             {0x00000000u},
572             /* ownTccs */
573             /* 31     0     63    32 */
574             {0x00000000u, 0x00000000u},
576             /* resvdPaRAMSets */
577             /* 31     0     63    32     95    64     127   96 */
578             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
579             /* 159  128     191  160     223  192     255  224 */
580              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
581             /* 287  256     319  288     351  320     383  352 */
582              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
583             /* 415  384     447  416     479  448     511  480 */
584              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
586             /* resvdDmaChannels */
587             /* 31     0     63    32 */
588             {0x00000000u, 0x00000000u},
590             /* resvdQdmaChannels */
591             /* 31     0 */
592             {0x00000000u},
594             /* resvdTccs */
595             /* 31     0     63    32 */
596             {0x00000000u, 0x00000000u},
597         },
599         /* Resources owned/reserved by region 4 */
600         {
601             /* ownPaRAMSets */
602             /* 31     0     63    32     95    64     127   96 */
603             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
604             /* 159  128     191  160     223  192     255  224 */
605              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
606             /* 287  256     319  288     351  320     383  352 */
607              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
608             /* 415  384     447  416     479  448     511  480 */
609              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
611             /* ownDmaChannels */
612             /* 31     0     63    32 */
613             {0x00000000u, 0x00000000u},
615             /* ownQdmaChannels */
616             /* 31     0 */
617             {0x00000000u},
619             /* ownTccs */
620             /* 31     0     63    32 */
621             {0x00000000u, 0x00000000u},
623             /* resvdPaRAMSets */
624             /* 31     0     63    32     95    64     127   96 */
625             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
626             /* 159  128     191  160     223  192     255  224 */
627              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
628             /* 287  256     319  288     351  320     383  352 */
629              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
630             /* 415  384     447  416     479  448     511  480 */
631              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
633             /* resvdDmaChannels */
634             /* 31     0     63    32 */
635             {0x00000000u, 0x00000000u},
637             /* resvdQdmaChannels */
638             /* 31     0 */
639             {0x00000000u},
641             /* resvdTccs */
642             /* 31     0     63    32 */
643             {0x00000000u, 0x00000000u},
644         },
646         /* Resources owned/reserved by region 5 */
647         {
648             /* ownPaRAMSets */
649             /* 31     0     63    32     95    64     127   96 */
650             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
651             /* 159  128     191  160     223  192     255  224 */
652              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
653             /* 287  256     319  288     351  320     383  352 */
654              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
655             /* 415  384     447  416     479  448     511  480 */
656              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
658             /* ownDmaChannels */
659             /* 31     0     63    32 */
660             {0x00000000u, 0x00000000u},
662             /* ownQdmaChannels */
663             /* 31     0 */
664             {0x00000000u},
666             /* ownTccs */
667             /* 31     0     63    32 */
668             {0x00000000u, 0x00000000u},
670             /* resvdPaRAMSets */
671             /* 31     0     63    32     95    64     127   96 */
672             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
673             /* 159  128     191  160     223  192     255  224 */
674              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
675             /* 287  256     319  288     351  320     383  352 */
676              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
677             /* 415  384     447  416     479  448     511  480 */
678              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
680             /* resvdDmaChannels */
681             /* 31     0     63    32 */
682             {0x00000000u, 0x00000000u},
684             /* resvdQdmaChannels */
685             /* 31     0 */
686             {0x00000000u},
688             /* resvdTccs */
689             /* 31     0     63    32 */
690             {0x00000000u, 0x00000000u},
691         },
693         /* Resources owned/reserved by region 6 */
694         {
695             /* ownPaRAMSets */
696             /* 31     0     63    32     95    64     127   96 */
697             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
698             /* 159  128     191  160     223  192     255  224 */
699              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
700             /* 287  256     319  288     351  320     383  352 */
701              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
702             /* 415  384     447  416     479  448     511  480 */
703              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
705             /* ownDmaChannels */
706             /* 31     0     63    32 */
707             {0x00000000u, 0x00000000u},
709             /* ownQdmaChannels */
710             /* 31     0 */
711             {0x00000000u},
713             /* ownTccs */
714             /* 31     0     63    32 */
715             {0x00000000u, 0x00000000u},
717             /* resvdPaRAMSets */
718             /* 31     0     63    32     95    64     127   96 */
719             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
720             /* 159  128     191  160     223  192     255  224 */
721              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
722             /* 287  256     319  288     351  320     383  352 */
723              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
724             /* 415  384     447  416     479  448     511  480 */
725              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
727             /* resvdDmaChannels */
728             /* 31     0     63    32 */
729             {0x00000000u, 0x00000000u},
731             /* resvdQdmaChannels */
732             /* 31     0 */
733             {0x00000000u},
735             /* resvdTccs */
736             /* 31     0     63    32 */
737             {0x00000000u, 0x00000000u},
738         },
740         /* Resources owned/reserved by region 7 */
741         {
742             /* ownPaRAMSets */
743             /* 31     0     63    32     95    64     127   96 */
744             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
745             /* 159  128     191  160     223  192     255  224 */
746              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
747             /* 287  256     319  288     351  320     383  352 */
748              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
749             /* 415  384     447  416     479  448     511  480 */
750              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
752             /* ownDmaChannels */
753             /* 31     0     63    32 */
754             {0x00000000u, 0x00000000u},
756             /* ownQdmaChannels */
757             /* 31     0 */
758             {0x00000000u},
760             /* ownTccs */
761             /* 31     0     63    32 */
762             {0x00000000u, 0x00000000u},
764             /* resvdPaRAMSets */
765             /* 31     0     63    32     95    64     127   96 */
766             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
767             /* 159  128     191  160     223  192     255  224 */
768              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
769             /* 287  256     319  288     351  320     383  352 */
770              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
771             /* 415  384     447  416     479  448     511  480 */
772              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
774             /* resvdDmaChannels */
775             /* 31     0     63    32 */
776             {0x00000000u, 0x00000000u},
778             /* resvdQdmaChannels */
779             /* 31     0 */
780             {0x00000000u},
782             /* resvdTccs */
783             /* 31     0     63    32 */
784             {0x00000000u, 0x00000000u},
785         },
786     }
787 };
789 /* Driver Instance Cross bar event to channel map Initialization Configuration */
790 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
792     /* EDMA3 INSTANCE# 0 */
793     {
794         /* Event to channel map for region 0 */
795         {
796             -1, -1, -1, -1, -1, -1, -1, -1,
797             -1, -1, -1, -1, -1, -1, -1, -1,
798             -1, -1, -1, -1, -1, -1, -1, -1,
799             -1, -1, -1, -1, -1, -1, -1
800         },
801         /* Event to channel map for region 1 */
802         {
803             -1, -1, -1, -1, -1, -1, -1, -1,
804             -1, -1, -1, -1, -1, -1, -1, -1,
805             -1, -1, -1, -1, -1, -1, -1, -1,
806             -1, 26, 27, -1, -1, -1, -1
807         },
808         /* Event to channel map for region 2 */
809         {
810             -1, -1, -1, -1, -1, -1, -1, -1,
811             -1, -1, -1, -1, -1, -1, -1, -1,
812             -1, -1, -1, -1, -1, -1, -1, -1,
813             -1, -1, -1, -1, -1, -1, -1
814         },
815         /* Event to channel map for region 3 */
816         {
817             -1, -1, -1, -1, -1, -1, -1, -1,
818             -1, -1, -1, -1, -1, -1, -1, -1,
819             -1, -1, -1, -1, -1, -1, -1, -1,
820             -1, -1, -1, -1, -1, -1, -1
821         },
822         /* Event to channel map for region 4 */
823         {
824             -1, -1, -1, -1, -1, -1, -1, -1,
825             -1, -1, -1, -1, -1, -1, -1, -1,
826             -1, -1, -1, -1, -1, -1, -1, -1,
827             -1, -1, -1, -1, -1, -1, -1
828         },
829         /* Event to channel map for region 5 */
830         {
831             -1, -1, -1, -1, -1, -1, -1, -1,
832             -1, -1, -1, -1, -1, -1, -1, -1,
833             -1, -1, -1, -1, -1, -1, -1, -1,
834             -1, -1, -1, -1, -1, -1, -1
835         },
836         /* Event to channel map for region 6 */
837         {
838             -1, -1, -1, -1, -1, -1, -1, -1,
839             -1, -1, -1, -1, -1, -1, -1, -1,
840             -1, -1, -1, -1, -1, -1, -1, -1,
841             -1, -1, -1, -1, -1, -1, -1
842         },
843         /* Event to channel map for region 7 */
844         {
845             -1, -1, -1, -1, -1, -1, -1, -1,
846             -1, -1, -1, -1, -1, -1, -1, -1,
847             -1, -1, -1, -1, -1, -1, -1, -1,
848             -1, -1, -1, -1, -1, -1, -1
849         },
850     }
851 };
853 /* End of File */