Added source files and example application project for supporting TI814X
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_ti814x_cfg.c
1 /*
2  * sample_ti814x_cfg.c
3  *
4  * SoC specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/drv/edma3_drv.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES         1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                    1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54     return 1;
55 }
57 unsigned short isGblConfigRequired(unsigned int dspNum)
58 {
59     (void) dspNum;
61     return 1;
62 }
64 /* Semaphore handles */
65 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
67 /** Number of PaRAM Sets available                                            */
68 #define EDMA3_NUM_PARAMSET                              (512u)
70 /** Number of TCCS available                                                  */
71 #define EDMA3_NUM_TCC                                   (64u)
73 /** Number of DMA Channels available                                          */
74 #define EDMA3_NUM_DMA_CHANNELS                          (64u)
76 /** Number of QDMA Channels available                                         */
77 #define EDMA3_NUM_QDMA_CHANNELS                         (8u)
79 /** Number of Event Queues available                                          */
80 #define EDMA3_0_NUM_EVTQUE                              (4u)
82 /** Number of Transfer Controllers available                                  */
83 #define EDMA3_0_NUM_TC                                  (4u)
85 /** Number of Regions                                                         */
86 #define EDMA3_0_NUM_REGIONS                             (2u)
89 /** Interrupt no. for Transfer Completion                                     */
90 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (20u)
91 /** Interrupt no. for CC Error                                                */
92 #define EDMA3_0_CC_ERROR_INT                            (21u)
93 /** Interrupt no. for TCs Error                                               */
94 #define EDMA3_0_TC0_ERROR_INT                           (22u)
95 #define EDMA3_0_TC1_ERROR_INT                           (27u)
96 #define EDMA3_0_TC2_ERROR_INT                           (28u)
97 #define EDMA3_0_TC3_ERROR_INT                           (29u)
98 #define EDMA3_0_TC4_ERROR_INT                           (0u)
99 #define EDMA3_0_TC5_ERROR_INT                           (0u)
100 #define EDMA3_0_TC6_ERROR_INT                           (0u)
101 #define EDMA3_0_TC7_ERROR_INT                           (0u)
103 /**
104  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
105  * ECM events (SoC specific). These ECM events come
106  * under ECM block XXX (handling those specific ECM events). Normally, block
107  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
108  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
109  * is mapped to a specific HWI_INT YYY in the tcf file.
110  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
111  * to transfer completion interrupt.
112  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
113  * to CC error interrupts.
114  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
115  * to TC error interrupts.
116  */
117 /* EDMA 0 */
119 #define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
120 #define EDMA3_0_HWI_INT_CC_ERR                              (7u)
121 #define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
122 #define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
123 #define EDMA3_0_HWI_INT_TC2_ERR                             (7u)
124 #define EDMA3_0_HWI_INT_TC3_ERR                             (7u)
127 /**
128  * \brief Mapping of DMA channels 0-31 to Hardware Events from
129  * various peripherals, which use EDMA for data transfer.
130  * All channels need not be mapped, some can be free also.
131  * 1: Mapped
132  * 0: Not mapped
133  *
134  * This mapping will be used to allocate DMA channels when user passes
135  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
136  * copy). The same mapping is used to allocate the TCC when user passes
137  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
138  *
139  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
140  */
141                                                       /* 31     0 */
142 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFFFFFFFFu)  /* TBD */
145 /**
146  * \brief Mapping of DMA channels 32-63 to Hardware Events from
147  * various peripherals, which use EDMA for data transfer.
148  * All channels need not be mapped, some can be free also.
149  * 1: Mapped
150  * 0: Not mapped
151  *
152  * This mapping will be used to allocate DMA channels when user passes
153  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
154  * copy). The same mapping is used to allocate the TCC when user passes
155  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
156  *
157  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
158  */
159 /* DMA channels 32-63 DOES NOT exist in omapl138. */
160 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFFFFFFFFu) /* TBD */
163 /* Variable which will be used internally for referring number of Event Queues*/
164 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
165                                                         EDMA3_0_NUM_EVTQUE,
166                                                     };
168 /* Variable which will be used internally for referring number of TCs.        */
169 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
170                                                     EDMA3_0_NUM_TC,
171                                                 };
173 /**
174  * Variable which will be used internally for referring transfer completion
175  * interrupt.
176  */
177 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
179     {
180         0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
181     },
182 };
184 /**
185  * Variable which will be used internally for referring channel controller's
186  * error interrupt.
187  */
188 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
189                                                     EDMA3_0_CC_ERROR_INT,
190                                                };
192 /**
193  * Variable which will be used internally for referring transfer controllers'
194  * error interrupts.
195  */
196 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
198    {
199        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
200        EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
201        EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
202        EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
203    }
204 };
206 /**
207  * Variables which will be used internally for referring the hardware interrupt
208  * for various EDMA3 interrupts.
209  */
210 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
211                                                     EDMA3_0_HWI_INT_XFER_COMP
212                                                   };
214 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
215                                                    EDMA3_0_HWI_INT_CC_ERR
216                                                };
218 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
219                                                      {
220                                                         EDMA3_0_HWI_INT_TC0_ERR,
221                                                         EDMA3_0_HWI_INT_TC1_ERR,
222                                                         EDMA3_0_HWI_INT_TC2_ERR,
223                                                         EDMA3_0_HWI_INT_TC3_ERR
224                                                      }
225                                                };
227 /* Driver Object Initialization Configuration */
228 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
230     {
231         /* EDMA3 INSTANCE# 0 */
232         /** Total number of DMA Channels supported by the EDMA3 Controller    */
233         EDMA3_NUM_DMA_CHANNELS,
234         /** Total number of QDMA Channels supported by the EDMA3 Controller   */
235         EDMA3_NUM_QDMA_CHANNELS,
236         /** Total number of TCCs supported by the EDMA3 Controller            */
237         EDMA3_NUM_TCC,
238         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
239         EDMA3_NUM_PARAMSET,
240         /** Total number of Event Queues in the EDMA3 Controller              */
241         EDMA3_0_NUM_EVTQUE,
242         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
243         EDMA3_0_NUM_TC,
244         /** Number of Regions on this EDMA3 controller                        */
245         EDMA3_0_NUM_REGIONS,
247         /**
248          * \brief Channel mapping existence
249          * A value of 0 (No channel mapping) implies that there is fixed association
250          * for a channel number to a parameter entry number or, in other words,
251          * PaRAM entry n corresponds to channel n.
252          */
253         0u,
255         /** Existence of memory protection feature */
256         0u,
258         /** Global Register Region of CC Registers */
259         (void *)0x49000000u,
260         /** Transfer Controller (TC) Registers */
261         {
262             (void *)0x49800000u,
263             (void *)0x49900000u,
264             (void *)0x49A00000u,
265             (void *)0x49B00000u,
266             (void *)NULL,
267             (void *)NULL,
268             (void *)NULL,
269             (void *)NULL
270         },
271         /** Interrupt no. for Transfer Completion */
272         EDMA3_0_CC_XFER_COMPLETION_INT,
273         /** Interrupt no. for CC Error */
274         EDMA3_0_CC_ERROR_INT,
275         /** Interrupt no. for TCs Error */
276         {
277             EDMA3_0_TC0_ERROR_INT,
278             EDMA3_0_TC1_ERROR_INT,
279             EDMA3_0_TC2_ERROR_INT,
280             EDMA3_0_TC3_ERROR_INT,
281             EDMA3_0_TC4_ERROR_INT,
282             EDMA3_0_TC5_ERROR_INT,
283             EDMA3_0_TC6_ERROR_INT,
284             EDMA3_0_TC7_ERROR_INT
285         },
287         /**
288          * \brief EDMA3 TC priority setting
289          *
290          * User can program the priority of the Event Queues
291          * at a system-wide level.  This means that the user can set the
292          * priority of an IO initiated by either of the TCs (Transfer Controllers)
293          * relative to IO initiated by the other bus masters on the
294          * device (ARM, DSP, USB, etc)
295          */
296         {
297             0u,
298             1u,
299             2u,
300             3u,
301             0u,
302             0u,
303             0u,
304             0u
305         },
306         /**
307          * \brief To Configure the Threshold level of number of events
308          * that can be queued up in the Event queues. EDMA3CC error register
309          * (CCERR) will indicate whether or not at any instant of time the
310          * number of events queued up in any of the event queues exceeds
311          * or equals the threshold/watermark value that is set
312          * in the queue watermark threshold register (QWMTHRA).
313          */
314         {
315             16u,
316             16u,
317             16u,
318             16u,
319             0u,
320             0u,
321             0u,
322             0u
323         },
325         /**
326          * \brief To Configure the Default Burst Size (DBS) of TCs.
327          * An optimally-sized command is defined by the transfer controller
328          * default burst size (DBS). Different TCs can have different
329          * DBS values. It is defined in Bytes.
330          */
331             {
332             16u,
333             16u,
334             0u,
335             0u,
336             0u,
337             0u,
338             0u,
339             0u
340             },
342         /**
343          * \brief Mapping from each DMA channel to a Parameter RAM set,
344          * if it exists, otherwise of no use.
345          */
346             {
347             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
348             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
349             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
350             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
351             32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
352             40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
353             48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
354             56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
355             },
357          /**
358           * \brief Mapping from each DMA channel to a TCC. This specific
359           * TCC code will be returned when the transfer is completed
360           * on the mapped channel.
361           */
362             {
363             0u, 1u, 2u, 3u,
364             4u, 5u, 6u, 7u,
365             8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
366             12u, 13u, 14u, 15u,
367             16u, 17u, 18u, 19u,
368             20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
369             24u, 25u, 26u, 27u,
370             28u, 29u, 30u, 31u,
371             32u, 33u, 34u, 35u,
372             36u, 37u, 38u, 39u,
373             40u, 41u, 42u, 43u,
374             44u, 45u, 46u, 47u,
375             48u, 49u, 50u, 51u,
376             52u, 53u, 54u, 55u,
377             56u, 57u, 58u, 59u,
378             60u, 61u, 62u, 63u
379             },
381         /**
382          * \brief Mapping of DMA channels to Hardware Events from
383          * various peripherals, which use EDMA for data transfer.
384          * All channels need not be mapped, some can be free also.
385          */
386             {
387             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
388             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
389             }
390         },
391 };
394 /* Driver Instance Initialization Configuration */
395 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
397     /* EDMA3 INSTANCE# 0 */
398     {
399         /* Resources owned/reserved by region 0 */
400         {
401             /* ownPaRAMSets */
402             /* 31     0     63    32     95    64     127   96 */
403             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
404             /* 159  128     191  160     223  192     255  224 */
405              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
406             /* 287  256     319  288     351  320     383  352 */
407              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
408             /* 415  384     447  416     479  448     511  480 */
409              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
411             /* ownDmaChannels */
412             /* 31     0     63    32 */
413             {0x00000000u, 0x00000000u},
415             /* ownQdmaChannels */
416             /* 31     0 */
417             {0x00000000u},
419             /* ownTccs */
420             /* 31     0     63    32 */
421             {0x00000000u, 0x00000000u},
423             /* resvdPaRAMSets */
424             /* 31     0     63    32     95    64     127   96 */
425             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
426             /* 159  128     191  160     223  192     255  224 */
427              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
428             /* 287  256     319  288     351  320     383  352 */
429              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
430             /* 415  384     447  416     479  448     511  480 */
431              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
433             /* resvdDmaChannels */
434             /* 31     0     63    32 */
435             {0x00000000u, 0x00000000u},
437             /* resvdQdmaChannels */
438             /* 31     0 */
439             {0x00000000u},
441             /* resvdTccs */
442             /* 31     0     63    32 */
443             {0x00000000u, 0x00000000u},
444         },
445         /* Resources owned/reserved by region 1 */
446         {
447             /* ownPaRAMSets */
448             /* 31     0     63    32     95    64     127   96 */
449             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
450             /* 159  128     191  160     223  192     255  224 */
451              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
452             /* 287  256     319  288     351  320     383  352 */
453              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
454             /* 415  384     447  416     479  448     511  480 */
455              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
457             /* ownDmaChannels */
458             /* 31     0     63    32 */
459             {0xFFFFFFFFu, 0x00000000u},
461             /* ownQdmaChannels */
462             /* 31     0 */
463             {0x000000FFu},
465             /* ownTccs */
466             /* 31     0     63    32 */
467             {0xFFFFFFFFu, 0x00000000u},
469             /* Resources reserved by Region 1 */
470             /* resvdPaRAMSets */
471             /* 31     0     63    32     95    64     127   96 */
472             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
473             /* 159  128     191  160     223  192     255  224 */
474              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
475             /* 287  256     319  288     351  320     383  352 */
476              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
477             /* 415  384     447  416     479  448     511  480 */
478              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
480             /* resvdDmaChannels */
481             /* 31       0 */
482             {0xFF3FF3FFu,
483             /* 63..32 */
484             0x00000000u},
486             /* resvdQdmaChannels */
487             /* 31     0 */
488             {0x00000000u},
490             /* resvdTccs */
491             /* 31       0 */
492             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
493             /* 63..32 */
494             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
495         },
496         /* Resources owned/reserved by region 2 */
497         {
498             /* ownPaRAMSets */
499             /* 31     0     63    32     95    64     127   96 */
500             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
501             /* 159  128     191  160     223  192     255  224 */
502              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
503             /* 287  256     319  288     351  320     383  352 */
504              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
505             /* 415  384     447  416     479  448     511  480 */
506              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
508             /* ownDmaChannels */
509             /* 31     0     63    32 */
510             {0x00000000u, 0x00000000u},
512             /* ownQdmaChannels */
513             /* 31     0 */
514             {0x00000000u},
516             /* ownTccs */
517             /* 31     0     63    32 */
518             {0x00000000u, 0x00000000u},
520             /* resvdPaRAMSets */
521             /* 31     0     63    32     95    64     127   96 */
522             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
523             /* 159  128     191  160     223  192     255  224 */
524              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
525             /* 287  256     319  288     351  320     383  352 */
526              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
527             /* 415  384     447  416     479  448     511  480 */
528              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
530             /* resvdDmaChannels */
531             /* 31     0     63    32 */
532             {0x00000000u, 0x00000000u},
534             /* resvdQdmaChannels */
535             /* 31     0 */
536             {0x00000000u},
538             /* resvdTccs */
539             /* 31     0     63    32 */
540             {0x00000000u, 0x00000000u},
541         },
543         /* Resources owned/reserved by region 3 */
544         {
545             /* ownPaRAMSets */
546             /* 31     0     63    32     95    64     127   96 */
547             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
548             /* 159  128     191  160     223  192     255  224 */
549              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
550             /* 287  256     319  288     351  320     383  352 */
551              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
552             /* 415  384     447  416     479  448     511  480 */
553              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
555             /* ownDmaChannels */
556             /* 31     0     63    32 */
557             {0x00000000u, 0x00000000u},
559             /* ownQdmaChannels */
560             /* 31     0 */
561             {0x00000000u},
563             /* ownTccs */
564             /* 31     0     63    32 */
565             {0x00000000u, 0x00000000u},
567             /* resvdPaRAMSets */
568             /* 31     0     63    32     95    64     127   96 */
569             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
570             /* 159  128     191  160     223  192     255  224 */
571              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
572             /* 287  256     319  288     351  320     383  352 */
573              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
574             /* 415  384     447  416     479  448     511  480 */
575              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
577             /* resvdDmaChannels */
578             /* 31     0     63    32 */
579             {0x00000000u, 0x00000000u},
581             /* resvdQdmaChannels */
582             /* 31     0 */
583             {0x00000000u},
585             /* resvdTccs */
586             /* 31     0     63    32 */
587             {0x00000000u, 0x00000000u},
588         },
590         /* Resources owned/reserved by region 4 */
591         {
592             /* ownPaRAMSets */
593             /* 31     0     63    32     95    64     127   96 */
594             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
595             /* 159  128     191  160     223  192     255  224 */
596              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
597             /* 287  256     319  288     351  320     383  352 */
598              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
599             /* 415  384     447  416     479  448     511  480 */
600              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
602             /* ownDmaChannels */
603             /* 31     0     63    32 */
604             {0x00000000u, 0x00000000u},
606             /* ownQdmaChannels */
607             /* 31     0 */
608             {0x00000000u},
610             /* ownTccs */
611             /* 31     0     63    32 */
612             {0x00000000u, 0x00000000u},
614             /* resvdPaRAMSets */
615             /* 31     0     63    32     95    64     127   96 */
616             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
617             /* 159  128     191  160     223  192     255  224 */
618              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
619             /* 287  256     319  288     351  320     383  352 */
620              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
621             /* 415  384     447  416     479  448     511  480 */
622              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
624             /* resvdDmaChannels */
625             /* 31     0     63    32 */
626             {0x00000000u, 0x00000000u},
628             /* resvdQdmaChannels */
629             /* 31     0 */
630             {0x00000000u},
632             /* resvdTccs */
633             /* 31     0     63    32 */
634             {0x00000000u, 0x00000000u},
635         },
637         /* Resources owned/reserved by region 5 */
638         {
639             /* ownPaRAMSets */
640             /* 31     0     63    32     95    64     127   96 */
641             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
642             /* 159  128     191  160     223  192     255  224 */
643              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
644             /* 287  256     319  288     351  320     383  352 */
645              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
646             /* 415  384     447  416     479  448     511  480 */
647              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
649             /* ownDmaChannels */
650             /* 31     0     63    32 */
651             {0x00000000u, 0x00000000u},
653             /* ownQdmaChannels */
654             /* 31     0 */
655             {0x00000000u},
657             /* ownTccs */
658             /* 31     0     63    32 */
659             {0x00000000u, 0x00000000u},
661             /* resvdPaRAMSets */
662             /* 31     0     63    32     95    64     127   96 */
663             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
664             /* 159  128     191  160     223  192     255  224 */
665              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
666             /* 287  256     319  288     351  320     383  352 */
667              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
668             /* 415  384     447  416     479  448     511  480 */
669              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
671             /* resvdDmaChannels */
672             /* 31     0     63    32 */
673             {0x00000000u, 0x00000000u},
675             /* resvdQdmaChannels */
676             /* 31     0 */
677             {0x00000000u},
679             /* resvdTccs */
680             /* 31     0     63    32 */
681             {0x00000000u, 0x00000000u},
682         },
684         /* Resources owned/reserved by region 6 */
685         {
686             /* ownPaRAMSets */
687             /* 31     0     63    32     95    64     127   96 */
688             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
689             /* 159  128     191  160     223  192     255  224 */
690              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
691             /* 287  256     319  288     351  320     383  352 */
692              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
693             /* 415  384     447  416     479  448     511  480 */
694              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
696             /* ownDmaChannels */
697             /* 31     0     63    32 */
698             {0x00000000u, 0x00000000u},
700             /* ownQdmaChannels */
701             /* 31     0 */
702             {0x00000000u},
704             /* ownTccs */
705             /* 31     0     63    32 */
706             {0x00000000u, 0x00000000u},
708             /* resvdPaRAMSets */
709             /* 31     0     63    32     95    64     127   96 */
710             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
711             /* 159  128     191  160     223  192     255  224 */
712              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
713             /* 287  256     319  288     351  320     383  352 */
714              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
715             /* 415  384     447  416     479  448     511  480 */
716              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
718             /* resvdDmaChannels */
719             /* 31     0     63    32 */
720             {0x00000000u, 0x00000000u},
722             /* resvdQdmaChannels */
723             /* 31     0 */
724             {0x00000000u},
726             /* resvdTccs */
727             /* 31     0     63    32 */
728             {0x00000000u, 0x00000000u},
729         },
731         /* Resources owned/reserved by region 7 */
732         {
733             /* ownPaRAMSets */
734             /* 31     0     63    32     95    64     127   96 */
735             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
736             /* 159  128     191  160     223  192     255  224 */
737              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
738             /* 287  256     319  288     351  320     383  352 */
739              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
740             /* 415  384     447  416     479  448     511  480 */
741              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
743             /* ownDmaChannels */
744             /* 31     0     63    32 */
745             {0x00000000u, 0x00000000u},
747             /* ownQdmaChannels */
748             /* 31     0 */
749             {0x00000000u},
751             /* ownTccs */
752             /* 31     0     63    32 */
753             {0x00000000u, 0x00000000u},
755             /* resvdPaRAMSets */
756             /* 31     0     63    32     95    64     127   96 */
757             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
758             /* 159  128     191  160     223  192     255  224 */
759              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
760             /* 287  256     319  288     351  320     383  352 */
761              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
762             /* 415  384     447  416     479  448     511  480 */
763              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
765             /* resvdDmaChannels */
766             /* 31     0     63    32 */
767             {0x00000000u, 0x00000000u},
769             /* resvdQdmaChannels */
770             /* 31     0 */
771             {0x00000000u},
773             /* resvdTccs */
774             /* 31     0     63    32 */
775             {0x00000000u, 0x00000000u},
776         },
777     }
778 };
780 /* Driver Instance Cross bar event to channel map Initialization Configuration */
781 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
783     /* EDMA3 INSTANCE# 0 */
784     {
785         /* Event to channel map for region 0 */
786         {
787             -1, -1, -1, -1, -1, -1, -1, -1,
788             -1, -1, -1, -1, -1, -1, -1, -1,
789             -1, -1, -1, -1, -1, -1, -1, -1,
790             -1, -1, -1, -1, -1, -1, -1
791         },
792         /* Event to channel map for region 1 */
793         {
794             -1, -1, -1, -1, -1, -1, -1, -1,
795             -1, -1, -1, -1, -1, -1, -1, -1,
796             -1, -1, -1, -1, -1, -1, -1, -1,
797             -1, -1, -1, -1, -1, -1, -1
798         },
799         /* Event to channel map for region 2 */
800         {
801             -1, -1, -1, -1, -1, -1, -1, -1,
802             -1, -1, -1, -1, -1, -1, -1, -1,
803             -1, -1, -1, -1, -1, -1, -1, -1,
804             -1, -1, -1, -1, -1, -1, -1
805         },
806         /* Event to channel map for region 3 */
807         {
808             -1, -1, -1, -1, -1, -1, -1, -1,
809             -1, -1, -1, -1, -1, -1, -1, -1,
810             -1, -1, -1, -1, -1, -1, -1, -1,
811             -1, -1, -1, -1, -1, -1, -1
812         },
813         /* Event to channel map for region 4 */
814         {
815             -1, -1, -1, -1, -1, -1, -1, -1,
816             -1, -1, -1, -1, -1, -1, -1, -1,
817             -1, -1, -1, -1, -1, -1, -1, -1,
818             -1, -1, -1, -1, -1, -1, -1
819         },
820         /* Event to channel map for region 5 */
821         {
822             -1, -1, -1, -1, -1, -1, -1, -1,
823             -1, -1, -1, -1, -1, -1, -1, -1,
824             -1, -1, -1, -1, -1, -1, -1, -1,
825             -1, -1, -1, -1, -1, -1, -1
826         },
827         /* Event to channel map for region 6 */
828         {
829             -1, -1, -1, -1, -1, -1, -1, -1,
830             -1, -1, -1, -1, -1, -1, -1, -1,
831             -1, -1, -1, -1, -1, -1, -1, -1,
832             -1, -1, -1, -1, -1, -1, -1
833         },
834         /* Event to channel map for region 7 */
835         {
836             -1, -1, -1, -1, -1, -1, -1, -1,
837             -1, -1, -1, -1, -1, -1, -1, -1,
838             -1, -1, -1, -1, -1, -1, -1, -1,
839             -1, -1, -1, -1, -1, -1, -1
840         },
841     }
842 };
844 /* End of File */