[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_ti816x_arm_int_reg.c
1 /*
2 * sample_dm740_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
41 #include <ti/sysbios/hal/Hwi.h>
42 #include <xdc/runtime/Error.h>
43 #include <xdc/runtime/System.h>
45 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
47 // #include <stdio.h>
48 /**
49 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
50 * (Not all TC error ISRs need to be registered, register only for the
51 * available Transfer Controllers).
52 */
53 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
54 {
55 &lisrEdma3TC0ErrHandler0,
56 &lisrEdma3TC1ErrHandler0,
57 &lisrEdma3TC2ErrHandler0,
58 &lisrEdma3TC3ErrHandler0,
59 &lisrEdma3TC4ErrHandler0,
60 &lisrEdma3TC5ErrHandler0,
61 &lisrEdma3TC6ErrHandler0,
62 &lisrEdma3TC7ErrHandler0,
63 };
65 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
66 extern unsigned int ccErrorInt[];
67 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
68 extern unsigned int numEdma3Tc[];
70 /**
71 * Variables which will be used internally for referring the hardware interrupt
72 * for various EDMA3 interrupts.
73 */
74 extern unsigned int hwIntXferComp;
75 extern unsigned int hwIntCcErr;
76 extern unsigned int hwIntTcErr;
78 extern unsigned int dsp_num;
79 /* This variable has to be used as an extern */
80 //unsigned int gpp_num = 4;
82 Hwi_Handle hwiCCXferCompInt;
83 Hwi_Handle hwiCCErrInt;
84 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
86 /** To Register the ISRs with the underlying OS, if required. */
87 void registerEdma3Interrupts (unsigned int edma3Id)
88 {
89 static UInt32 cookie = 0;
90 unsigned int numTc = 0;
91 Hwi_Params hwiParams;
92 Error_Block eb;
94 /* Initialize the Error Block */
95 Error_init(&eb);
97 /* Disabling the global interrupts */
98 cookie = Hwi_disable();
100 /* Initialize the HWI parameters with user specified values */
101 Hwi_Params_init(&hwiParams);
103 /* argument for the ISR */
104 hwiParams.arg = edma3Id;
105 /* set the priority ID */
106 //hwiParams.priority = hwIntXferComp;
107 //hwiParams.enableInt = TRUE;
109 hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
110 (&lisrEdma3ComplHandler0),
111 (const Hwi_Params *) (&hwiParams),
112 &eb);
113 if (TRUE == Error_check(&eb))
114 {
115 System_printf("HWI Create Failed\n",Error_getCode(&eb));
116 }
119 #ifdef BUILD_NETRA_A8
120 /* Initialize the HWI parameters with user specified values */
121 Hwi_Params_init(&hwiParams);
122 /* argument for the ISR */
123 hwiParams.arg = edma3Id;
124 /* set the priority ID */
125 hwiParams.priority = hwIntCcErr;
126 //hwiParams.enableInt = TRUE;
128 hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
129 (&lisrEdma3CCErrHandler0),
130 (const Hwi_Params *) (&hwiParams),
131 &eb);
133 if (TRUE == Error_check(&eb))
134 {
135 System_printf("HWI Create Failed\n",Error_getCode(&eb));
136 }
138 while (numTc < numEdma3Tc[edma3Id])
139 {
140 /* Initialize the HWI parameters with user specified values */
141 Hwi_Params_init(&hwiParams);
142 /* argument for the ISR */
143 hwiParams.arg = edma3Id;
144 /* set the priority ID */
145 hwiParams.priority = hwIntTcErr;
146 //hwiParams.enableInt = TRUE;
148 hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
149 (ptrEdma3TcIsrHandler[numTc]),
150 (const Hwi_Params *) (&hwiParams),
151 &eb);
152 if (TRUE == Error_check(&eb))
153 {
154 System_printf("HWI Create Failed\n",Error_getCode(&eb));
155 }
156 numTc++;
157 }
158 /**
159 * Enabling the HWI_ID.
160 * EDMA3 interrupts (transfer completion, CC error etc.)
161 * correspond to different ECM events (SoC specific). These ECM events come
162 * under ECM block XXX (handling those specific ECM events). Normally, block
163 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
164 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
165 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
166 * mapped HWI_INT YYY, one should use the corresponding bitmask in the
167 * API C64_enableIER(), in which the YYY bit is SET.
168 */
169 Hwi_enableInterrupt(ccErrorInt[edma3Id]);
170 Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
171 numTc = 0;
172 while (numTc < numEdma3Tc[edma3Id])
173 {
174 Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
175 numTc++;
176 }
178 #endif
180 /* Restore interrupts */
181 Hwi_restore(cookie);
182 }
184 /** To Unregister the ISRs with the underlying OS, if previously registered. */
185 void unregisterEdma3Interrupts (unsigned int edma3Id)
186 {
187 static UInt32 cookie = 0;
188 unsigned int numTc = 0;
190 /* Disabling the global interrupts */
191 cookie = Hwi_disable();
193 Hwi_delete(&hwiCCXferCompInt);
194 Hwi_delete(&hwiCCErrInt);
195 while (numTc < numEdma3Tc[edma3Id])
196 {
197 Hwi_delete(&hwiTCErrInt[numTc]);
198 numTc++;
199 }
200 /* Restore interrupts */
201 Hwi_restore(cookie);
202 }