packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_cfg.c

   1 /*
   2  * sample_dm740_cfg.c
   3  *
   4  * Platform specific EDMA3 hardware related information like number of transfer
   5  * controllers, various interrupt ids etc. It is used while interrupts
   6  * enabling / disabling. It needs to be ported for different SoCs.
   7  *
   8  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   9  *
  10  *
  11  *  Redistribution and use in source and binary forms, with or without
  12  *  modification, are permitted provided that the following conditions
  13  *  are met:
  14  *
  15  *    Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  *
  18  *    Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the
  21  *    distribution.
  22  *
  23  *    Neither the name of Texas Instruments Incorporated nor the names of
  24  *    its contributors may be used to endorse or promote products derived
  25  *    from this software without specific prior written permission.
  26  *
  27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39 */
  40
  41 #include <ti/sdo/edma3/drv/edma3_drv.h>
  42
  43 /* Number of EDMA3 controllers present in the system */
  44 #define NUM_EDMA3_INSTANCES                     1u
  45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
  46
  47 /* Number of DSPs present in the system */
  48 #define NUM_DSPS                                        1u
  49 const unsigned int numDsps = NUM_DSPS;
  50
  51 /* Determine the processor id by reading DNUM register. */
  52 unsigned short determineProcId()
  53         {
  54 #if 0
  55         volatile unsigned int *addr;
  56         unsigned int core_no;
  57
  58     /* Identify the core number */
  59     addr = (unsigned int *)(CGEM_REG_START+0x40000);
  60     core_no = ((*addr) & 0x000F0000)>>16;
  61
  62         return core_no;
  63 #endif
  64
  65 #ifdef BUILD_NETRA_A8
  66         return 0;
  67 #elif defined BUILD_NETRA_DSP
  68         return 1;
  69 #elif defined BUILD_NETRA_M3VPSS
  70         return 4;
  71 #elif defined BUILD_NETRA_M3VIDEO
  72         return 5;
  73 #else
  74         return 1;
  75 #endif
  76         }
  77
  78 signed char*  getGlobalAddr(signed char* addr)
  79 {
  80      return (addr); /* The address is already a global address */
  81 }
  82
  83 unsigned short isGblConfigRequired(unsigned int dspNum)
  84         {
  85         (void) dspNum;
  86 #ifdef BUILD_NETRA_DSP
  87         return 1;
  88 #else
  89         return 0;
  90 #endif
  91         }
  92
  93 /* Semaphore handles */
  94 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  95
  96 /** Number of PaRAM Sets available */
  97 #define EDMA3_NUM_PARAMSET                              (512u)
  98 /** Number of TCCS available */
  99 #define EDMA3_NUM_TCC                                   (64u)
 100 /** Number of Event Queues available */
 101 #define EDMA3_NUM_EVTQUE                                (4u)
 102 /** Number of Transfer Controllers available */
 103 #define EDMA3_NUM_TC                                    (4u)
 104
 105 /** Interrupt no. for Transfer Completion */
 106 #define EDMA3_CC_XFER_COMPLETION_INT_A8                 (12u)
 107 #define EDMA3_CC_XFER_COMPLETION_INT_DSP                (20u)
 108 #define EDMA3_CC_XFER_COMPLETION_INT_M3VPSS             (63u)
 109 #define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO            (62u)
 110
 111 #ifdef BUILD_NETRA_A8
 112 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A8
 113 #elif defined BUILD_NETRA_DSP
 114 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
 115 #elif defined BUILD_NETRA_M3VIDEO
 116 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO
 117 #elif defined BUILD_NETRA_M3VPSS
 118 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
 119 #else
 120 #define EDMA3_CC_XFER_COMPLETION_INT                    {0u}
 121 #endif
 122
 123 /** Interrupt no. for CC Error */
 124 #define EDMA3_CC_ERROR_INT_A8                           (14u)
 125 #define EDMA3_CC_ERROR_INT_DSP                          (21u)
 126
 127 #ifdef BUILD_NETRA_A8
 128 #define EDMA3_CC_ERROR_INT                              {EDMA3_CC_ERROR_INT_A8}
 129 #elif defined BUILD_NETRA_DSP
 130 #define EDMA3_CC_ERROR_INT                              {EDMA3_CC_ERROR_INT_DSP}
 131 #else
 132 #define EDMA3_CC_ERROR_INT                              (0u)
 133 #endif
 134
 135 /** Interrupt no. for TCs Error */
 136 #define EDMA3_TC0_ERROR_INT_DSP                         (22u)
 137 #define EDMA3_TC0_ERROR_INT_A8                          (112u)
 138 #define EDMA3_TC1_ERROR_INT_A8                          (113u)
 139 #define EDMA3_TC2_ERROR_INT_A8                          (114u)
 140 #define EDMA3_TC3_ERROR_INT_A8                          (115u)
 141
 142 #ifdef BUILD_NETRA_A8
 143 #define EDMA3_TC0_ERROR_INT                             {EDMA3_TC0_ERROR_INT_A8}
 144 #define EDMA3_TC1_ERROR_INT                             {EDMA3_TC0_ERROR_INT_A8}
 145 #define EDMA3_TC2_ERROR_INT                             {EDMA3_TC0_ERROR_INT_A8}
 146 #define EDMA3_TC3_ERROR_INT                             {EDMA3_TC0_ERROR_INT_A8}
 147 #elif defined BUILD_NETRA_DSP
 148 #define EDMA3_TC0_ERROR_INT                             {EDMA3_TC0_ERROR_INT_DSP}
 149 #define EDMA3_TC1_ERROR_INT                             (0u)
 150 #define EDMA3_TC2_ERROR_INT                             (0u)
 151 #define EDMA3_TC3_ERROR_INT                             (0u)
 152 #else
 153 #define EDMA3_TC0_ERROR_INT                             (0u)
 154 #define EDMA3_TC1_ERROR_INT                             (0u)
 155 #define EDMA3_TC2_ERROR_INT                             (0u)
 156 #define EDMA3_TC3_ERROR_INT                             (0u)
 157 #endif
 158
 159 #define EDMA3_TC4_ERROR_INT                             (0u)
 160 #define EDMA3_TC5_ERROR_INT                             (0u)
 161 #define EDMA3_TC6_ERROR_INT                             (0u)
 162 #define EDMA3_TC7_ERROR_INT                             (0u)
 163
 164 /**
 165 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
 166 * ECM events (SoC specific). These ECM events come
 167 * under ECM block XXX (handling those specific ECM events). Normally, block
 168 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
 169 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
 170 * is mapped to a specific HWI_INT YYY in the tcf file.
 171 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
 172 * to transfer completion interrupt.
 173 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
 174 * to CC error interrupts.
 175 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
 176 * to TC error interrupts.
 177 */
 178 #define EDMA3_HWI_INT_XFER_COMP                                                 (7u)
 179 #define EDMA3_HWI_INT_CC_ERR                                                    (7u)
 180 #define EDMA3_HWI_INT_TC_ERR                                                    (7u)
 181
 182
 183 /**
 184  * \brief Mapping of DMA channels 0-31 to Hardware Events from
 185  * various peripherals, which use EDMA for data transfer.
 186  * All channels need not be mapped, some can be free also.
 187  * 1: Mapped
 188  * 0: Not mapped
 189  *
 190  * This mapping will be used to allocate DMA channels when user passes
 191  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 192  * copy). The same mapping is used to allocate the TCC when user passes
 193  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 194  *
 195  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 196  */
 197                                                                                                           /* 31     0 */
 198 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
 199
 200 /**
 201  * \brief Mapping of DMA channels 32-63 to Hardware Events from
 202  * various peripherals, which use EDMA for data transfer.
 203  * All channels need not be mapped, some can be free also.
 204  * 1: Mapped
 205  * 0: Not mapped
 206  *
 207  * This mapping will be used to allocate DMA channels when user passes
 208  * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 209  * copy). The same mapping is used to allocate the TCC when user passes
 210  * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 211  *
 212  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 213  */
 214                                                                                                           /* 63     32 */
 215 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
 216
 217 /* Variable which will be used internally for referring number of Event Queues. */
 218 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
 219
 220 /* Variable which will be used internally for referring number of TCs. */
 221 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
 222
 223 /**
 224  * Variable which will be used internally for referring transfer completion
 225  * interrupt.
 226  */
 227 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
 228                                                         {
 229                                                         EDMA3_CC_XFER_COMPLETION_INT_A8, EDMA3_CC_XFER_COMPLETION_INT_DSP, 0u, 0u,
 230                                                         EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO, EDMA3_CC_XFER_COMPLETION_INT_M3VPSS, 0u, 0u,
 231                                                         },
 232                         };
 233
 234 /**
 235  * Variable which will be used internally for referring channel controller's
 236  * error interrupt.
 237  */
 238 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
 239
 240 /**
 241  * Variable which will be used internally for referring transfer controllers'
 242  * error interrupts.
 243  */
 244 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
 245                                 {
 246                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
 247                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
 248                                 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
 249                                 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
 250                                 }
 251                             };
 252
 253 /**
 254  * Variables which will be used internally for referring the hardware interrupt
 255  * for various EDMA3 interrupts.
 256  */
 257 unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
 258 unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
 259 unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
 260
 261 /**
 262  * \brief Base address as seen from the different cores may be different
 263  * And is defined based on the core
 264  */
 265 #ifdef BUILD_NETRA_DSP
 266 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x09000000))
 267 #define EDMA3_TC0_BASE_ADDR                          ((void *)(0x09800000))
 268 #define EDMA3_TC1_BASE_ADDR                          ((void *)(0x09900000))
 269 #define EDMA3_TC2_BASE_ADDR                          ((void *)(0x09A00000))
 270 #define EDMA3_TC3_BASE_ADDR                          ((void *)(0x09B00000))
 271 #else
 272 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x49000000))
 273 #define EDMA3_TC0_BASE_ADDR                          ((void *)(0x49800000))
 274 #define EDMA3_TC1_BASE_ADDR                          ((void *)(0x49900000))
 275 #define EDMA3_TC2_BASE_ADDR                          ((void *)(0x49A00000))
 276 #define EDMA3_TC3_BASE_ADDR                          ((void *)(0x49B00000))
 277 #endif
 278
 279
 280 /* Driver Object Initialization Configuration */
 281 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
 282         {
 283             {
 284             /** Total number of DMA Channels supported by the EDMA3 Controller */
 285             64u,
 286             /** Total number of QDMA Channels supported by the EDMA3 Controller */
 287             8u,
 288             /** Total number of TCCs supported by the EDMA3 Controller */
 289             64u,
 290             /** Total number of PaRAM Sets supported by the EDMA3 Controller */
 291             512u,
 292             /** Total number of Event Queues in the EDMA3 Controller */
 293             4u,
 294             /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
 295             4u,
 296             /** Number of Regions on this EDMA3 controller */
 297             6u,
 298
 299             /**
 300              * \brief Channel mapping existence
 301              * A value of 0 (No channel mapping) implies that there is fixed association
 302              * for a channel number to a parameter entry number or, in other words,
 303              * PaRAM entry n corresponds to channel n.
 304              */
 305             1u,
 306
 307             /** Existence of memory protection feature */
 308             1u,
 309
 310             /** Global Register Region of CC Registers */
 311             EDMA3_CC_BASE_ADDR,
 312             /** Transfer Controller (TC) Registers */
 313                 {
 314                 EDMA3_TC0_BASE_ADDR,
 315                 EDMA3_TC1_BASE_ADDR,
 316                 EDMA3_TC2_BASE_ADDR,
 317                 EDMA3_TC3_BASE_ADDR,
 318                 (void *)NULL,
 319                 (void *)NULL,
 320                 (void *)NULL,
 321                 (void *)NULL
 322                 },
 323             /** Interrupt no. for Transfer Completion */
 324             EDMA3_CC_XFER_COMPLETION_INT,
 325             /** Interrupt no. for CC Error */
 326             EDMA3_CC_ERROR_INT,
 327             /** Interrupt no. for TCs Error */
 328                 {
 329                 EDMA3_TC0_ERROR_INT,
 330                 EDMA3_TC1_ERROR_INT,
 331                 EDMA3_TC2_ERROR_INT,
 332                 EDMA3_TC3_ERROR_INT,
 333                 EDMA3_TC4_ERROR_INT,
 334                 EDMA3_TC5_ERROR_INT,
 335                 EDMA3_TC6_ERROR_INT,
 336                 EDMA3_TC7_ERROR_INT
 337                 },
 338
 339             /**
 340              * \brief EDMA3 TC priority setting
 341              *
 342              * User can program the priority of the Event Queues
 343              * at a system-wide level.  This means that the user can set the
 344              * priority of an IO initiated by either of the TCs (Transfer Controllers)
 345              * relative to IO initiated by the other bus masters on the
 346              * device (ARM, DSP, USB, etc)
 347              */
 348                 {
 349                 0u,
 350                 1u,
 351                 2u,
 352                 3u,
 353                 0u,
 354                 0u,
 355                 0u,
 356                 0u
 357                 },
 358             /**
 359              * \brief To Configure the Threshold level of number of events
 360              * that can be queued up in the Event queues. EDMA3CC error register
 361              * (CCERR) will indicate whether or not at any instant of time the
 362              * number of events queued up in any of the event queues exceeds
 363              * or equals the threshold/watermark value that is set
 364              * in the queue watermark threshold register (QWMTHRA).
 365              */
 366                 {
 367                 16u,
 368                 16u,
 369                 16u,
 370                 16u,
 371                 0u,
 372                 0u,
 373                 0u,
 374                 0u
 375                 },
 376
 377             /**
 378              * \brief To Configure the Default Burst Size (DBS) of TCs.
 379              * An optimally-sized command is defined by the transfer controller
 380              * default burst size (DBS). Different TCs can have different
 381              * DBS values. It is defined in Bytes.
 382              */
 383                 {
 384                 16u,
 385                 16u,
 386                 16u,
 387                 16u,
 388                 0u,
 389                 0u,
 390                 0u,
 391                 0u
 392                 },
 393
 394             /**
 395              * \brief Mapping from each DMA channel to a Parameter RAM set,
 396              * if it exists, otherwise of no use.
 397              */
 398                 {
 399                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 400                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 401                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 402                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 403                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 404                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 405                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 406                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 407                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 408                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 409                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 410                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 411                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 412                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 413                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 414                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 415                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 416                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 417                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 418                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 419                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 420                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 421                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 422                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 423                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 424                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 425                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 426                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 427                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 428                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 429                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
 430                 EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP
 431                 },
 432
 433              /**
 434               * \brief Mapping from each DMA channel to a TCC. This specific
 435               * TCC code will be returned when the transfer is completed
 436               * on the mapped channel.
 437               */
 438                 {
 439                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 440                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 441                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 442                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 443                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 444                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 445                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 446                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 447                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 448                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 449                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 450                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 451                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 452                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 453                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
 454                 EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP
 455                 },
 456
 457             /**
 458              * \brief Mapping of DMA channels to Hardware Events from
 459              * various peripherals, which use EDMA for data transfer.
 460              * All channels need not be mapped, some can be free also.
 461              */
 462                 {
 463                 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
 464                 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
 465                 },
 466                 },
 467         };
 468
 469 /**
 470  * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
 471  * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
 472  * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
 473  * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
 474  *
 475  * Only Resources owned by a perticular core are allocated by Driver
 476  * Reserved resources are not allocated if requested for any available resource
 477  */
 478
 479 /* Defines for Own DMA channels For different cores */
 480 /* channels  0 to 31 */
 481 #define EDMA3_OWN_DMA_CHANNELS_0_A8    (0xFFFFFFFFu)
 482 #define EDMA3_OWN_DMA_CHANNELS_0_DSP   (0xFFFFFFFFu)
 483 #define EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO    (0xFFFFFFFFu)
 484 #define EDMA3_OWN_DMA_CHANNELS_0_M3VPSS    (0xFFFFFFFFu)
 485 /* Channels 32 to 63 */
 486 #define EDMA3_OWN_DMA_CHANNELS_1_A8    (0xFFFFFFFFu)
 487 #define EDMA3_OWN_DMA_CHANNELS_1_DSP   (0xFFFFFFFFu)
 488 #define EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO    (0xFFFFFFFFu)
 489 #define EDMA3_OWN_DMA_CHANNELS_1_M3VPSS    (0xFFFFFFFFu)
 490
 491 /* Defines for Own QDMA channels For different cores */
 492 #define EDMA3_OWN_QDMA_CHANNELS_0_A8    (0x000000FFu)
 493 #define EDMA3_OWN_QDMA_CHANNELS_0_DSP   (0x000000FFu)
 494 #define EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO    (0x000000FFu)
 495 #define EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS    (0x000000FFu)
 496
 497 /* Defines for Own TCCs For different cores */
 498 #define EDMA3_OWN_TCC_0_A8    (0xFFFFFFFFu)
 499 #define EDMA3_OWN_TCC_0_DSP   (0xFFFFFFFFu)
 500 #define EDMA3_OWN_TCC_0_M3VIDEO    (0xFFFFFFFFu)
 501 #define EDMA3_OWN_TCC_0_M3VPSS    (0xFFFFFFFFu)
 502 /* Channels 32 to 63 */
 503 #define EDMA3_OWN_TCC_1_A8    (0xFFFFFFFFu)
 504 #define EDMA3_OWN_TCC_1_DSP   (0xFFFFFFFFu)
 505 #define EDMA3_OWN_TCC_1_M3VIDEO    (0xFFFFFFFFu)
 506 #define EDMA3_OWN_TCC_1_M3VPSS    (0xFFFFFFFFu)
 507
 508 /* Defines for Reserved DMA channels For different cores */
 509 /* channels  0 to 31 */
 510 #define EDMA3_RESERVED_DMA_CHANNELS_0_A8    (0x00u)
 511 #define EDMA3_RESERVED_DMA_CHANNELS_0_DSP   (0x00u)
 512 #define EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO    (0x00u)
 513 #define EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS    (0x00u)
 514 /* Channels 32 to 63 */
 515 #define EDMA3_RESERVED_DMA_CHANNELS_1_A8    (0x00u)
 516 #define EDMA3_RESERVED_DMA_CHANNELS_1_DSP   (0x00u)
 517 #define EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO    (0x00u)
 518 #define EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS    (0x00u)
 519
 520 /* Defines for RESERVED QDMA channels For different cores */
 521 #define EDMA3_RESERVED_QDMA_CHANNELS_0_A8    (0x00u)
 522 #define EDMA3_RESERVED_QDMA_CHANNELS_0_DSP   (0x00u)
 523 #define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO    (0x00u)
 524 #define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS    (0x00u)
 525
 526 /* Defines for RESERVED TCCs For different cores */
 527 #define EDMA3_RESERVED_TCC_0_A8    (0x00u)
 528 #define EDMA3_RESERVED_TCC_0_DSP   (0x00u)
 529 #define EDMA3_RESERVED_TCC_0_M3VIDEO    (0x00u)
 530 #define EDMA3_RESERVED_TCC_0_M3VPSS    (0x00u)
 531 /* Channels 32 to 63 */
 532 #define EDMA3_RESERVED_TCC_1_A8    (0x00u)
 533 #define EDMA3_RESERVED_TCC_1_DSP   (0x00u)
 534 #define EDMA3_RESERVED_TCC_1_M3VIDEO    (0x00u)
 535 #define EDMA3_RESERVED_TCC_1_M3VPSS    (0x00u)
 536
 537 /* Driver Instance Initialization Configuration */
 538 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 539         {
 540                 /* EDMA3 INSTANCE# 0 */
 541                 {
 542                         /* Resources owned/reserved by region 0 (Configuration for Netra A8 Core)*/
 543                         {
 544                                 /* ownPaRAMSets */
 545                                 /* 31     0     63    32     95    64     127   96 */
 546                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 547                                 /* 159  128     191  160     223  192     255  224 */
 548                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 549                                 /* 287  256     319  288     351  320     383  352 */
 550                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 551                                 /* 415  384     447  416     479  448     511  480 */
 552                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 553
 554                                 /* ownDmaChannels */
 555                                 /* 31     0     63    32 */
 556                                 {EDMA3_OWN_DMA_CHANNELS_0_A8, EDMA3_OWN_DMA_CHANNELS_1_A8},
 557
 558                                 /* ownQdmaChannels */
 559                                 /* 31     0 */
 560                                 {EDMA3_OWN_QDMA_CHANNELS_0_A8},
 561
 562                                 /* ownTccs */
 563                                 /* 31     0     63    32 */
 564                                 {EDMA3_OWN_TCC_0_A8, EDMA3_OWN_TCC_1_A8},
 565
 566                                 /* resvdPaRAMSets */
 567                                 /* 31     0     63    32     95    64     127   96 */
 568                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 569                                 /* 159  128     191  160     223  192     255  224 */
 570                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 571                                 /* 287  256     319  288     351  320     383  352 */
 572                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 573                                 /* 415  384     447  416     479  448     511  480 */
 574                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 575
 576                                 /* resvdDmaChannels */
 577                                 /* 31     0     63    32 */
 578                                 {EDMA3_RESERVED_DMA_CHANNELS_0_A8, EDMA3_RESERVED_DMA_CHANNELS_1_A8},
 579
 580                                 /* resvdQdmaChannels */
 581                                 /* 31     0 */
 582                                 {EDMA3_RESERVED_QDMA_CHANNELS_0_A8},
 583
 584                                 /* resvdTccs */
 585                                 /* 31     0     63    32 */
 586                                 {EDMA3_RESERVED_TCC_0_A8, EDMA3_RESERVED_TCC_1_A8},
 587                         },
 588
 589                 /* Resources owned/reserved by region 1 (Configuration for Netra DSP Core)*/
 590                     {
 591                         /* ownPaRAMSets */
 592                         /* 31     0     63    32     95    64     127   96 */
 593                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 594                                 /* 159  128     191  160     223  192     255  224 */
 595                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 596                                 /* 287  256     319  288     351  320     383  352 */
 597                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 598                                 /* 415  384     447  416     479  448     511  480 */
 599                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 600
 601                         /* ownDmaChannels */
 602                         /* 31     0     63    32 */
 603                         {EDMA3_OWN_DMA_CHANNELS_0_DSP, EDMA3_OWN_DMA_CHANNELS_1_DSP},
 604
 605                         /* ownQdmaChannels */
 606                         /* 31     0 */
 607                         {EDMA3_OWN_QDMA_CHANNELS_0_DSP},
 608
 609                         /* ownTccs */
 610                         /* 31     0     63    32 */
 611                         {EDMA3_OWN_TCC_0_DSP, EDMA3_OWN_TCC_1_DSP},
 612
 613                         /* resvdPaRAMSets */
 614                         /* 31     0     63    32     95    64     127   96 */
 615                         {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 616                         /* 159  128     191  160     223  192     255  224 */
 617                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 618                         /* 287  256     319  288     351  320     383  352 */
 619                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 620                         /* 415  384     447  416     479  448     511  480 */
 621                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 622
 623                         /* resvdDmaChannels */
 624                                 /* 31     0     63    32 */
 625                                 {EDMA3_RESERVED_DMA_CHANNELS_0_DSP, EDMA3_RESERVED_DMA_CHANNELS_1_DSP},
 626
 627                         /* resvdQdmaChannels */
 628                         /* 31     0 */
 629                         {EDMA3_RESERVED_QDMA_CHANNELS_0_DSP},
 630
 631                         /* resvdTccs */
 632                                 /* 31     0     63    32 */
 633                                 {EDMA3_RESERVED_TCC_0_DSP, EDMA3_RESERVED_TCC_1_DSP},
 634                     },
 635
 636                 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/
 637                         {
 638                                 /* ownPaRAMSets */
 639                                 /* 31     0     63    32     95    64     127   96 */
 640                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 641                                 /* 159  128     191  160     223  192     255  224 */
 642                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 643                                 /* 287  256     319  288     351  320     383  352 */
 644                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 645                                 /* 415  384     447  416     479  448     511  480 */
 646                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 647
 648                                 /* ownDmaChannels */
 649                                 /* 31     0     63    32 */
 650                                 {0x00000000u, 0x00000000u},
 651
 652                                 /* ownQdmaChannels */
 653                                 /* 31     0 */
 654                                 {0x00000000u},
 655
 656                                 /* ownTccs */
 657                                 /* 31     0     63    32 */
 658                                 {0x00000000u, 0x00000000u},
 659
 660                                 /* resvdPaRAMSets */
 661                                 /* 31     0     63    32     95    64     127   96 */
 662                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 663                                 /* 159  128     191  160     223  192     255  224 */
 664                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 665                                 /* 287  256     319  288     351  320     383  352 */
 666                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 667                                 /* 415  384     447  416     479  448     511  480 */
 668                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 669
 670                                 /* resvdDmaChannels */
 671                                 /* 31     0     63    32 */
 672                                 {0x00000000u, 0x00000000u},
 673
 674                                 /* resvdQdmaChannels */
 675                                 /* 31     0 */
 676                                 {0x00000000u},
 677
 678                                 /* resvdTccs */
 679                                 /* 31     0     63    32 */
 680                                 {0x00000000u, 0x00000000u},
 681                         },
 682
 683                 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
 684                         {
 685                                 /* ownPaRAMSets */
 686                                 /* 31     0     63    32     95    64     127   96 */
 687                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 688                                 /* 159  128     191  160     223  192     255  224 */
 689                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 690                                 /* 287  256     319  288     351  320     383  352 */
 691                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 692                                 /* 415  384     447  416     479  448     511  480 */
 693                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 694
 695                                 /* ownDmaChannels */
 696                                 /* 31     0     63    32 */
 697                                 {0x00000000u, 0x00000000u},
 698
 699                                 /* ownQdmaChannels */
 700                                 /* 31     0 */
 701                                 {0x00000000u},
 702
 703                                 /* ownTccs */
 704                                 /* 31     0     63    32 */
 705                                 {0x00000000u, 0x00000000u},
 706
 707                                 /* resvdPaRAMSets */
 708                                 /* 31     0     63    32     95    64     127   96 */
 709                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 710                                 /* 159  128     191  160     223  192     255  224 */
 711                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 712                                 /* 287  256     319  288     351  320     383  352 */
 713                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 714                                 /* 415  384     447  416     479  448     511  480 */
 715                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 716
 717                                 /* resvdDmaChannels */
 718                                 /* 31     0     63    32 */
 719                                 {0x00000000u, 0x00000000u},
 720
 721                                 /* resvdQdmaChannels */
 722                                 /* 31     0 */
 723                                 {0x00000000u},
 724
 725                                 /* resvdTccs */
 726                                 /* 31     0     63    32 */
 727                                 {0x00000000u, 0x00000000u},
 728                         },
 729
 730                 /* Resources owned/reserved by region 4 (Configuration for Netra M3VIDEO Core)*/
 731                         {
 732                                 /* ownPaRAMSets */
 733                                 /* 31     0     63    32     95    64     127   96 */
 734                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 735                                 /* 159  128     191  160     223  192     255  224 */
 736                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 737                                 /* 287  256     319  288     351  320     383  352 */
 738                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 739                                 /* 415  384     447  416     479  448     511  480 */
 740                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 741
 742                                 /* ownDmaChannels */
 743                                 /* 31     0     63    32 */
 744                                 {EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO, EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO},
 745
 746                                 /* ownQdmaChannels */
 747                                 /* 31     0 */
 748                                 {EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO},
 749
 750                                 /* ownTccs */
 751                                 /* 31     0     63    32 */
 752                                 {EDMA3_OWN_TCC_0_M3VIDEO, EDMA3_OWN_TCC_0_M3VIDEO},
 753
 754                                 /* resvdPaRAMSets */
 755                                 /* 31     0     63    32     95    64     127   96 */
 756                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 757                                 /* 159  128     191  160     223  192     255  224 */
 758                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 759                                 /* 287  256     319  288     351  320     383  352 */
 760                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 761                                 /* 415  384     447  416     479  448     511  480 */
 762                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 763
 764                                 /* resvdDmaChannels */
 765                                 /* 31     0     63    32 */
 766                                 {EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO, EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO},
 767
 768                                 /* resvdQdmaChannels */
 769                                 /* 31     0 */
 770                                 {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO},
 771
 772                                 /* resvdTccs */
 773                                 /* 31     0     63    32 */
 774                                 {EDMA3_RESERVED_TCC_0_M3VIDEO, EDMA3_RESERVED_TCC_1_M3VIDEO},
 775                         },
 776
 777                 /* Resources owned/reserved by region 5 (Configuration for Netra M3VPSS Core)*/
 778                         {
 779                                 /* ownPaRAMSets */
 780                                 /* 31     0     63    32     95    64     127   96 */
 781                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 782                                 /* 159  128     191  160     223  192     255  224 */
 783                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 784                                 /* 287  256     319  288     351  320     383  352 */
 785                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 786                                 /* 415  384     447  416     479  448     511  480 */
 787                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 788
 789                                 /* ownDmaChannels */
 790                                 /* 31     0     63    32 */
 791                                 {EDMA3_OWN_DMA_CHANNELS_0_M3VPSS, EDMA3_OWN_DMA_CHANNELS_1_M3VPSS},
 792
 793                                 /* ownQdmaChannels */
 794                                 /* 31     0 */
 795                                 {EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS},
 796
 797                                 /* ownTccs */
 798                                 /* 31     0     63    32 */
 799                                 {EDMA3_OWN_TCC_0_M3VPSS, EDMA3_OWN_TCC_1_M3VPSS},
 800
 801                                 /* resvdPaRAMSets */
 802                                 /* 31     0     63    32     95    64     127   96 */
 803                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 804                                 /* 159  128     191  160     223  192     255  224 */
 805                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 806                                 /* 287  256     319  288     351  320     383  352 */
 807                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 808                                 /* 415  384     447  416     479  448     511  480 */
 809                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 810
 811                                 /* resvdDmaChannels */
 812                                 /* 31     0     63    32 */
 813                                 {EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS, EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS},
 814
 815                                 /* resvdQdmaChannels */
 816                                 /* 31     0 */
 817                                 {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS},
 818
 819                                 /* resvdTccs */
 820                                 /* 31     0     63    32 */
 821                                 {EDMA3_RESERVED_TCC_0_M3VPSS, EDMA3_RESERVED_TCC_1_M3VPSS},
 822                         },
 823
 824                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
 825                         {
 826                                 /* ownPaRAMSets */
 827                                 /* 31     0     63    32     95    64     127   96 */
 828                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 829                                 /* 159  128     191  160     223  192     255  224 */
 830                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 831                                 /* 287  256     319  288     351  320     383  352 */
 832                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 833                                 /* 415  384     447  416     479  448     511  480 */
 834                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 835
 836                                 /* ownDmaChannels */
 837                                 /* 31     0     63    32 */
 838                                 {0x00000000u, 0x00000000u},
 839
 840                                 /* ownQdmaChannels */
 841                                 /* 31     0 */
 842                                 {0x00000000u},
 843
 844                                 /* ownTccs */
 845                                 /* 31     0     63    32 */
 846                                 {0x00000000u, 0x00000000u},
 847
 848                                 /* resvdPaRAMSets */
 849                                 /* 31     0     63    32     95    64     127   96 */
 850                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 851                                 /* 159  128     191  160     223  192     255  224 */
 852                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 853                                 /* 287  256     319  288     351  320     383  352 */
 854                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 855                                 /* 415  384     447  416     479  448     511  480 */
 856                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 857
 858                                 /* resvdDmaChannels */
 859                                 /* 31     0     63    32 */
 860                                 {0x00000000u, 0x00000000u},
 861
 862                                 /* resvdQdmaChannels */
 863                                 /* 31     0 */
 864                                 {0x00000000u},
 865
 866                                 /* resvdTccs */
 867                                 /* 31     0     63    32 */
 868                                 {0x00000000u, 0x00000000u},
 869                         },
 870
 871                 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
 872                         {
 873                                 /* ownPaRAMSets */
 874                                 /* 31     0     63    32     95    64     127   96 */
 875                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 876                                 /* 159  128     191  160     223  192     255  224 */
 877                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 878                                 /* 287  256     319  288     351  320     383  352 */
 879                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 880                                 /* 415  384     447  416     479  448     511  480 */
 881                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 882
 883                                 /* ownDmaChannels */
 884                                 /* 31     0     63    32 */
 885                                 {0x00000000u, 0x00000000u},
 886
 887                                 /* ownQdmaChannels */
 888                                 /* 31     0 */
 889                                 {0x00000000u},
 890
 891                                 /* ownTccs */
 892                                 /* 31     0     63    32 */
 893                                 {0x00000000u, 0x00000000u},
 894
 895                                 /* resvdPaRAMSets */
 896                                 /* 31     0     63    32     95    64     127   96 */
 897                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 898                                 /* 159  128     191  160     223  192     255  224 */
 899                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 900                                 /* 287  256     319  288     351  320     383  352 */
 901                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 902                                 /* 415  384     447  416     479  448     511  480 */
 903                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 904
 905                                 /* resvdDmaChannels */
 906                                 /* 31     0     63    32 */
 907                                 {0x00000000u, 0x00000000u},
 908
 909                                 /* resvdQdmaChannels */
 910                                 /* 31     0 */
 911                                 {0x00000000u},
 912
 913                                 /* resvdTccs */
 914                                 /* 31     0     63    32 */
 915                                 {0x00000000u, 0x00000000u},
 916                         },
 917             },
 918         };
 919
 920
 921
 922 /* End of File */
 923
 924