Merge pull request #20 in PROCESSOR-SDK/edma3_lld from misrac_fix_PRSDK-3354 to master
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / src / edma3_drv_basic.c
1 /*
2  * edma3_drv_basic.c
3  *
4  * EDMA3 Driver Basic Interface Implementation. This file contains
5  * beginner-level EDMA3 Driver APIs which are required to:
6  * a) Request/free a DMA, QDMA and Link channel.
7  * b) Program various fields in the PaRAM Set like source/destination
8  * parameters, transfer parameters etc.
9  * c) Enable/disable a transfer.
10  * These APIs are provided to program a DMA/QDMA channel for simple use-cases
11  * and don't expose all the features of EDMA3 hardware. Users who want to go
12  * beyond this and have complete control on the EDMA3 hardware are advised
13  * to refer edma3_drv_adv.c source file.
14  *
15  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
16  *
17  *
18  *  Redistribution and use in source and binary forms, with or without
19  *  modification, are permitted provided that the following conditions
20  *  are met:
21  *
22  *    Redistributions of source code must retain the above copyright
23  *    notice, this list of conditions and the following disclaimer.
24  *
25  *    Redistributions in binary form must reproduce the above copyright
26  *    notice, this list of conditions and the following disclaimer in the
27  *    documentation and/or other materials provided with the
28  *    distribution.
29  *
30  *    Neither the name of Texas Instruments Incorporated nor the names of
31  *    its contributors may be used to endorse or promote products derived
32  *    from this software without specific prior written permission.
33  *
34  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45  *
46 */
48 /* EDMa3 Driver Internal Header Files */
49 #include <ti/sdo/edma3/drv/src/edma3.h>
50 /* Resource Manager Internal Header Files */
51 #include <ti/sdo/edma3/rm/src/edma3resmgr.h>
53 /* Instrumentation Header File */
54 #ifdef EDMA3_INSTRUMENTATION_ENABLED
55 #include <ti/sdo/edma3/rm/src/edma3_log.h>
56 #endif
58 /* For assert() */
59 /**
60  * Define NDEBUG to ignore assert().
61  * NDEBUG should be defined before including assert.h header file.
62  */
63 #include <assert.h>
66 /* Externel Variables */
67 /*---------------------------------------------------------------------------*/
68 /**
69  * Maximum Resource Manager Instances supported by the EDMA3 Package.
70  */
71 extern const uint32_t EDMA3_MAX_RM_INSTANCES;
74 /**
75  * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
76  *
77  * Typically one RM object will cater to one EDMA3 HW controller
78  * and will have all the global config information.
79  */
80 extern EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
83 /**
84  * \brief Region Specific Configuration structure for
85  * EDMA3 controller, to provide region specific Information.
86  *
87  * This configuration info can also be provided by the user at run-time,
88  * while calling EDMA3_RM_open (). If not provided at run-time,
89  * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
90  * for the specified platform.
91  */
92 #ifdef BUILD_C6XDSP
93 extern far EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
94 #else
95 extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
96 #endif
98 /**
99  * Handles of EDMA3 Resource Manager Instances.
100  *
101  * Used to maintain information of the EDMA3 RM Instances
102  * for each HW controller.
103  * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per
104  * EDMA3 HW.
105  */
106 #ifdef BUILD_C6XDSP
107 extern far EDMA3_RM_Instance *ptrRMIArray;
108 #else
109 extern EDMA3_RM_Instance *ptrRMIArray;
110 #endif
112 /** Local MemSet function */
113 extern void edma3MemZero(void *dst, uint32_t len);
114 /** Local MemCpy function */
115 extern void edma3MemCpy(void *dst, const void *src, uint32_t len);
117 /**
118  * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
119  *
120  * Typically one object will cater to one EDMA3 HW controller
121  * and will have all regions' (ARM, DSP etc) specific config information.
122  */
123 extern EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES];
126 /**
127  * Handles of EDMA3 Driver Instances.
128  *
129  * Used to maintain information of the EDMA3 Driver Instances for
130  * each region, for each HW controller.
131  * There could be as many Driver Instances as there are shadow
132  * regions. Multiple EDMA3 Driver instances on the same shadow
133  * region are NOT allowed.
134  */
135 extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
138 /**
139  * \brief Resources bound to a Channel
140  *
141  * When a request for a channel is made, the resources PaRAM Set and TCC
142  * get bound to that channel. This information is needed internally by the
143  * driver when a request is made to free the channel (Since it is the
144  * responsibility of the driver to free up the channel-associated resources
145  * from the Resource Manager layer).
146  */
147 extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
149 /** Max of DMA Channels */
150 extern uint32_t edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
151 /** Min of Link Channels */
152 extern uint32_t edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
153 /** Max of Link Channels */
154 extern uint32_t edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
155 /** Min of QDMA Channels */
156 extern uint32_t edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
157 /** Max of QDMA Channels */
158 extern uint32_t edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
159 /** Max of Logical Channels */
160 extern uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
162 /* Local functions prototypes */
163 /*---------------------------------------------------------------------------*/
164 /** Remove various mappings and do cleanup for DMA/QDMA channels */
165 static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
166                                  uint32_t channelId);
168 /** @brief Global Variable which describes the EDMA3 LLD Version Information */
169 const char   edma3LldVersionStr[] = EDMA3_LLD_DRV_VERSION_STR ":" __DATE__  ":" __TIME__;
170 /*---------------------------------------------------------------------------*/
172 EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
173                                     uint32_t *pLCh,
174                                     uint32_t *pTcc,
175                                     EDMA3_RM_EventQueue evtQueue,
176                                     EDMA3_RM_TccCallback tccCb,
177                                     void *cbData)
178     {
179     EDMA3_RM_ResDesc resObj;
180     EDMA3_RM_ResDesc channelObj;
181     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
182     EDMA3_DRV_Instance *drvInst = NULL;
183     EDMA3_DRV_Object *drvObject = NULL;
184     uint32_t mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP;
185     int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
186     EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
187     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
188     int32_t mappedPaRAMId;
189         uint32_t edma3Id;
190         uint32_t freeDmaQdmaChannel = FALSE;
191         uint32_t mapXbarEvtToChanFlag = FALSE;
192         uint32_t xBarEvtBeforeMap = 0;
194 #ifdef EDMA3_INSTRUMENTATION_ENABLED
195     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
196                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
197                 EDMA3_DVT_dCOUNTER,
198                 EDMA3_DVT_dNONE,
199                 EDMA3_DVT_dNONE));
200 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
203         /* If parameter checking is enabled... */
204 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
205     if ((pLCh == NULL) || (hEdma == NULL))
206         {
207         result = EDMA3_DRV_E_INVALID_PARAM;
208         }
209 #endif
211         if (EDMA3_DRV_SOK == result)
212         {
213         drvInst = (EDMA3_DRV_Instance *)hEdma;
214         drvObject = drvInst->pDrvObjectHandle;
216         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
217             {
218             result = EDMA3_DRV_E_INVALID_PARAM;
219             }
220                 }
221     if (EDMA3_DRV_SOK == result)
222         {
223             if ( drvInst->mapXbarToChan != NULL)
224                 {
225                     xBarEvtBeforeMap = *pLCh;
226                     edma3Id = drvObject->phyCtrllerInstId;
227                     if ((xBarEvtBeforeMap > edma3_dma_ch_max_val [edma3Id]) &&
228                         (xBarEvtBeforeMap < EDMA3_DRV_DMA_CHANNEL_ANY) && 
229                         ((*pLCh) == (*pTcc)))
230                         {
231                         result = drvInst->mapXbarToChan(xBarEvtBeforeMap, 
232                                     pLCh, 
233                                     &drvInst->drvXbarToEvtMapConfig);
234                         if (EDMA3_DRV_SOK == result)
235                             {
236                             *pTcc = *pLCh;
237                             mapXbarEvtToChanFlag = TRUE;
238                             }
239                 }
240             }
241         }
243         if (EDMA3_DRV_SOK == result)
244         {
245         edma3Id = drvObject->phyCtrllerInstId;
246         globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
247         
248         /* Identify the request type and validate the appropriate arguments.
249                  * Starting in the order of PaRAM Set availability,
250                  * check for a specific DMA channel request first.
251                  */
252                 if ((*pLCh) <= edma3_dma_ch_max_val [edma3Id])
253                         {
254                         /* A 'Specific' DMA channel is requested */
255                         chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
256                         /* Fill the resObj structure as well */
257                         resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
258                         resObj.resId = *pLCh;
260                         /* Check the TCC and Event Queue number */
261             if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
262                                 || (pTcc == NULL))
263                 {
264                 result = EDMA3_DRV_E_INVALID_PARAM;
265                 }
266                         }
268                 if ((*pLCh) == EDMA3_DRV_DMA_CHANNEL_ANY)
269                         {
270                         /* 'Any' DMA channel is requested */
271                         chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
272                         resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
273                         resObj.resId = EDMA3_RM_RES_ANY;
275                         /* Check the TCC and Event Queue number */
276             if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
277                                 || (pTcc == NULL))
278                 {
279                 result = EDMA3_DRV_E_INVALID_PARAM;
280                 }
281                         }
283                 if (((*pLCh) >= edma3_link_ch_min_val[edma3Id]) &&
284                                 ((*pLCh) <= edma3_link_ch_max_val[edma3Id]))
285                         {
286                         /* A 'Specific' Link channel is requested, TCC may or may not be
287                          * required.
288                          */
289                         /* Save the PaRAM Id for future use */
290                         paRAMId = *pLCh;
292                         if (pTcc != NULL)
293                                 {
294                                 if (*pTcc < drvObject->gblCfgParams.numTccs)
295                                         {
296                                         /* Argument passed as *pTcc is a valid TCC number */
297                                         chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
298                                 resObj.type = EDMA3_RM_RES_PARAM_SET;
299                                         }
300                                 else
301                                         {
302                                         /* Argument passed as *pTcc is Invalid TCC number */
303                                         result = EDMA3_DRV_E_INVALID_PARAM;
304                                         }
305                                 }
306                         else
307                                 {
308                                 /* pTcc is NULL, only Link Channel required */
309                                 chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
310                                 resObj.type = EDMA3_RM_RES_PARAM_SET;
311                                 }
312                         }
314                 if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)
315                         {
316                         /* 'Any' Link channel is requested, TCC is not required */
317                         chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
318                         resObj.type = EDMA3_RM_RES_PARAM_SET;
319                         }
321                 if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL_WITH_TCC)
322                         {
323                         if (pTcc != NULL)
324                                 {
325                                 /* 'Any' Link channel is requested, TCC is required */
326                                 if (*pTcc < drvObject->gblCfgParams.numTccs)
327                                         {
328                                         /* Argument passed as *pTcc is a valid TCC number */
329                                         chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
330                                         resObj.type = EDMA3_RM_RES_PARAM_SET;
331                                         }
332                                 else
333                                         {
334                                         /* Argument passed as *pTcc is Invalid TCC number */
335                                         result = EDMA3_DRV_E_INVALID_PARAM;
336                                         }
337                                 }
338                         else
339                                 {
340                                 /* pTcc is NULL */
341                                 result = EDMA3_DRV_E_INVALID_PARAM;
342                                 }
343                         }
345                 if (((*pLCh) >= EDMA3_DRV_QDMA_CHANNEL_0) &&
346                                 ((*pLCh) <= EDMA3_DRV_QDMA_CHANNEL_7))
347                         {
348                         /* A 'Specific' QDMA channel is requested */
349                         chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
350                         resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
351                         resObj.resId = *pLCh - EDMA3_DRV_QDMA_CHANNEL_0;
353                         /* Check the TCC and Event Queue number */
354             if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
355                                 || (pTcc == NULL))
356                 {
357                 result = EDMA3_DRV_E_INVALID_PARAM;
358                 }
359                         }
361                 if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY)
362                         {
363                         /* 'Any' QDMA channel is requested */
364                         chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
365                         resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
366                         resObj.resId = EDMA3_RM_RES_ANY;
368                         /* Check the TCC and Event Queue number */
369             if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
370                                 || (pTcc == NULL))
371                 {
372                 result = EDMA3_DRV_E_INVALID_PARAM;
373                 }
374                         }
376                 if (EDMA3_DRV_CHANNEL_TYPE_NONE == chType)
377                         {
378                         /* Invalid request */
379                         result = EDMA3_DRV_E_INVALID_PARAM;
380                         }
381                 }
383         /* Step 1: Allocate the DMA/QDMA channel first, if required */
384         if (EDMA3_DRV_SOK == result)
385         {
386         switch (chType)
387                 {
388                 case EDMA3_DRV_CHANNEL_TYPE_DMA:
389                                 result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
390                                                                                                 (EDMA3_RM_ResDesc *)&resObj);
391                 if (result == EDMA3_RM_SOK)
392                     {
393                     *pLCh = resObj.resId;
395                     mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
396                     if (mappedPaRAMId != (int32_t)EDMA3_DRV_CH_NO_PARAM_MAP)
397                         {
398                         paRAMId = mappedPaRAMId;
399                         }
401                     if (*pTcc == EDMA3_DRV_TCC_ANY)
402                         {
403                             mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];
404                         if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP)
405                             {
406                             mappedTcc = EDMA3_RM_RES_ANY;
407                             }
408                         }
409                     else
410                         {
411                         mappedTcc = *pTcc;
412                         }
414                     /* Save the Resource Type/ID for TCC registeration */
415                     channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
416                                         channelObj.resId = *pLCh;
418                                         /* Free DMA channel in case the function fails in future */
419                                         freeDmaQdmaChannel = TRUE;
420                     }
421                 else
422                     {
423                     result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;
424                     }
426                                 break;
428                 case EDMA3_DRV_CHANNEL_TYPE_QDMA:
429                                 result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
430                                                                                                 (EDMA3_RM_ResDesc *)&resObj);
431                 if (result == EDMA3_DRV_SOK)
432                     {
433                     (*pLCh) = resObj.resId + edma3_qdma_ch_min_val[edma3Id];
435                     if (*pTcc == EDMA3_DRV_TCC_ANY)
436                         {
437                         mappedTcc = EDMA3_RM_RES_ANY;
438                         }
439                     else
440                         {
441                         mappedTcc = *pTcc;
442                         }
444                     /* Save the Resource Type/ID for TCC registeration */
445                     channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
446                                         channelObj.resId = resObj.resId;
448                                         /* Free DMA channel in case the function fails in future */
449                                         freeDmaQdmaChannel = TRUE;
450                     }
451                 else
452                     {
453                     result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
454                     }
455                                 break;
457                         default:
458                                 break;
459                 }
460                 }
462         /* Step 2: Allocate the PaRAM Set */
463         if (EDMA3_DRV_SOK == result)
464         {
465         resObj.type = EDMA3_RM_RES_PARAM_SET;
466         resObj.resId = (uint32_t)paRAMId;
467         result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
468                 }
470         if (EDMA3_DRV_SOK == result)
471         {
472         paRAMId = (int32_t)resObj.resId;
474         if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
475                 {
476                 /* Link channel number should be same as the PaRAM Set */
477             *pLCh = resObj.resId;
478                         edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
479             edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
480                 }
482         if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK_TCC)
483             {
484                 /* Link channel number should be same as the PaRAM Set */
485             *pLCh = resObj.resId;
486                         edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
487             edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
489                         /* save the tcc now */
490                         edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
492             /* Set TCC in ParamSet.OPT field */
493             globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
494             globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
495             }
496                 }
497         else
498                 {
499                 /* PaRAM allocation failed, free the previously allocated DMA/QDMA
500                  * channel, if required
501                  */
502                 if (((chType == EDMA3_DRV_CHANNEL_TYPE_DMA)
503                         || (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)) &&
504                         (TRUE == freeDmaQdmaChannel))
505                         {
506                 EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
507                         }
508                 }
510         /* Step 3: Allocate TCC only for DMA/QDMA channels */
511         if ((EDMA3_DRV_SOK == result) &&
512                 ((chType == EDMA3_DRV_CHANNEL_TYPE_DMA) || (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)))
513         {
514         resObj.type = EDMA3_RM_RES_TCC;
515         resObj.resId = mappedTcc;
516         result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
518                 if (EDMA3_DRV_SOK == result)
519                 {
520                 *pTcc = resObj.resId;
522                         /* Save TCC and PaRAM set */
523                         edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
524                         edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
526                         switch (chType)
527                                 {
528                                 case EDMA3_DRV_CHANNEL_TYPE_DMA:
529                                         {
530                                         /* Step 4: Register the callback function, if required */
531                                         if (NULL != tccCb)
532                                                 {
533                             result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
534                                                                             (EDMA3_RM_ResDesc *)&channelObj,
535                                                                             *pTcc, tccCb, cbData);
536                                                 }
537                     if (result != EDMA3_DRV_SOK)
538                         {
539                         EDMA3_DRV_freeChannel (hEdma, *pLCh);
540                         result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
541                         }
542                                         else
543                                                 {
544 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
545                                                 uint32_t intState = 0;
546                         edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
547                                                                                         &intState);
548                         /* Step 5: Associate DMA Channel to Event Queue */
549                         globalRegs->DMAQNUM[(*pLCh) >> 3U] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
550                         globalRegs->DMAQNUM[(*pLCh) >> 3U] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh), evtQueue);
552                         edma3OsProtectExit(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
553                                                                                         intState);
554 #endif
556                         /* Step 6: Map PaRAM Set to DMA Channel */
557                                                 if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
558                                 {
559                                             globalRegs->DCHMAP[*pLCh] &= EDMA3_DRV_DCH_PARAM_CLR_MASK;
560                                             globalRegs->DCHMAP[*pLCh] |= EDMA3_DRV_DCH_PARAM_SET_MASK((uint32_t)paRAMId);
561                             }
563                         /* Step 7: Set TCC in ParamSet.OPT field */
564                         globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
565                         globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
567                                                 edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
568                                                 }
569                                         }
570                                         break;
572                                 case EDMA3_DRV_CHANNEL_TYPE_QDMA:
573                                         {
574                                         uint32_t qdmaChannel = channelObj.resId;
576                                         /* Step 4: Register the callback function, if required */
577                                         if (NULL != tccCb)
578                                                 {
579                             result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
580                                                                             (EDMA3_RM_ResDesc *)&channelObj,
581                                                                             *pTcc, tccCb, cbData);
582                                                 }
583                     if (result != EDMA3_DRV_SOK)
584                         {
585                         EDMA3_DRV_freeChannel (hEdma, *pLCh);
586                         result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
587                         }
588                                         else
589                                                 {
590 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
591                                                 uint32_t intState = 0;
592                         edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
593                                                                                         &intState);
594                         /* Step 5: Associate QDMA Channel to Event Queue */
595                         globalRegs->QDMAQNUM &= EDMA3_DRV_QDMAQNUM_CLR_MASK(qdmaChannel);
596                         globalRegs->QDMAQNUM |= EDMA3_DRV_QDMAQNUM_SET_MASK(qdmaChannel, evtQueue);
598                         edma3OsProtectExit(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
599                                                                                         intState);
600 #endif
602                         /* Step 6: Map PaRAM Set to DMA Channel and set the Default Trigger Word */
603                                         globalRegs->QCHMAP[qdmaChannel] &= EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK;
604                                         globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_PARAM_SET_MASK((uint32_t)paRAMId);
605                                         globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT);
607                         /* Step 7: Set TCC in ParamSet.OPT field */
608                         globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
609                         globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
611                                                 edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
613                                                 /* Step 8: Enable the QDMA Channel */
614                                                 drvInst->shadowRegs->QEESR = 1U << qdmaChannel;
615                                                 }
616                                         }
617                                         break;
618                                 default:
619                                         break;
620                                 }
621                         }
622                 else
623                         {
624                         /* TCC allocation failed, free the PaRAM Set, */
625             resObj.type = EDMA3_RM_RES_PARAM_SET;
626             resObj.resId = (uint32_t)paRAMId;
627             EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
629                         /* And free the DMA/QDMA channel */
630                         EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
632                         result = EDMA3_DRV_E_TCC_UNAVAIL;
633                         }
634                 }
636         if (EDMA3_DRV_SOK == result)
637         {
638                 if ((drvInst->configScrMapXbarToEvt != NULL) && 
639                         (mapXbarEvtToChanFlag == TRUE))
640                         {
641                         drvInst->configScrMapXbarToEvt(xBarEvtBeforeMap, *pLCh);
642                         }
643         }
645 #ifdef EDMA3_INSTRUMENTATION_ENABLED
646     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
647                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
648                 EDMA3_DVT_dCOUNTER,
649                 EDMA3_DVT_dNONE,
650                 EDMA3_DVT_dNONE));
651 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
653     return result;
656 EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
657                                                 uint32_t channelId)
658     {
659     EDMA3_RM_ResDesc resObj;
660     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
661     EDMA3_DRV_Instance *drvInst = NULL;
662     EDMA3_DRV_Object *drvObject = NULL;
663     int32_t paRAMId;
664     uint32_t tcc;
665     EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
666     uint32_t edma3Id;
668 #ifdef EDMA3_INSTRUMENTATION_ENABLED
669     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
670                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
671                 EDMA3_DVT_dCOUNTER,
672                 EDMA3_DVT_dNONE,
673                 EDMA3_DVT_dNONE));
674 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
676         /* If parameter checking is enabled... */
677 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
678     if (hEdma == NULL)
679         {
680         result = EDMA3_DRV_E_INVALID_PARAM;
681         }
682 #endif
684     if (EDMA3_DRV_SOK == result)
685         {
686         drvInst = (EDMA3_DRV_Instance *)hEdma;
687         drvObject = drvInst->pDrvObjectHandle;
689         if (drvObject == NULL)
690             {
691             result = EDMA3_DRV_E_INVALID_PARAM;
692             }
693                 else
694                         {
695                         edma3Id = drvObject->phyCtrllerInstId;
696                         }
697         }
699     if (EDMA3_DRV_SOK == result)
700         {
701         /* Check the channel type */
702         if (channelId <= edma3_dma_ch_max_val [edma3Id])
703             {
704             /* DMA Channel */
705             chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
706             }
708         if ((channelId >= edma3_link_ch_min_val[edma3Id])
709                                 && (channelId <= edma3_link_ch_max_val[edma3Id]))
710             {
711             /* LINK Channel */
712             chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
713             }
715         if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
716                                 && (channelId <= edma3_qdma_ch_max_val[edma3Id]))
717             {
718             /* QDMA Channel */
719             chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
720             }
722         if (chType == EDMA3_DRV_CHANNEL_TYPE_NONE)
723             {
724             result = EDMA3_DRV_E_INVALID_PARAM;
725             }
726         }
729     if (EDMA3_DRV_SOK == result)
730     {
731         if(channelId < EDMA3_MAX_LOGICAL_CH)
732         {
733             if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
734                 {
735                 /* LINK Channel */
736                 resObj.type = EDMA3_RM_RES_PARAM_SET;
738                 /* Get the PaRAM id from the book-keeping info. */
739                 resObj.resId = (uint32_t)(edma3DrvChBoundRes[edma3Id][channelId].paRAMId);
741                 result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
742                                             (EDMA3_RM_ResDesc *)&resObj);
744                 if (EDMA3_DRV_SOK == result)
745                     {
746                     edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
747                     }
748                 }
749             else
750                 {
751                 /* DMA/QDMA Channel */
752                 paRAMId = edma3DrvChBoundRes[edma3Id][channelId].paRAMId;
753                 tcc = edma3DrvChBoundRes[edma3Id][channelId].tcc;
755                 /* Check the paRAMId and tcc values first */
756                 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
757                     {
758                     result = EDMA3_DRV_E_INVALID_PARAM;
759                     }
761                 if (tcc >= drvObject->gblCfgParams.numTccs)
762                     {
763                     result = EDMA3_DRV_E_INVALID_PARAM;
764                     }
766                 if (EDMA3_DRV_SOK == result)
767                     {
768                     /* Disable the transfer and remove various mappings. */
769                     result = edma3RemoveMapping(hEdma, channelId);
770                     }
772                 if (EDMA3_DRV_SOK == result)
773                     {
774                     /* Now Free the PARAM set and TCC */
775                     resObj.type = EDMA3_RM_RES_PARAM_SET;
776                     resObj.resId = (uint32_t)paRAMId;
777                     result = EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
779                     if (EDMA3_DRV_SOK == result)
780                         {
781                         /* PaRAM Set Freed */
782                         edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
784                         /* Free the TCC */
785                         resObj.type = EDMA3_RM_RES_TCC;
786                         resObj.resId = tcc;
787                         result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
788                                                     (EDMA3_RM_ResDesc *)&resObj);
789                         }
791                     if (EDMA3_DRV_SOK == result)
792                         {
793                         /* TCC Freed. */
794                         edma3DrvChBoundRes[edma3Id][channelId].tcc = EDMA3_MAX_TCC;
796                         /* Now free the DMA/QDMA Channel in the end. */
797                         if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)
798                             {
799                             resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
800                             resObj.resId = (channelId - edma3_qdma_ch_min_val[edma3Id]);
801                             result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
802                                                         (EDMA3_RM_ResDesc *)&resObj);
803                             }
804                         else
805                             {
806                             resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
807                             resObj.resId = channelId;
808                             result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
809                                                         (EDMA3_RM_ResDesc *)&resObj);
810                             }
811                         }
812                     }
813                 }
814         }
815     }
817 #ifdef EDMA3_INSTRUMENTATION_ENABLED
818     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
819                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
820                 EDMA3_DVT_dCOUNTER,
821                 EDMA3_DVT_dNONE,
822                 EDMA3_DVT_dNONE));
823 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
825     return result;
826     }
828 EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
829                                                 uint32_t channelId)
831     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
832     EDMA3_DRV_Instance *drvInst = NULL;
833     EDMA3_DRV_Object *drvObject = NULL;
834     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
835     uint32_t count;
836     uint32_t value = 0;
837         uint32_t edma3Id;
839 #ifdef EDMA3_INSTRUMENTATION_ENABLED
840     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
841                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
842                 EDMA3_DVT_dCOUNTER,
843                 EDMA3_DVT_dNONE,
844                 EDMA3_DVT_dNONE));
845 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
847         /* If parameter checking is enabled... */
848 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
849     if (hEdma == NULL)
850         {
851         result = EDMA3_DRV_E_INVALID_PARAM;
852         }
853 #endif
855         /* Check if the parameters are OK. */
856         if (EDMA3_DRV_SOK == result)
857         {
858         drvInst = (EDMA3_DRV_Instance *)hEdma;
859         drvObject = drvInst->pDrvObjectHandle;
861         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
862             {
863             result = EDMA3_DRV_E_INVALID_PARAM;
864             }
865         else
866             {
867             edma3Id = drvObject->phyCtrllerInstId;
869                         /* If parameter checking is enabled... */
870 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
871             if (channelId > edma3_dma_ch_max_val [edma3Id])
872                 {
873                 result = EDMA3_DRV_E_INVALID_PARAM;
874                 }
875 #endif
877                         /* Check if the parameters are OK. */
878                         if (EDMA3_DRV_SOK == result)
879                 {
880                 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
882 #ifdef EDMA3_DRV_DEBUG
883             EDMA3_DRV_PRINTF("EMR =%l\r\n", globalRegs->EMR);
884 #endif
885                 if(channelId < 32U)
886                     {
887                     /* Disables the DMA channels */
888                     drvInst->shadowRegs->EECR = (1U << channelId);
889                     /* Write to EMCR to clear the corresponding EMR bit */
890                     globalRegs->EMCR = (1U << channelId);
891                     /* Clears the SER */
892                     drvInst->shadowRegs->SECR = (1U << channelId);
893                     }
894                 else
895                     {
896 #ifdef EDMA3_DRV_DEBUG
897                     EDMA3_DRV_PRINTF("EMRH =%l\r\n", globalRegs->EMRH);
898 #endif
899                     /* Disables the DMA channels */
900                     drvInst->shadowRegs->EECRH = (1U << (channelId - 32U));
901                     /* Write to EMCR to clear the corresponding EMR bit */
902                     globalRegs->EMCRH = (1U << (channelId - 32U));
903                     /* Clears the SER */
904                     drvInst->shadowRegs->SECRH = (1U << (channelId - 32U));
905                     }
907                 /* Clear the global CC Error Register */
908                 for (count = 0; count < drvObject->gblCfgParams.numEvtQueue; count++)
909                     {
910                     value |= (((uint32_t)1U) << count);
911                     }
913                 globalRegs->CCERRCLR = (EDMA3_CCRL_CCERR_TCCERR_MASK | value);
914                 }
915             }
916         }
918 #ifdef EDMA3_INSTRUMENTATION_ENABLED
919     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
920                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
921                 EDMA3_DVT_dCOUNTER,
922                 EDMA3_DVT_dNONE,
923                 EDMA3_DVT_dNONE));
924 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
926     return result;
927     }
929 EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
930                     uint32_t lCh,
931                     EDMA3_DRV_OptField optField,
932                     uint32_t newOptFieldVal)
933     {
934     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
935     EDMA3_DRV_Instance *drvInst = NULL;
936     EDMA3_DRV_Object *drvObject = NULL;
937     uint32_t newOptVal = 0;
938     uint32_t oldOptVal = 0;
939     int32_t paRAMId = 0;
940     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
941         uint32_t edma3Id;
943 #ifdef EDMA3_INSTRUMENTATION_ENABLED
944     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
945                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
946                 EDMA3_DVT_dCOUNTER,
947                 EDMA3_DVT_dNONE,
948                 EDMA3_DVT_dNONE));
949 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
951         /* If parameter checking is enabled... */
952 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
953     if ((hEdma == NULL)
954         || (((int32_t)optField < (int32_t)EDMA3_DRV_OPT_FIELD_SAM)
955         || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
956         {
957         result = EDMA3_DRV_E_INVALID_PARAM;
958         }
959 #endif
961         /* Check if the parameters are OK. */
962         if (EDMA3_DRV_SOK == result)
963         {
964         drvInst = (EDMA3_DRV_Instance *)hEdma;
965         drvObject = drvInst->pDrvObjectHandle;
967         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
968             {
969             result = EDMA3_DRV_E_INVALID_PARAM;
970             }
971         else
972             {
973             edma3Id = drvObject->phyCtrllerInstId;
974             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
975                 }
976                 }
978     if (EDMA3_DRV_SOK == result)
979     {
980         /* If parameter checking is enabled... */
981 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
982     if (lCh > edma3_log_ch_max_val [edma3Id])
983         {
984         result = EDMA3_DRV_E_INVALID_PARAM;
985         }
986 #endif
987     }
988         
989         if (EDMA3_DRV_SOK == result)
990         {
991         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
992         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
993             {
994             result = EDMA3_DRV_E_INVALID_PARAM;
995             }
996                 }
998     if (EDMA3_DRV_SOK == result)
999         {
1000         oldOptVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1002         switch (optField)
1003             {
1004             case EDMA3_DRV_OPT_FIELD_SAM :
1005                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_SAM_CLR_MASK)
1006                             |
1007                             (EDMA3_DRV_OPT_SAM_SET_MASK(newOptFieldVal));
1008                 break;
1009             case EDMA3_DRV_OPT_FIELD_DAM :
1010                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_DAM_CLR_MASK)
1011                             |
1012                             (EDMA3_DRV_OPT_DAM_SET_MASK(newOptFieldVal));
1013                 break;
1014             case EDMA3_DRV_OPT_FIELD_SYNCDIM :
1015                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_SYNCDIM_CLR_MASK)
1016                             |
1017                             (EDMA3_DRV_OPT_SYNCDIM_SET_MASK(newOptFieldVal));
1018                 break;
1019             case EDMA3_DRV_OPT_FIELD_STATIC :
1020                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_STATIC_CLR_MASK)
1021                             |
1022                             (EDMA3_DRV_OPT_STATIC_SET_MASK(newOptFieldVal));
1023                 break;
1024             case EDMA3_DRV_OPT_FIELD_FWID :
1025                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_FWID_CLR_MASK)
1026                             |
1027                             (EDMA3_DRV_OPT_FWID_SET_MASK(newOptFieldVal));
1028                 break;
1029             case EDMA3_DRV_OPT_FIELD_TCCMODE :
1030                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCMODE_CLR_MASK)
1031                             |
1032                             (EDMA3_DRV_OPT_TCCMODE_SET_MASK(newOptFieldVal));
1033                 break;
1034             case EDMA3_DRV_OPT_FIELD_TCC :
1035                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
1036                             |
1037                             (EDMA3_DRV_OPT_TCC_SET_MASK(newOptFieldVal));
1038                 break;
1039             case EDMA3_DRV_OPT_FIELD_TCINTEN :
1040                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCINTEN_CLR_MASK)
1041                             |
1042                             (EDMA3_DRV_OPT_TCINTEN_SET_MASK(newOptFieldVal));
1043                 break;
1044             case EDMA3_DRV_OPT_FIELD_ITCINTEN :
1045                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCINTEN_CLR_MASK)
1046                             |
1047                             (EDMA3_DRV_OPT_ITCINTEN_SET_MASK(newOptFieldVal));
1048                 break;
1049             case EDMA3_DRV_OPT_FIELD_TCCHEN :
1050                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCHEN_CLR_MASK)
1051                             |
1052                             (EDMA3_DRV_OPT_TCCHEN_SET_MASK(newOptFieldVal));
1053                 break;
1054             case EDMA3_DRV_OPT_FIELD_ITCCHEN :
1055                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCCHEN_CLR_MASK)
1056                             |
1057                             (EDMA3_DRV_OPT_ITCCHEN_SET_MASK(newOptFieldVal));
1058                 break;
1059             default:
1060                 break;
1061             }
1063         *(&globalRegs->PARAMENTRY[paRAMId].OPT) = newOptVal;
1064         }
1066 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1067     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1068                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1069                 EDMA3_DVT_dCOUNTER,
1070                 EDMA3_DVT_dNONE,
1071                 EDMA3_DVT_dNONE));
1072 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1074     return result;
1075     }
1077 EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
1078                     uint32_t lCh,
1079                     EDMA3_DRV_OptField optField,
1080                     uint32_t *optFieldVal)
1081     {
1082     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1083     EDMA3_DRV_Instance *drvInst = NULL;
1084     EDMA3_DRV_Object *drvObject = NULL;
1085     uint32_t optVal = 0;
1086     int32_t paRAMId = 0;
1087     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1088         uint32_t edma3Id;
1090 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1091     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1092                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1093                 EDMA3_DVT_dCOUNTER,
1094                 EDMA3_DVT_dNONE,
1095                 EDMA3_DVT_dNONE));
1096 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1098         /* If parameter checking is enabled... */
1099 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1100     if (((hEdma == NULL) || (optFieldVal == NULL))
1101         || (((int32_t)optField < (int32_t)EDMA3_DRV_OPT_FIELD_SAM)
1102         || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
1103         {
1104         result = EDMA3_DRV_E_INVALID_PARAM;
1105         }
1106 #endif
1108         /* Check if the parameters are OK. */
1109         if (EDMA3_DRV_SOK == result)
1110         {
1111         drvInst = (EDMA3_DRV_Instance *)hEdma;
1112         drvObject = drvInst->pDrvObjectHandle;
1114         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1115             {
1116             result = EDMA3_DRV_E_INVALID_PARAM;
1117             }
1118         else
1119             {
1120             edma3Id = drvObject->phyCtrllerInstId;
1121             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1122                 }
1123                 }
1125     if (EDMA3_DRV_SOK == result)
1126     {
1127         /* If parameter checking is enabled... */
1128 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1129     if (lCh > edma3_log_ch_max_val [edma3Id])
1130         {
1131         result = EDMA3_DRV_E_INVALID_PARAM;
1132         }
1133 #endif
1134     }
1136         if (EDMA3_DRV_SOK == result)
1137         {
1138         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1139         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1140             {
1141             result = EDMA3_DRV_E_INVALID_PARAM;
1142             }
1143                 }
1145     if (EDMA3_DRV_SOK == result)
1146         {
1147         optVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1149         switch (optField)
1150             {
1151             case EDMA3_DRV_OPT_FIELD_SAM :
1152                 *optFieldVal = EDMA3_DRV_OPT_SAM_GET_MASK(optVal);
1153                 break;
1154             case EDMA3_DRV_OPT_FIELD_DAM :
1155                 *optFieldVal = EDMA3_DRV_OPT_DAM_GET_MASK(optVal);
1156                 break;
1157             case EDMA3_DRV_OPT_FIELD_SYNCDIM :
1158                 *optFieldVal = EDMA3_DRV_OPT_SYNCDIM_GET_MASK(optVal);
1159                 break;
1160             case EDMA3_DRV_OPT_FIELD_STATIC :
1161                 *optFieldVal = EDMA3_DRV_OPT_STATIC_GET_MASK(optVal);
1162                 break;
1163             case EDMA3_DRV_OPT_FIELD_FWID :
1164                 *optFieldVal = EDMA3_DRV_OPT_FWID_GET_MASK(optVal);
1165                 break;
1166             case EDMA3_DRV_OPT_FIELD_TCCMODE :
1167                 *optFieldVal = EDMA3_DRV_OPT_TCCMODE_GET_MASK(optVal);
1168                 break;
1169             case EDMA3_DRV_OPT_FIELD_TCC :
1170                 *optFieldVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
1171                 break;
1172             case EDMA3_DRV_OPT_FIELD_TCINTEN :
1173                 *optFieldVal = EDMA3_DRV_OPT_TCINTEN_GET_MASK(optVal);
1174                 break;
1175             case EDMA3_DRV_OPT_FIELD_ITCINTEN :
1176                 *optFieldVal = EDMA3_DRV_OPT_ITCINTEN_GET_MASK(optVal);
1177                 break;
1178             case EDMA3_DRV_OPT_FIELD_TCCHEN :
1179                 *optFieldVal = EDMA3_DRV_OPT_TCCHEN_GET_MASK(optVal);
1180                 break;
1181             case EDMA3_DRV_OPT_FIELD_ITCCHEN :
1182                 *optFieldVal = EDMA3_DRV_OPT_ITCCHEN_GET_MASK(optVal);
1183                 break;
1184             default:
1185                 break;
1186             }
1187         }
1189 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1190     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1191                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1192                 EDMA3_DVT_dCOUNTER,
1193                 EDMA3_DVT_dNONE,
1194                 EDMA3_DVT_dNONE));
1195 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1197     return result;
1198     }
1200 EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
1201                     uint32_t lCh,
1202                     uint32_t srcAddr,
1203                     EDMA3_DRV_AddrMode addrMode,
1204                     EDMA3_DRV_FifoWidth fifoWidth)
1205     {
1206     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1207     uint32_t opt = 0;
1208     EDMA3_DRV_Instance *drvInst = NULL;
1209     EDMA3_DRV_Object *drvObject = NULL;
1210     int32_t paRAMId = 0;
1211     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1212     uint32_t mappedEvtQ = 0;
1213     uint32_t defaultBurstSize = 0;
1214         uint32_t edma3Id;
1216 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1217     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1218                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1219                 EDMA3_DVT_dCOUNTER,
1220                 EDMA3_DVT_dNONE,
1221                 EDMA3_DVT_dNONE));
1222 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1224         /* If parameter checking is enabled... */
1225 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1226     if ((hEdma == NULL)
1227         || ((((int32_t)addrMode < (int32_t)EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
1228         || (((int32_t)fifoWidth < (int32_t)EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
1229         {
1230         result = EDMA3_DRV_E_INVALID_PARAM;
1231         }
1233     /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
1234     if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1235         && ((srcAddr & 0x1FU) != 0x0))
1236         {
1237         /** Memory is not 32 bytes aligned */
1238         result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
1239         }
1240 #endif
1242         /* Check if the parameters are OK. */
1243         if (EDMA3_DRV_SOK == result)
1244         {
1245         drvInst = (EDMA3_DRV_Instance *)hEdma;
1246         drvObject = drvInst->pDrvObjectHandle;
1248         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1249             {
1250             result =  EDMA3_DRV_E_INVALID_PARAM;
1251             }
1252         else
1253             {
1254             edma3Id = drvObject->phyCtrllerInstId;
1255             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1256                 }
1257                 }
1259         if (EDMA3_DRV_SOK == result)
1260     {
1261         /* If parameter checking is enabled... */
1262 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1263     if (lCh > edma3_log_ch_max_val [edma3Id])
1264         {
1265         result = EDMA3_DRV_E_INVALID_PARAM;
1266         }
1267 #endif
1268     }
1270         if (EDMA3_DRV_SOK == result)
1271         {
1272         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1273         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1274             {
1275             result = EDMA3_DRV_E_INVALID_PARAM;
1276             }
1277                 }
1279         if (EDMA3_DRV_SOK == result)
1280         {
1281         /**
1282           * If request is for FIFO mode, check whether the FIFO size
1283           * is supported by the Transfer Controller which will be used for
1284           * this transfer or not.
1285           */
1286         if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1287             {
1288             if (lCh <= edma3_dma_ch_max_val [edma3Id])
1289                 {
1290                 mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3U])
1291                                 & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
1292                                   >> ((lCh%8U)*4U);
1293                 }
1294             else
1295                 {
1296                 if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
1297                      &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
1298                     {
1299                     mappedEvtQ = ((globalRegs->QDMAQNUM)
1300                                     & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
1301                                    >> (lCh*4U);
1302                     }
1303                 }
1305             /**
1306                * mappedEvtQ contains the event queue and hence the TC which will
1307                * process this transfer request. Check whether this TC supports the
1308                * FIFO size or not.
1309                */
1310             defaultBurstSize = (uint32_t)1U << fifoWidth;
1311             if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
1312                 {
1313                 result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
1314                 }
1315             }
1316         }
1318         if (EDMA3_DRV_SOK == result)
1319         {
1320         /* Set Src Address */
1321         *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
1322                     (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;
1324         opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1326         /* Set SAM */
1327         opt &= EDMA3_DRV_OPT_SAM_CLR_MASK;
1328         opt |= EDMA3_DRV_OPT_SAM_SET_MASK(addrMode);
1329         /* Set FIFO Width */
1330         opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
1331         opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
1333         /* Set the OPT */
1334         *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1335         }
1337 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1338     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1339                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1340                 EDMA3_DVT_dCOUNTER,
1341                 EDMA3_DVT_dNONE,
1342                 EDMA3_DVT_dNONE));
1343 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1345     return result;
1346     }
1348 EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
1349                     uint32_t lCh,
1350                     uint32_t destAddr,
1351                     EDMA3_DRV_AddrMode addrMode,
1352                     EDMA3_DRV_FifoWidth fifoWidth)
1353     {
1354     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1355     uint32_t opt = 0;
1356     EDMA3_DRV_Instance *drvInst = NULL;
1357     EDMA3_DRV_Object *drvObject = NULL;
1358     int32_t paRAMId = 0;
1359     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1360     uint32_t mappedEvtQ = 0;
1361     uint32_t defaultBurstSize = 0;
1362         uint32_t edma3Id;
1364 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1365     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1366                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1367                 EDMA3_DVT_dCOUNTER,
1368                 EDMA3_DVT_dNONE,
1369                 EDMA3_DVT_dNONE));
1370 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1372         /* If parameter checking is enabled... */
1373 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1374     if ((hEdma == NULL)
1375         || ((((int32_t)addrMode < (int32_t)EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
1376         || (((int32_t)fifoWidth < (int32_t)EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
1377         {
1378         result = EDMA3_DRV_E_INVALID_PARAM;
1379         }
1381     /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
1382     if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1383         && ((destAddr & 0x1FU)!=0x0))
1384         {
1385         /** Memory is not 32 bytes aligned */
1386         result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
1387         }
1388 #endif
1390         /* Check if the parameters are OK. */
1391         if (EDMA3_DRV_SOK == result)
1392         {
1393         drvInst = (EDMA3_DRV_Instance *)hEdma;
1394         drvObject = drvInst->pDrvObjectHandle;
1396         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1397             {
1398             result =  EDMA3_DRV_E_INVALID_PARAM;
1399             }
1400         else
1401             {
1402             edma3Id = drvObject->phyCtrllerInstId;
1403             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1404                 }
1405                 }
1407         if (EDMA3_DRV_SOK == result)
1408     {
1409         /* If parameter checking is enabled... */
1410 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1411     if (lCh > edma3_log_ch_max_val [edma3Id])
1412         {
1413         result = EDMA3_DRV_E_INVALID_PARAM;
1414         }
1415 #endif
1416     }
1417         
1418         if (EDMA3_DRV_SOK == result)
1419         {
1420         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1421         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1422             {
1423             result = EDMA3_DRV_E_INVALID_PARAM;
1424             }
1425                 }
1427     if (EDMA3_DRV_SOK == result)
1428         {
1429         /**
1430           * If request is for FIFO mode, check whether the FIFO size
1431           * is supported by the Transfer Controller which will be used for
1432           * this transfer or not.
1433           */
1434         if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1435             {
1436             if (lCh <= edma3_dma_ch_max_val [edma3Id])
1437                 {
1438                 mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3U])
1439                                 & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
1440                                   >> ((lCh%8U)*4U);
1441                 }
1442             else
1443                 {
1444                 if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
1445                      &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
1446                     {
1447                     mappedEvtQ = ((globalRegs->QDMAQNUM)
1448                                     & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
1449                                    >> (lCh*4U);
1450                     }
1451                 }
1453             /**
1454                * mappedEvtQ contains the event queue and hence the TC which will
1455                * process this transfer request. Check whether this TC supports the
1456                * FIFO size or not.
1457                */
1458             defaultBurstSize = (uint32_t)1U << fifoWidth;
1459             if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
1460                 {
1461                 result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
1462                 }
1463             }
1464         }
1466     if (EDMA3_DRV_SOK == result)
1467         {
1468         /* Set the Dest address */
1469         *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
1470                     (uint32_t)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;
1472         opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1474         /* Set DAM */
1475         opt &= EDMA3_DRV_OPT_DAM_CLR_MASK;
1476         opt |= EDMA3_DRV_OPT_DAM_SET_MASK(addrMode);
1477         /* Set FIFO Width */
1478         opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
1479         opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
1481         /* Set the OPT */
1482         *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1483         }
1485 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1486     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1487                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1488                 EDMA3_DVT_dCOUNTER,
1489                 EDMA3_DVT_dNONE,
1490                 EDMA3_DVT_dNONE));
1491 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1493     return result;
1494     }
1496 EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
1497                     uint32_t lCh,
1498                     int32_t srcBIdx, int32_t srcCIdx)
1499     {
1500     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1501     uint32_t srcDstBidx;
1502     uint32_t srcDstCidx;
1503     EDMA3_DRV_Instance *drvInst = NULL;
1504     EDMA3_DRV_Object *drvObject = NULL;
1505     int32_t paRAMId = 0;
1506     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1507         uint32_t edma3Id;
1509 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1510     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1511                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1512                 EDMA3_DVT_dCOUNTER,
1513                 EDMA3_DVT_dNONE,
1514                 EDMA3_DVT_dNONE));
1515 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1517         /* If parameter checking is enabled... */
1518 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1519     if (hEdma == NULL)
1520         {
1521         result = EDMA3_DRV_E_INVALID_PARAM;
1522         }
1524     if (((srcBIdx > EDMA3_DRV_SRCBIDX_MAX_VAL)
1525         || (srcBIdx < EDMA3_DRV_SRCBIDX_MIN_VAL))
1526         || ((srcCIdx > EDMA3_DRV_SRCCIDX_MAX_VAL)
1527         || (srcCIdx < EDMA3_DRV_SRCCIDX_MIN_VAL)))
1528         {
1529         result = EDMA3_DRV_E_INVALID_PARAM;
1530         }
1531 #endif
1533         /* Check if the parameters are OK. */
1534         if (EDMA3_DRV_SOK == result)
1535         {
1536         drvInst = (EDMA3_DRV_Instance *)hEdma;
1537         drvObject = drvInst->pDrvObjectHandle;
1539         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1540             {
1541             result =  EDMA3_DRV_E_INVALID_PARAM;
1542             }
1543         else
1544             {
1545             edma3Id = drvObject->phyCtrllerInstId;
1546             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1547                 }
1548                 }
1550         if (EDMA3_DRV_SOK == result)
1551     {
1552         /* If parameter checking is enabled... */
1553 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1554     if (lCh > edma3_log_ch_max_val [edma3Id])
1555         {
1556         result = EDMA3_DRV_E_INVALID_PARAM;
1557         }
1558 #endif
1559     }
1561         if (EDMA3_DRV_SOK == result)
1562         {
1563         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1564         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1565             {
1566             result = EDMA3_DRV_E_INVALID_PARAM;
1567             }
1568                 else
1569                 {
1570                 /* Get SrcDestBidx PaRAM Set entry */
1571                 srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1572                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
1574                 srcDstBidx &= 0xFFFF0000U;
1575                 /* Update it */
1576                 srcDstBidx |= ((uint32_t)srcBIdx & (uint32_t)0xFFFF);
1578                 /* Store it back */
1579                 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1580                             + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
1582                 /* Get SrcDestCidx PaRAM Set entry */
1583                 srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1584                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
1586                 srcDstCidx &= 0xFFFF0000U;
1587                 /* Update it */
1588                 srcDstCidx |= ((uint32_t)srcCIdx & (uint32_t)0xFFFF);
1590                 /* Store it back */
1591                 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1592                             + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
1593                 }
1594                 }
1596 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1597     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1598                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1599                 EDMA3_DVT_dCOUNTER,
1600                 EDMA3_DVT_dNONE,
1601                 EDMA3_DVT_dNONE));
1602 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1604     return result;
1605     }
1607 EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, uint32_t lCh,
1608                             int32_t destBIdx, int32_t destCIdx)
1609     {
1610     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1611     uint32_t srcDstBidx;
1612     uint32_t srcDstCidx;
1613     EDMA3_DRV_Instance *drvInst = NULL;
1614     EDMA3_DRV_Object *drvObject = NULL;
1615     int32_t paRAMId = 0;
1616     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1617         uint32_t edma3Id;
1619 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1620     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1621                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1622                 EDMA3_DVT_dCOUNTER,
1623                 EDMA3_DVT_dNONE,
1624                 EDMA3_DVT_dNONE));
1625 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1627         /* If parameter checking is enabled... */
1628 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1629     if (hEdma == NULL)
1630         {
1631         result = EDMA3_DRV_E_INVALID_PARAM;
1632         }
1634     if (((destBIdx > EDMA3_DRV_DSTBIDX_MAX_VAL)
1635         || (destBIdx < EDMA3_DRV_DSTBIDX_MIN_VAL))
1636         || ((destCIdx > EDMA3_DRV_DSTCIDX_MAX_VAL)
1637         || (destCIdx < EDMA3_DRV_DSTCIDX_MIN_VAL)))
1638         {
1639         result = EDMA3_DRV_E_INVALID_PARAM;
1640         }
1641 #endif
1643         /* Check if the parameters are OK. */
1644         if (EDMA3_DRV_SOK == result)
1645         {
1646         drvInst = (EDMA3_DRV_Instance *)hEdma;
1647         drvObject = drvInst->pDrvObjectHandle;
1649         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1650             {
1651             result =  EDMA3_DRV_E_INVALID_PARAM;
1652             }
1653         else
1654             {
1655             edma3Id = drvObject->phyCtrllerInstId;
1656             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1657                 }
1658                 }
1660         if (EDMA3_DRV_SOK == result)
1661     {
1662         /* If parameter checking is enabled... */
1663 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1664     if (lCh > edma3_log_ch_max_val [edma3Id])
1665         {
1666         result = EDMA3_DRV_E_INVALID_PARAM;
1667         }
1668 #endif
1669     }
1671         if (EDMA3_DRV_SOK == result)
1672         {
1673         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1674         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1675             {
1676             result = EDMA3_DRV_E_INVALID_PARAM;
1677             }
1678                 else
1679             {
1680             /* Get SrcDestBidx PaRAM Set entry */
1681             srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1682                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
1684             srcDstBidx &= 0xFFFFU;
1685             /* Update it */
1686             srcDstBidx |= (((uint32_t)destBIdx & (uint32_t)0xFFFF) << 16U);
1688             /* Store it back */
1689             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1690                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
1692             /* Get SrcDestCidx PaRAM Set entry */
1693             srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1694                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
1696             srcDstCidx &= 0xFFFFU;
1697             /* Update it */
1698             srcDstCidx |= (((uint32_t)destCIdx & (uint32_t)0xFFFF) << 16U);
1700             /* Store it back */
1701             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1702                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
1703             }
1704         }
1706 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1707     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1708                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1709                 EDMA3_DVT_dCOUNTER,
1710                 EDMA3_DVT_dNONE,
1711                 EDMA3_DVT_dNONE));
1712 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1714     return result;
1715     }
1717 EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
1718         uint32_t lCh, uint32_t aCnt, uint32_t bCnt, uint32_t cCnt,
1719         uint32_t bCntReload, EDMA3_DRV_SyncType syncType)
1720     {
1721     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1722     uint32_t abCnt = 0;
1723     uint32_t linkBCntReld = 0;
1724     uint32_t opt = 0;
1725     EDMA3_DRV_Instance *drvInst = NULL;
1726     EDMA3_DRV_Object *drvObject = NULL;
1727     int32_t paRAMId = 0;
1728     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1729         uint32_t edma3Id;
1731 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1732     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1733                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1734                 EDMA3_DVT_dCOUNTER,
1735                 EDMA3_DVT_dNONE,
1736                 EDMA3_DVT_dNONE));
1737 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1739         /* If parameter checking is enabled... */
1740 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1741     if (hEdma == NULL)
1742         {
1743         result = EDMA3_DRV_E_INVALID_PARAM;
1744         }
1746     if ((((aCnt > EDMA3_DRV_ACNT_MAX_VAL)
1747         || (bCnt > EDMA3_DRV_BCNT_MAX_VAL))
1748         || ((cCnt > EDMA3_DRV_CCNT_MAX_VAL)
1749         || (bCntReload > EDMA3_DRV_BCNTRELD_MAX_VAL)))
1750         || (((int32_t)syncType < (int32_t)EDMA3_DRV_SYNC_A) || (syncType > EDMA3_DRV_SYNC_AB)))
1751         {
1752         result = EDMA3_DRV_E_INVALID_PARAM;
1753         }
1754 #endif
1756         /* Check if the parameters are OK. */
1757         if (EDMA3_DRV_SOK == result)
1758         {
1759         drvInst = (EDMA3_DRV_Instance *)hEdma;
1760         drvObject = drvInst->pDrvObjectHandle;
1762         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1763             {
1764             result =  EDMA3_DRV_E_INVALID_PARAM;
1765             }
1766         else
1767             {
1768             edma3Id = drvObject->phyCtrllerInstId;
1769             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1770                 }
1771                 }
1773         if (EDMA3_DRV_SOK == result)
1774     {
1775         /* If parameter checking is enabled... */
1776 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1777     if (lCh > edma3_log_ch_max_val [edma3Id])
1778         {
1779         result = EDMA3_DRV_E_INVALID_PARAM;
1780         }
1781 #endif
1782     }
1784         if (EDMA3_DRV_SOK == result)
1785         {
1786         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1787         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1788             {
1789             result = EDMA3_DRV_E_INVALID_PARAM;
1790             }
1791                 else
1792                 {
1793                 abCnt = aCnt | ((bCnt&0xFFFFU) << 16U);
1795             /* Set aCnt and bCnt */
1796             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1797                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;
1799             /* Set cCnt */
1800             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1801                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;
1804             linkBCntReld = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1805                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
1807             linkBCntReld |= ((bCntReload & 0xFFFFU) << 16U);
1809             /* Set bCntReload */
1810             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1811                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;
1813             opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1815             /* Set Sync Type */
1816             opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK;
1817             opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK(syncType);
1819             *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1820             }
1821         }
1823 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1824     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1825                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1826                 EDMA3_DVT_dCOUNTER,
1827                 EDMA3_DVT_dNONE,
1828                 EDMA3_DVT_dNONE));
1829 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1831     return result;
1832     }
1834 EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
1835                                         uint32_t lCh,
1836                                         EDMA3_DRV_TrigMode trigMode)
1837     {
1838     EDMA3_DRV_Instance *drvInst = NULL;
1839     EDMA3_DRV_Object *drvObject = NULL;
1840     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1841     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1842         uint32_t edma3Id;
1844 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1845     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1846                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1847                 EDMA3_DVT_dCOUNTER,
1848                 EDMA3_DVT_dNONE,
1849                 EDMA3_DVT_dNONE));
1850 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1852         /* If parameter checking is enabled... */
1853 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1854     if (hEdma == NULL)
1855         {
1856         result = EDMA3_DRV_E_INVALID_PARAM;
1857         }
1858 #endif
1860         if (EDMA3_DRV_SOK == result)
1861         {
1862         drvInst = (EDMA3_DRV_Instance *)hEdma;
1863         drvObject = drvInst->pDrvObjectHandle;
1865         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1866             {
1867             result = EDMA3_DRV_E_INVALID_PARAM;
1868             }
1869         else
1870             {
1871             edma3Id = drvObject->phyCtrllerInstId;
1872             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1873                 }
1874                 }
1876     if (EDMA3_DRV_SOK == result)
1877         {
1878         /* If parameter checking is enabled... */
1879 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1880     if (lCh > edma3_log_ch_max_val [edma3Id])
1881         {
1882         result = EDMA3_DRV_E_INVALID_PARAM;
1883         }
1885     /* Trigger type is Manual */
1886     if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
1887         && (lCh > edma3_dma_ch_max_val [edma3Id]))
1888         {
1889         /* Channel Id lies outside DMA channel range */
1890         result = EDMA3_DRV_E_INVALID_PARAM;
1891         }
1893     /* Trigger type is QDMA */
1894     if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
1895         && ((lCh < edma3_qdma_ch_min_val[edma3Id])
1896         || (lCh > edma3_qdma_ch_max_val[edma3Id])))
1897         {
1898         /* Channel Id lies outside QDMA channel range */
1899         result = EDMA3_DRV_E_INVALID_PARAM;
1900         }
1902         /* Trigger type is Event */
1903     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
1904         && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
1905          & ((uint32_t)1U<<(lCh%32U))) == FALSE))
1906         {
1907         /* Channel was not mapped to any Hw Event. */
1908         result = EDMA3_DRV_E_INVALID_PARAM;
1909         }
1910 #endif
1911         }
1912                 
1913         if (EDMA3_DRV_SOK == result)
1914         {
1915         switch (trigMode)
1916             {
1917             case EDMA3_DRV_TRIG_MODE_MANUAL :
1918                 {
1919                 if (lCh < 32U)
1920                     {
1921                     drvInst->shadowRegs->ESR = (1UL << lCh);
1922                     }
1923                 else
1924                     {
1925                     drvInst->shadowRegs->ESRH = (1UL << (lCh-32U));
1926                     }
1927                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1928                                                                                                         EDMA3_DRV_TRIG_MODE_MANUAL;
1929                 }
1930                 break;
1932             case EDMA3_DRV_TRIG_MODE_QDMA :
1933                 {
1934                 drvInst->shadowRegs->QEESR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
1935                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1936                                                                                                                 EDMA3_DRV_TRIG_MODE_QDMA;
1937                 }
1938                 break;
1940             case EDMA3_DRV_TRIG_MODE_EVENT :
1941                 {
1942                 if (lCh < 32U)
1943                    {
1944                     /*clear SECR to clean any previous NULL request */
1945                     drvInst->shadowRegs->SECR = (1UL << lCh);
1947                     /*clear EMCR to clean any previous NULL request */
1948                     globalRegs->EMCR = (1UL << lCh);
1950                     drvInst->shadowRegs->EESR = (1UL << lCh);
1951                     }
1952                 else
1953                     {
1954                     /*clear SECR to clean any previous NULL request */
1955                     drvInst->shadowRegs->SECRH = (1UL << (lCh-32U));
1957                     /*clear EMCR to clean any previous NULL request */
1958                     globalRegs->EMCRH = (1UL << (lCh-32U));
1960                     drvInst->shadowRegs->EESRH = (1UL << (lCh-32U));
1961                     }
1963                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1964                                                                                                                 EDMA3_DRV_TRIG_MODE_EVENT;
1965                 }
1966                 break;
1968             default :
1969                 result = EDMA3_DRV_E_INVALID_PARAM;
1970                 break;
1971             }
1972         }
1974 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1975         EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1976                     EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1977                     EDMA3_DVT_dCOUNTER,
1978                     EDMA3_DVT_dNONE,
1979                     EDMA3_DVT_dNONE));
1980 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1982     return result;
1983     }
1985 EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
1986                                 uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
1988     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1989     EDMA3_DRV_Instance *drvInst = NULL;
1990     EDMA3_DRV_Object *drvObject = NULL;
1991     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1992         uint32_t edma3Id;
1994 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1995     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1996                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1997                 EDMA3_DVT_dCOUNTER,
1998                 EDMA3_DVT_dNONE,
1999                 EDMA3_DVT_dNONE));
2000 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2002         /* If parameter checking is enabled... */
2003 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2004     if (hEdma == NULL)
2005         {
2006         result = EDMA3_DRV_E_INVALID_PARAM;
2007         }
2008 #endif
2010         /* Check if the parameters are OK. */
2011         if (EDMA3_DRV_SOK == result)
2012         {
2013         drvInst = (EDMA3_DRV_Instance *)hEdma;
2014         drvObject = drvInst->pDrvObjectHandle;
2016         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
2017             {
2018             result = EDMA3_DRV_E_INVALID_PARAM;
2019             }
2020         else
2021             {
2022             edma3Id = drvObject->phyCtrllerInstId;
2023             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
2024                 }
2025                 }
2026         if (EDMA3_DRV_SOK == result)
2027         {
2028         /* If parameter checking is enabled... */
2029 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2030     if (lCh > edma3_log_ch_max_val [edma3Id])
2031         {
2032         result = EDMA3_DRV_E_INVALID_PARAM;
2033         }
2035     /* Trigger type is Manual */
2036     if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
2037         && (lCh > edma3_dma_ch_max_val [edma3Id]))
2038         {
2039         /* Channel Id lies outside DMA channel range */
2040         result = EDMA3_DRV_E_INVALID_PARAM;
2041         }
2043     /* Trigger type is QDMA */
2044     if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
2045         && ((lCh < edma3_qdma_ch_min_val[edma3Id])
2046         || (lCh > edma3_qdma_ch_max_val[edma3Id])))
2047         {
2048         /* Channel Id lies outside QDMA channel range */
2049         result = EDMA3_DRV_E_INVALID_PARAM;
2050         }
2052         /* Trigger type is Event */
2053     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
2054         && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
2055          & ((uint32_t)1U<<(lCh%32U))) == FALSE))
2056         {
2057         /* Channel was not mapped to any Hw Event. */
2058         result = EDMA3_DRV_E_INVALID_PARAM;
2059         }
2060 #endif
2061         }
2062                 
2063         if (EDMA3_DRV_SOK == result)
2064         {
2065         switch (trigMode)
2066             {
2067             case EDMA3_DRV_TRIG_MODE_MANUAL :
2068                 {
2069                 if (lCh < 32U)
2070                     {
2071                     if((drvInst->shadowRegs->SER & ((uint32_t)1U<<lCh))!=FALSE)
2072                         {
2073                         drvInst->shadowRegs->SECR = (1U<<lCh);
2074                         }
2075                     if((globalRegs->EMR & ((uint32_t)1U<<lCh))!=FALSE)
2076                         {
2077                         globalRegs->EMCR = (1U<<lCh);
2078                         }
2079                     }
2080                 else
2081                     {
2082                     if((drvInst->shadowRegs->SERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2083                         {
2084                         drvInst->shadowRegs->SECRH = (1U<<(lCh-32U));
2085                         }
2087                     if((globalRegs->EMRH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2088                         {
2089                         globalRegs->EMCRH = (1U<<(lCh-32U));
2090                         }
2091                     }
2092                 }
2093                 break;
2095             case EDMA3_DRV_TRIG_MODE_QDMA :
2096                 {
2097                 drvInst->shadowRegs->QEECR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
2098                 }
2099                 break;
2101             case EDMA3_DRV_TRIG_MODE_EVENT :
2102                 {
2103                 if (lCh < 32U)
2104                     {
2105                     drvInst->shadowRegs->EECR = (1U << lCh);
2107                     if((drvInst->shadowRegs->ER & ((uint32_t)1U<<lCh))!=FALSE)
2108                         {
2109                         drvInst->shadowRegs->ECR = (1U<<lCh);
2110                         }
2111                     if((drvInst->shadowRegs->SER & ((uint32_t)1U<<lCh))!=FALSE)
2112                         {
2113                         drvInst->shadowRegs->SECR = (1U<<lCh);
2114                         }
2115                     if((globalRegs->EMR & ((uint32_t)1U<<lCh))!=FALSE)
2116                         {
2117                         globalRegs->EMCR = (1U<<lCh);
2118                         }
2119                     }
2120                 else
2121                     {
2122                     drvInst->shadowRegs->EECRH = (1U << (lCh-32U));
2123                     if((drvInst->shadowRegs->ERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2124                         {
2125                         drvInst->shadowRegs->ECRH = (1U<<(lCh-32U));
2126                         }
2128                     if((drvInst->shadowRegs->SERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2129                         {
2130                         drvInst->shadowRegs->SECRH = (1U<<(lCh-32U));
2131                         }
2133                     if((globalRegs->EMRH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2134                         {
2135                         globalRegs->EMCRH = (1U<<(lCh-32U));
2136                         }
2137                     }
2138                 }
2139                 break;
2141             default :
2142                 result = EDMA3_DRV_E_INVALID_PARAM;
2143                 break;
2144             }
2145         }
2147 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2148     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2149                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
2150                 EDMA3_DVT_dCOUNTER,
2151                 EDMA3_DVT_dNONE,
2152                 EDMA3_DVT_dNONE));
2153 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2155     return result;
2156     }
2158 EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
2159                                 uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
2161     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
2162     EDMA3_DRV_Instance *drvInst = NULL;
2163     EDMA3_DRV_Object *drvObject = NULL;
2164         uint32_t edma3Id;
2166 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2167     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2168                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
2169                 EDMA3_DVT_dCOUNTER,
2170                 EDMA3_DVT_dNONE,
2171                 EDMA3_DVT_dNONE));
2172 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2174         /* If parameter checking is enabled... */
2175 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2176     if (hEdma == NULL)
2177         {
2178         result = EDMA3_DRV_E_INVALID_PARAM;
2179         }
2180 #endif
2182         /* Check if the parameters are OK. */
2183         if (EDMA3_DRV_SOK == result)
2184         {
2185         drvInst = (EDMA3_DRV_Instance *)hEdma;
2186         drvObject = drvInst->pDrvObjectHandle;
2188         if (drvObject == NULL)
2189             {
2190             result = EDMA3_DRV_E_INVALID_PARAM;
2191             }
2192         else
2193             {
2194             edma3Id = drvObject->phyCtrllerInstId;
2195                 }
2196                 }
2198     if (EDMA3_DRV_SOK == result)
2199         {
2200         /* If parameter checking is enabled... */
2201 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2202     if (lCh > edma3_log_ch_max_val [edma3Id])
2203         {
2204         result = EDMA3_DRV_E_INVALID_PARAM;
2205         }
2207     /* Trigger type is QDMA */
2208     if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
2209         && ((lCh < edma3_qdma_ch_min_val[edma3Id])
2210         || (lCh > edma3_qdma_ch_max_val[edma3Id])))
2211         {
2212         /* Channel Id lies outside QDMA channel range */
2213         result = EDMA3_DRV_E_INVALID_PARAM;
2214         }
2216         /* Trigger type is Event */
2217     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
2218         && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
2219          & ((uint32_t)1U<<(lCh%32U))) == FALSE))
2220         {
2221         /* Channel was not mapped to any Hw Event. */
2222         result = EDMA3_DRV_E_INVALID_PARAM;
2223         }
2224 #endif
2225         }
2226                 
2227         if (EDMA3_DRV_SOK == result)
2228         {
2229         switch (trigMode)
2230             {
2231             case EDMA3_DRV_TRIG_MODE_QDMA:
2232                 {
2233                 drvInst->shadowRegs->QEECR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
2234                 }
2235                 break;
2237             case EDMA3_DRV_TRIG_MODE_EVENT:
2238                 {
2239                 if (lCh < 32U)
2240                     {
2241                         drvInst->shadowRegs->EECR = (1U << lCh);
2242                     }
2243                 else
2244                     {
2245                         drvInst->shadowRegs->EECRH = (1U << (lCh-32U));
2246                     }
2247                 }
2248                 break;
2250             default :
2251                 result = EDMA3_DRV_E_INVALID_PARAM;
2252                 break;
2253             }
2254         }
2256 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2257     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2258                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
2259                 EDMA3_DVT_dCOUNTER,
2260                 EDMA3_DVT_dNONE,
2261                 EDMA3_DVT_dNONE));
2262 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2264     return result;
2265     }
2267 /* Definitions of Local functions - Start */
2268 /** Remove various mappings and do cleanup for DMA/QDMA channels */
2269 static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
2270                                  uint32_t channelId)
2271     {
2272         uint32_t intState=0;
2273     EDMA3_DRV_Instance *drvInst = NULL;
2274     EDMA3_DRV_Object *drvObject = NULL;
2275     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
2276     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
2277     EDMA3_RM_ResDesc channelObj;
2278         uint32_t edma3Id;
2280         assert (hEdma != NULL);
2282     drvInst = (EDMA3_DRV_Instance *)hEdma;
2283     drvObject = drvInst->pDrvObjectHandle;
2285     if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
2286         {
2287         result = EDMA3_DRV_E_INVALID_PARAM;
2288         }
2289     else
2290         {
2291         edma3Id = drvObject->phyCtrllerInstId;
2292         globalRegs = (volatile EDMA3_CCRL_Regs *)
2293                                 (drvObject->gblCfgParams.globalRegs);
2294         }
2296     if (EDMA3_DRV_SOK == result)
2297     {
2298         assert (channelId <= edma3_log_ch_max_val [edma3Id]);
2299     }
2301     if (EDMA3_DRV_SOK == result)
2302     {
2304     /**
2305      * Disable any ongoing transfer on the channel, if transfer was
2306      * enabled earlier.
2307      */
2308     if (EDMA3_DRV_TRIG_MODE_NONE !=
2309         edma3DrvChBoundRes[edma3Id][channelId].trigMode)
2310         {
2311         result = EDMA3_DRV_disableTransfer(hEdma, channelId,
2312             edma3DrvChBoundRes[edma3Id][channelId].trigMode);
2313         }
2314     }
2315         
2316     if (EDMA3_DRV_SOK == result)
2317         {
2318         /*
2319         * Unregister the TCC Callback function and disable the interrupts.
2320         */
2321         if (channelId < drvObject->gblCfgParams.numDmaChannels)
2322             {
2323             /* DMA channel */
2324             channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
2325             channelObj.resId = channelId;
2326             }
2327         else
2328             {
2329             /* QDMA channel */
2330             channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
2331             channelObj.resId = channelId - edma3_qdma_ch_min_val[edma3Id];
2332             }
2334         result = EDMA3_RM_unregisterTccCb(drvInst->resMgrInstance,
2335                     (EDMA3_RM_ResDesc *)&channelObj);
2336         }
2338     if (result == EDMA3_RM_SOK)
2339         {
2340         edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT, &intState);
2342         if (channelId <= edma3_dma_ch_max_val [edma3Id])
2343         {
2344             if((channelId >> 3U) < 8)
2345             {
2346                 /* DMA channel */
2347 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
2348                 /* Remove the channel to Event Queue mapping */
2349                 globalRegs->DMAQNUM[channelId >> 3U] &=
2350                                 EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
2351 #endif
2352                 /**
2353                  * If DMA channel to PaRAM Set mapping exists,
2354                  * remove it too.
2355                  */
2356                 if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
2357                     {
2358                     globalRegs->DCHMAP[channelId] &=
2359                                             EDMA3_RM_DCH_PARAM_CLR_MASK;
2360                     }
2361             }
2362             else
2363             {
2364                 result = EDMA3_DRV_E_INVALID_PARAM;
2365             }
2366         }
2367         else
2368             {
2369             /* QDMA channel */
2370 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
2371             /* Remove the channel to Event Queue mapping */
2372             globalRegs->QDMAQNUM = (globalRegs->QDMAQNUM) &
2373                 (EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-edma3_qdma_ch_min_val[edma3Id]));
2374 #endif
2375             /* Remove the channel to PARAM set mapping */
2376             /* Unmap PARAM Set Number for specified channelId */
2377             globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
2378                                         EDMA3_RM_QCH_PARAM_CLR_MASK;
2380             /* Reset the Trigger Word */
2381             globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
2382                                         EDMA3_RM_QCH_TRWORD_CLR_MASK;
2383             }
2385         edma3OsProtectExit(edma3Id,
2386                                                         (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
2387                                                         intState);
2388         }
2390     return result;
2391     }
2392 uint32_t EDMA3_DRV_getVersion (void)
2394     return EDMA3_LLD_DRV_VERSION_ID;
2397 const char* EDMA3_DRV_getVersionStr (void)
2399     return edma3LldVersionStr;
2401 /* Definitions of Local functions - End */
2403 /* End of File */