Merge pull request #28 in PROCESSOR-SDK/edma3_lld from PRSDK-3314 to master
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / src / edma3_drv_basic.c
1 /*
2  * edma3_drv_basic.c
3  *
4  * EDMA3 Driver Basic Interface Implementation. This file contains
5  * beginner-level EDMA3 Driver APIs which are required to:
6  * a) Request/free a DMA, QDMA and Link channel.
7  * b) Program various fields in the PaRAM Set like source/destination
8  * parameters, transfer parameters etc.
9  * c) Enable/disable a transfer.
10  * These APIs are provided to program a DMA/QDMA channel for simple use-cases
11  * and don't expose all the features of EDMA3 hardware. Users who want to go
12  * beyond this and have complete control on the EDMA3 hardware are advised
13  * to refer edma3_drv_adv.c source file.
14  *
15  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
16  *
17  *
18  *  Redistribution and use in source and binary forms, with or without
19  *  modification, are permitted provided that the following conditions
20  *  are met:
21  *
22  *    Redistributions of source code must retain the above copyright
23  *    notice, this list of conditions and the following disclaimer.
24  *
25  *    Redistributions in binary form must reproduce the above copyright
26  *    notice, this list of conditions and the following disclaimer in the
27  *    documentation and/or other materials provided with the
28  *    distribution.
29  *
30  *    Neither the name of Texas Instruments Incorporated nor the names of
31  *    its contributors may be used to endorse or promote products derived
32  *    from this software without specific prior written permission.
33  *
34  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45  *
46 */
48 /* EDMa3 Driver Internal Header Files */
49 #include <ti/sdo/edma3/drv/src/edma3.h>
50 /* Resource Manager Internal Header Files */
51 #include <ti/sdo/edma3/rm/src/edma3resmgr.h>
53 /* Instrumentation Header File */
54 #ifdef EDMA3_INSTRUMENTATION_ENABLED
55 #include <ti/sdo/edma3/rm/src/edma3_log.h>
56 #endif
58 /* For assert() */
59 /**
60  * Define NDEBUG to ignore assert().
61  * NDEBUG should be defined before including assert.h header file.
62  */
63 #include <assert.h>
66 /* Externel Variables */
67 /*---------------------------------------------------------------------------*/
68 /**
69  * Maximum Resource Manager Instances supported by the EDMA3 Package.
70  */
71 extern const uint32_t EDMA3_MAX_RM_INSTANCES;
74 /**
75  * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
76  *
77  * Typically one RM object will cater to one EDMA3 HW controller
78  * and will have all the global config information.
79  */
80 extern EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
83 /**
84  * \brief Region Specific Configuration structure for
85  * EDMA3 controller, to provide region specific Information.
86  *
87  * This configuration info can also be provided by the user at run-time,
88  * while calling EDMA3_RM_open (). If not provided at run-time,
89  * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
90  * for the specified platform.
91  */
92 #ifdef BUILD_C6XDSP
93 extern far EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
94 #else
95 extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
96 #endif
98 /**
99  * Handles of EDMA3 Resource Manager Instances.
100  *
101  * Used to maintain information of the EDMA3 RM Instances
102  * for each HW controller.
103  * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per
104  * EDMA3 HW.
105  */
106 #ifdef BUILD_C6XDSP
107 extern far EDMA3_RM_Instance *ptrRMIArray;
108 #else
109 extern EDMA3_RM_Instance *ptrRMIArray;
110 #endif
112 /** Local MemSet function */
113 extern void edma3MemZero(void *dst, uint32_t len);
114 /** Local MemCpy function */
115 extern void edma3MemCpy(void *dst, const void *src, uint32_t len);
117 /**
118  * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
119  *
120  * Typically one object will cater to one EDMA3 HW controller
121  * and will have all regions' (ARM, DSP etc) specific config information.
122  */
123 extern EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES];
126 /**
127  * Handles of EDMA3 Driver Instances.
128  *
129  * Used to maintain information of the EDMA3 Driver Instances for
130  * each region, for each HW controller.
131  * There could be as many Driver Instances as there are shadow
132  * regions. Multiple EDMA3 Driver instances on the same shadow
133  * region are NOT allowed.
134  */
135 extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
138 /**
139  * \brief Resources bound to a Channel
140  *
141  * When a request for a channel is made, the resources PaRAM Set and TCC
142  * get bound to that channel. This information is needed internally by the
143  * driver when a request is made to free the channel (Since it is the
144  * responsibility of the driver to free up the channel-associated resources
145  * from the Resource Manager layer).
146  */
147 extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
149 /** Max of DMA Channels */
150 extern uint32_t edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
151 /** Min of Link Channels */
152 extern uint32_t edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
153 /** Max of Link Channels */
154 extern uint32_t edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
155 /** Min of QDMA Channels */
156 extern uint32_t edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
157 /** Max of QDMA Channels */
158 extern uint32_t edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
159 /** Max of Logical Channels */
160 extern uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
162 /* Local functions prototypes */
163 /*---------------------------------------------------------------------------*/
164 /** Remove various mappings and do cleanup for DMA/QDMA channels */
165 static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
166                                  uint32_t channelId);
168 /** @brief Global Variable which describes the EDMA3 LLD Version Information */
169 const char   edma3LldVersionStr[] = EDMA3_LLD_DRV_VERSION_STR ":" __DATE__  ":" __TIME__;
170 /*---------------------------------------------------------------------------*/
172 EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
173                                     uint32_t *pLCh,
174                                     uint32_t *pTcc,
175                                     EDMA3_RM_EventQueue evtQueue,
176                                     EDMA3_RM_TccCallback tccCb,
177                                     void *cbData)
178     {
179     EDMA3_RM_ResDesc resObj;
180     EDMA3_RM_ResDesc channelObj;
181     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
182     EDMA3_DRV_Instance *drvInst = NULL;
183     EDMA3_DRV_Object *drvObject = NULL;
184     uint32_t mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP;
185     int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
186     EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
187     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
188     int32_t mappedPaRAMId;
189         uint32_t edma3Id;
190         uint32_t freeDmaQdmaChannel = FALSE;
191         uint32_t mapXbarEvtToChanFlag = FALSE;
192         uint32_t xBarEvtBeforeMap = 0;
194 #ifdef EDMA3_INSTRUMENTATION_ENABLED
195     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
196                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
197                 EDMA3_DVT_dCOUNTER,
198                 EDMA3_DVT_dNONE,
199                 EDMA3_DVT_dNONE));
200 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
203         /* If parameter checking is enabled... */
204 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
205     if ((pLCh == NULL) || (hEdma == NULL))
206         {
207         result = EDMA3_DRV_E_INVALID_PARAM;
208         }
209 #endif
211         if (EDMA3_DRV_SOK == result)
212         {
213         drvInst = (EDMA3_DRV_Instance *)hEdma;
214         drvObject = drvInst->pDrvObjectHandle;
216         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
217             {
218             result = EDMA3_DRV_E_INVALID_PARAM;
219             }
220                 }
221     if (EDMA3_DRV_SOK == result)
222         {
223             if ( drvInst->mapXbarToChan != NULL)
224                 {
225                     xBarEvtBeforeMap = *pLCh;
226                     edma3Id = drvObject->phyCtrllerInstId;
227                     if ((xBarEvtBeforeMap > edma3_dma_ch_max_val [edma3Id]) &&
228                         (xBarEvtBeforeMap < EDMA3_DRV_DMA_CHANNEL_ANY) && 
229                         ((*pLCh) == (*pTcc)))
230                         {
231                         result = drvInst->mapXbarToChan(xBarEvtBeforeMap, 
232                                     pLCh, 
233                                     &drvInst->drvXbarToEvtMapConfig);
234                         if (EDMA3_DRV_SOK == result)
235                             {
236                             *pTcc = *pLCh;
237                             mapXbarEvtToChanFlag = TRUE;
238                             }
239                 }
240             }
241         }
243         if (EDMA3_DRV_SOK == result)
244         {
245         edma3Id = drvObject->phyCtrllerInstId;
246         globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
247         
248         /* Identify the request type and validate the appropriate arguments.
249                  * Starting in the order of PaRAM Set availability,
250                  * check for a specific DMA channel request first.
251                  */
252                 if ((*pLCh) <= edma3_dma_ch_max_val [edma3Id])
253                         {
254                         /* A 'Specific' DMA channel is requested */
255                         chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
256                         /* Fill the resObj structure as well */
257                         resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
258                         resObj.resId = *pLCh;
260                         /* Check the TCC and Event Queue number */
261             if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
262                                 || (pTcc == NULL))
263                 {
264                 result = EDMA3_DRV_E_INVALID_PARAM;
265                 }
266                         }
268                 if ((*pLCh) == EDMA3_DRV_DMA_CHANNEL_ANY)
269                         {
270                         /* 'Any' DMA channel is requested */
271                         chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
272                         resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
273                         resObj.resId = EDMA3_RM_RES_ANY;
275                         /* Check the TCC and Event Queue number */
276             if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
277                                 || (pTcc == NULL))
278                 {
279                 result = EDMA3_DRV_E_INVALID_PARAM;
280                 }
281                         }
283                 if (((*pLCh) >= edma3_link_ch_min_val[edma3Id]) &&
284                                 ((*pLCh) <= edma3_link_ch_max_val[edma3Id]))
285                         {
286                         /* A 'Specific' Link channel is requested, TCC may or may not be
287                          * required.
288                          */
289                         /* Save the PaRAM Id for future use */
290                         paRAMId = *pLCh;
292                         if (pTcc != NULL)
293                                 {
294                                 if (*pTcc < drvObject->gblCfgParams.numTccs)
295                                         {
296                                         /* Argument passed as *pTcc is a valid TCC number */
297                                         chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
298                                 resObj.type = EDMA3_RM_RES_PARAM_SET;
299                                         }
300                                 else
301                                         {
302                                         /* Argument passed as *pTcc is Invalid TCC number */
303                                         result = EDMA3_DRV_E_INVALID_PARAM;
304                                         }
305                                 }
306                         else
307                                 {
308                                 /* pTcc is NULL, only Link Channel required */
309                                 chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
310                                 resObj.type = EDMA3_RM_RES_PARAM_SET;
311                                 }
312                         }
314                 if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)
315                         {
316                         /* 'Any' Link channel is requested, TCC is not required */
317                         chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
318                         resObj.type = EDMA3_RM_RES_PARAM_SET;
319                         }
321                 if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL_WITH_TCC)
322                         {
323                         if (pTcc != NULL)
324                                 {
325                                 /* 'Any' Link channel is requested, TCC is required */
326                                 if (*pTcc < drvObject->gblCfgParams.numTccs)
327                                         {
328                                         /* Argument passed as *pTcc is a valid TCC number */
329                                         chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
330                                         resObj.type = EDMA3_RM_RES_PARAM_SET;
331                                         }
332                                 else
333                                         {
334                                         /* Argument passed as *pTcc is Invalid TCC number */
335                                         result = EDMA3_DRV_E_INVALID_PARAM;
336                                         }
337                                 }
338                         else
339                                 {
340                                 /* pTcc is NULL */
341                                 result = EDMA3_DRV_E_INVALID_PARAM;
342                                 }
343                         }
345                 if (((*pLCh) >= EDMA3_DRV_QDMA_CHANNEL_0) &&
346                                 ((*pLCh) <= EDMA3_DRV_QDMA_CHANNEL_7))
347                         {
348                         /* A 'Specific' QDMA channel is requested */
349                         chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
350                         resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
351                         resObj.resId = *pLCh - EDMA3_DRV_QDMA_CHANNEL_0;
353                         /* Check the TCC and Event Queue number */
354             if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
355                                 || (pTcc == NULL))
356                 {
357                 result = EDMA3_DRV_E_INVALID_PARAM;
358                 }
359                         }
361                 if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY)
362                         {
363                         /* 'Any' QDMA channel is requested */
364                         chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
365                         resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
366                         resObj.resId = EDMA3_RM_RES_ANY;
368                         /* Check the TCC and Event Queue number */
369             if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
370                                 || (pTcc == NULL))
371                 {
372                 result = EDMA3_DRV_E_INVALID_PARAM;
373                 }
374                         }
376                 if (EDMA3_DRV_CHANNEL_TYPE_NONE == chType)
377                         {
378                         /* Invalid request */
379                         result = EDMA3_DRV_E_INVALID_PARAM;
380                         }
381                 }
383         /* Step 1: Allocate the DMA/QDMA channel first, if required */
384         if (EDMA3_DRV_SOK == result)
385         {
386         switch (chType)
387                 {
388                 case EDMA3_DRV_CHANNEL_TYPE_DMA:
389                                 result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
390                                                                                                 (EDMA3_RM_ResDesc *)&resObj);
391                 if (result == EDMA3_RM_SOK)
392                     {
393                     *pLCh = resObj.resId;
395                     mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
396                     if (mappedPaRAMId != (int32_t)EDMA3_DRV_CH_NO_PARAM_MAP)
397                         {
398                         paRAMId = mappedPaRAMId;
399                         }
401                     if (*pTcc == EDMA3_DRV_TCC_ANY)
402                         {
403                             mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];
404                         if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP)
405                             {
406                             mappedTcc = EDMA3_RM_RES_ANY;
407                             }
408                         }
409                     else
410                         {
411                         mappedTcc = *pTcc;
412                         }
414                     /* Save the Resource Type/ID for TCC registeration */
415                     channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
416                                         channelObj.resId = *pLCh;
418                                         /* Free DMA channel in case the function fails in future */
419                                         freeDmaQdmaChannel = TRUE;
420                     }
421                 else
422                     {
423                     result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;
424                     }
426                                 break;
428                 case EDMA3_DRV_CHANNEL_TYPE_QDMA:
429                                 result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
430                                                                                                 (EDMA3_RM_ResDesc *)&resObj);
431                 if (result == EDMA3_DRV_SOK)
432                     {
433                     (*pLCh) = resObj.resId + edma3_qdma_ch_min_val[edma3Id];
435                     if (*pTcc == EDMA3_DRV_TCC_ANY)
436                         {
437                         mappedTcc = EDMA3_RM_RES_ANY;
438                         }
439                     else
440                         {
441                         mappedTcc = *pTcc;
442                         }
444                     /* Save the Resource Type/ID for TCC registeration */
445                     channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
446                                         channelObj.resId = resObj.resId;
448                                         /* Free DMA channel in case the function fails in future */
449                                         freeDmaQdmaChannel = TRUE;
450                     }
451                 else
452                     {
453                     result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
454                     }
455                                 break;
457                         default:
458                                 break;
459                 }
460                 }
462         /* Step 2: Allocate the PaRAM Set */
463         if (EDMA3_DRV_SOK == result)
464         {
465         resObj.type = EDMA3_RM_RES_PARAM_SET;
466         resObj.resId = (uint32_t)paRAMId;
467         result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
468                 }
470         if (EDMA3_DRV_SOK == result)
471         {
472         paRAMId = (int32_t)resObj.resId;
474         if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
475                 {
476                 /* Link channel number should be same as the PaRAM Set */
477             *pLCh = resObj.resId;
478                         edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
479             edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
480                 }
482         if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK_TCC)
483             {
484                 /* Link channel number should be same as the PaRAM Set */
485             *pLCh = resObj.resId;
486                         edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
487             edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
489                         /* save the tcc now */
490                         edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
492             /* Set TCC in ParamSet.OPT field */
493             globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
494             globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
495             }
496                 }
497         else
498                 {
499                 /* PaRAM allocation failed, free the previously allocated DMA/QDMA
500                  * channel, if required
501                  */
502                 if (((chType == EDMA3_DRV_CHANNEL_TYPE_DMA)
503                         || (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)) &&
504                         (TRUE == freeDmaQdmaChannel))
505                         {
506                 EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
507                         }
508                 }
510         /* Step 3: Allocate TCC only for DMA/QDMA channels */
511         if ((EDMA3_DRV_SOK == result) &&
512                 ((chType == EDMA3_DRV_CHANNEL_TYPE_DMA) || (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)))
513         {
514         resObj.type = EDMA3_RM_RES_TCC;
515         resObj.resId = mappedTcc;
516         result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
518                 if (EDMA3_DRV_SOK == result)
519                 {
520                 *pTcc = resObj.resId;
522                         /* Save TCC and PaRAM set */
523                         edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
524                         edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
526                         switch (chType)
527                                 {
528                                 case EDMA3_DRV_CHANNEL_TYPE_DMA:
529                                         {
530                                         /* Step 4: Register the callback function, if required */
531                                         if (NULL != tccCb)
532                                                 {
533                             result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
534                                                                             (EDMA3_RM_ResDesc *)&channelObj,
535                                                                             *pTcc, tccCb, cbData);
536                                                 }
537                     if (result != EDMA3_DRV_SOK)
538                         {
539                         EDMA3_DRV_freeChannel (hEdma, *pLCh);
540                         result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
541                         }
542                                         else
543                                                 {
544 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
545                                                 uint32_t intState = 0;
546                         edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
547                                                                                         &intState);
548                         /* Step 5: Associate DMA Channel to Event Queue */
549                         globalRegs->DMAQNUM[(*pLCh) >> 3U] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
550                         globalRegs->DMAQNUM[(*pLCh) >> 3U] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh), evtQueue);
552                         edma3OsProtectExit(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
553                                                                                         intState);
554 #endif
556                         /* Step 6: Map PaRAM Set to DMA Channel */
557                                                 if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
558                                 {
559                                             globalRegs->DCHMAP[*pLCh] &= EDMA3_DRV_DCH_PARAM_CLR_MASK;
560                                             globalRegs->DCHMAP[*pLCh] |= EDMA3_DRV_DCH_PARAM_SET_MASK((uint32_t)paRAMId);
561                             }
563                         /* Step 7: Set TCC in ParamSet.OPT field */
564                         globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
565                         globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
567                                                 edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
568                                                 }
569                                         }
570                                         break;
572                                 case EDMA3_DRV_CHANNEL_TYPE_QDMA:
573                                         {
574                                         uint32_t qdmaChannel = channelObj.resId;
576                                         /* Step 4: Register the callback function, if required */
577                                         if (NULL != tccCb)
578                                                 {
579                             result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
580                                                                             (EDMA3_RM_ResDesc *)&channelObj,
581                                                                             *pTcc, tccCb, cbData);
582                                                 }
583                     if (result != EDMA3_DRV_SOK)
584                         {
585                         EDMA3_DRV_freeChannel (hEdma, *pLCh);
586                         result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
587                         }
588                                         else
589                                                 {
590 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
591                                                 uint32_t intState = 0;
592                         edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
593                                                                                         &intState);
594                         /* Step 5: Associate QDMA Channel to Event Queue */
595                         globalRegs->QDMAQNUM &= EDMA3_DRV_QDMAQNUM_CLR_MASK(qdmaChannel);
596                         globalRegs->QDMAQNUM |= EDMA3_DRV_QDMAQNUM_SET_MASK(qdmaChannel, evtQueue);
598                         edma3OsProtectExit(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
599                                                                                         intState);
600 #endif
602                         /* Step 6: Map PaRAM Set to DMA Channel and set the Default Trigger Word */
603                                         globalRegs->QCHMAP[qdmaChannel] &= EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK;
604                                         globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_PARAM_SET_MASK((uint32_t)paRAMId);
605                                         globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT);
607                         /* Step 7: Set TCC in ParamSet.OPT field */
608                         globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
609                         globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
611                                                 edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
613                                                 /* Step 8: Enable the QDMA Channel */
614                                                 drvInst->shadowRegs->QEESR = 1U << qdmaChannel;
615                                                 }
616                                         }
617                                         break;
618                                 default:
619                                         break;
620                                 }
621                         }
622                 else
623                         {
624                         /* TCC allocation failed, free the PaRAM Set, */
625             resObj.type = EDMA3_RM_RES_PARAM_SET;
626             resObj.resId = (uint32_t)paRAMId;
627             EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
629                         /* And free the DMA/QDMA channel */
630                         EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
632                         result = EDMA3_DRV_E_TCC_UNAVAIL;
633                         }
634                 }
636         if (EDMA3_DRV_SOK == result)
637         {
638                 if ((drvInst->configScrMapXbarToEvt != NULL) && 
639                         (mapXbarEvtToChanFlag == TRUE))
640                         {
641                         drvInst->configScrMapXbarToEvt(xBarEvtBeforeMap, *pLCh);
642                         }
643         }
645 #ifdef EDMA3_INSTRUMENTATION_ENABLED
646     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
647                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
648                 EDMA3_DVT_dCOUNTER,
649                 EDMA3_DVT_dNONE,
650                 EDMA3_DVT_dNONE));
651 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
653     return result;
656 EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
657                                                 uint32_t channelId)
658     {
659     EDMA3_RM_ResDesc resObj;
660     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
661     EDMA3_DRV_Instance *drvInst = NULL;
662     EDMA3_DRV_Object *drvObject = NULL;
663     int32_t paRAMId;
664     uint32_t tcc;
665     EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
666     uint32_t edma3Id;
668 #ifdef EDMA3_INSTRUMENTATION_ENABLED
669     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
670                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
671                 EDMA3_DVT_dCOUNTER,
672                 EDMA3_DVT_dNONE,
673                 EDMA3_DVT_dNONE));
674 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
676         /* If parameter checking is enabled... */
677 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
678     if (hEdma == NULL)
679         {
680         result = EDMA3_DRV_E_INVALID_PARAM;
681         }
682 #endif
684     if (EDMA3_DRV_SOK == result)
685         {
686         drvInst = (EDMA3_DRV_Instance *)hEdma;
687         drvObject = drvInst->pDrvObjectHandle;
689         if (drvObject == NULL)
690             {
691             result = EDMA3_DRV_E_INVALID_PARAM;
692             }
693                 else
694                         {
695                         edma3Id = drvObject->phyCtrllerInstId;
696                         }
697         }
699     if (EDMA3_DRV_SOK == result)
700         {
701         /* Check the channel type */
702         if (channelId <= edma3_dma_ch_max_val [edma3Id])
703             {
704             /* DMA Channel */
705             chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
706             }
708         if ((channelId >= edma3_link_ch_min_val[edma3Id])
709                                 && (channelId <= edma3_link_ch_max_val[edma3Id]))
710             {
711             /* LINK Channel */
712             chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
713             }
715         if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
716                                 && (channelId <= edma3_qdma_ch_max_val[edma3Id]))
717             {
718             /* QDMA Channel */
719             chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
720             }
722         if (chType == EDMA3_DRV_CHANNEL_TYPE_NONE)
723             {
724             result = EDMA3_DRV_E_INVALID_PARAM;
725             }
726         }
729     if (EDMA3_DRV_SOK == result)
730         {
731         if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
732             {
733             /* LINK Channel */
734             resObj.type = EDMA3_RM_RES_PARAM_SET;
736             /* Get the PaRAM id from the book-keeping info. */
737             resObj.resId = (uint32_t)(edma3DrvChBoundRes[edma3Id][channelId].paRAMId);
739             result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
740                                         (EDMA3_RM_ResDesc *)&resObj);
742             if (EDMA3_DRV_SOK == result)
743                 {
744                 edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
745                 }
746             }
747         else
748             {
749             /* DMA/QDMA Channel */
750             paRAMId = edma3DrvChBoundRes[edma3Id][channelId].paRAMId;
751             tcc = edma3DrvChBoundRes[edma3Id][channelId].tcc;
753             /* Check the paRAMId and tcc values first */
754             if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
755                 {
756                 result = EDMA3_DRV_E_INVALID_PARAM;
757                 }
759             if (tcc >= drvObject->gblCfgParams.numTccs)
760                 {
761                 result = EDMA3_DRV_E_INVALID_PARAM;
762                 }
764             if (EDMA3_DRV_SOK == result)
765                 {
766                 /* Disable the transfer and remove various mappings. */
767                 result = edma3RemoveMapping(hEdma, channelId);
768                 }
770             if (EDMA3_DRV_SOK == result)
771                 {
772                 /* Now Free the PARAM set and TCC */
773                 resObj.type = EDMA3_RM_RES_PARAM_SET;
774                 resObj.resId = (uint32_t)paRAMId;
775                 result = EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
777                 if (EDMA3_DRV_SOK == result)
778                     {
779                     /* PaRAM Set Freed */
780                     edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
782                     /* Free the TCC */
783                     resObj.type = EDMA3_RM_RES_TCC;
784                     resObj.resId = tcc;
785                     result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
786                                                 (EDMA3_RM_ResDesc *)&resObj);
787                     }
789                 if (EDMA3_DRV_SOK == result)
790                     {
791                     /* TCC Freed. */
792                     edma3DrvChBoundRes[edma3Id][channelId].tcc = EDMA3_MAX_TCC;
794                     /* Now free the DMA/QDMA Channel in the end. */
795                     if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)
796                         {
797                         resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
798                         resObj.resId = (channelId - edma3_qdma_ch_min_val[edma3Id]);
799                         result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
800                                                     (EDMA3_RM_ResDesc *)&resObj);
801                         }
802                     else
803                         {
804                         resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
805                         resObj.resId = channelId;
806                         result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
807                                                     (EDMA3_RM_ResDesc *)&resObj);
808                         }
809                     }
810                 }
811             }
812         }
814 #ifdef EDMA3_INSTRUMENTATION_ENABLED
815     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
816                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
817                 EDMA3_DVT_dCOUNTER,
818                 EDMA3_DVT_dNONE,
819                 EDMA3_DVT_dNONE));
820 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
822     return result;
823     }
825 EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
826                                                 uint32_t channelId)
828     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
829     EDMA3_DRV_Instance *drvInst = NULL;
830     EDMA3_DRV_Object *drvObject = NULL;
831     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
832     uint32_t count;
833     uint32_t value = 0;
834         uint32_t edma3Id;
836 #ifdef EDMA3_INSTRUMENTATION_ENABLED
837     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
838                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
839                 EDMA3_DVT_dCOUNTER,
840                 EDMA3_DVT_dNONE,
841                 EDMA3_DVT_dNONE));
842 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
844         /* If parameter checking is enabled... */
845 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
846     if (hEdma == NULL)
847         {
848         result = EDMA3_DRV_E_INVALID_PARAM;
849         }
850 #endif
852         /* Check if the parameters are OK. */
853         if (EDMA3_DRV_SOK == result)
854         {
855         drvInst = (EDMA3_DRV_Instance *)hEdma;
856         drvObject = drvInst->pDrvObjectHandle;
858         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
859             {
860             result = EDMA3_DRV_E_INVALID_PARAM;
861             }
862         else
863             {
864             edma3Id = drvObject->phyCtrllerInstId;
866                         /* If parameter checking is enabled... */
867 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
868             if (channelId > edma3_dma_ch_max_val [edma3Id])
869                 {
870                 result = EDMA3_DRV_E_INVALID_PARAM;
871                 }
872 #endif
874                         /* Check if the parameters are OK. */
875                         if (EDMA3_DRV_SOK == result)
876                 {
877                 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
879 #ifdef EDMA3_DRV_DEBUG
880             EDMA3_DRV_PRINTF("EMR =%l\r\n", globalRegs->EMR);
881 #endif
882                 if(channelId < 32U)
883                     {
884                     /* Disables the DMA channels */
885                     drvInst->shadowRegs->EECR = (1U << channelId);
886                     /* Write to EMCR to clear the corresponding EMR bit */
887                     globalRegs->EMCR = (1U << channelId);
888                     /* Clears the SER */
889                     drvInst->shadowRegs->SECR = (1U << channelId);
890                     }
891                 else
892                     {
893 #ifdef EDMA3_DRV_DEBUG
894                     EDMA3_DRV_PRINTF("EMRH =%l\r\n", globalRegs->EMRH);
895 #endif
896                     /* Disables the DMA channels */
897                     drvInst->shadowRegs->EECRH = (1U << (channelId - 32U));
898                     /* Write to EMCR to clear the corresponding EMR bit */
899                     globalRegs->EMCRH = (1U << (channelId - 32U));
900                     /* Clears the SER */
901                     drvInst->shadowRegs->SECRH = (1U << (channelId - 32U));
902                     }
904                 /* Clear the global CC Error Register */
905                 for (count = 0; count < drvObject->gblCfgParams.numEvtQueue; count++)
906                     {
907                     value |= (((uint32_t)1U) << count);
908                     }
910                 globalRegs->CCERRCLR = (EDMA3_CCRL_CCERR_TCCERR_MASK | value);
911                 }
912             }
913         }
915 #ifdef EDMA3_INSTRUMENTATION_ENABLED
916     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
917                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
918                 EDMA3_DVT_dCOUNTER,
919                 EDMA3_DVT_dNONE,
920                 EDMA3_DVT_dNONE));
921 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
923     return result;
924     }
926 EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
927                     uint32_t lCh,
928                     EDMA3_DRV_OptField optField,
929                     uint32_t newOptFieldVal)
930     {
931     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
932     EDMA3_DRV_Instance *drvInst = NULL;
933     EDMA3_DRV_Object *drvObject = NULL;
934     uint32_t newOptVal = 0;
935     uint32_t oldOptVal = 0;
936     int32_t paRAMId = 0;
937     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
938         uint32_t edma3Id;
940 #ifdef EDMA3_INSTRUMENTATION_ENABLED
941     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
942                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
943                 EDMA3_DVT_dCOUNTER,
944                 EDMA3_DVT_dNONE,
945                 EDMA3_DVT_dNONE));
946 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
948         /* If parameter checking is enabled... */
949 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
950     if ((hEdma == NULL)
951         || (((int32_t)optField < (int32_t)EDMA3_DRV_OPT_FIELD_SAM)
952         || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
953         {
954         result = EDMA3_DRV_E_INVALID_PARAM;
955         }
956 #endif
958         /* Check if the parameters are OK. */
959         if (EDMA3_DRV_SOK == result)
960         {
961         drvInst = (EDMA3_DRV_Instance *)hEdma;
962         drvObject = drvInst->pDrvObjectHandle;
964         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
965             {
966             result = EDMA3_DRV_E_INVALID_PARAM;
967             }
968         else
969             {
970             edma3Id = drvObject->phyCtrllerInstId;
971             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
972                 }
973                 }
975     if (EDMA3_DRV_SOK == result)
976     {
977         /* If parameter checking is enabled... */
978 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
979     if (lCh > edma3_log_ch_max_val [edma3Id])
980         {
981         result = EDMA3_DRV_E_INVALID_PARAM;
982         }
983 #endif
984     }
985         
986         if (EDMA3_DRV_SOK == result)
987         {
988         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
989         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
990             {
991             result = EDMA3_DRV_E_INVALID_PARAM;
992             }
993                 }
995     if (EDMA3_DRV_SOK == result)
996         {
997         oldOptVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
999         switch (optField)
1000             {
1001             case EDMA3_DRV_OPT_FIELD_SAM :
1002                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_SAM_CLR_MASK)
1003                             |
1004                             (EDMA3_DRV_OPT_SAM_SET_MASK(newOptFieldVal));
1005                 break;
1006             case EDMA3_DRV_OPT_FIELD_DAM :
1007                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_DAM_CLR_MASK)
1008                             |
1009                             (EDMA3_DRV_OPT_DAM_SET_MASK(newOptFieldVal));
1010                 break;
1011             case EDMA3_DRV_OPT_FIELD_SYNCDIM :
1012                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_SYNCDIM_CLR_MASK)
1013                             |
1014                             (EDMA3_DRV_OPT_SYNCDIM_SET_MASK(newOptFieldVal));
1015                 break;
1016             case EDMA3_DRV_OPT_FIELD_STATIC :
1017                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_STATIC_CLR_MASK)
1018                             |
1019                             (EDMA3_DRV_OPT_STATIC_SET_MASK(newOptFieldVal));
1020                 break;
1021             case EDMA3_DRV_OPT_FIELD_FWID :
1022                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_FWID_CLR_MASK)
1023                             |
1024                             (EDMA3_DRV_OPT_FWID_SET_MASK(newOptFieldVal));
1025                 break;
1026             case EDMA3_DRV_OPT_FIELD_TCCMODE :
1027                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCMODE_CLR_MASK)
1028                             |
1029                             (EDMA3_DRV_OPT_TCCMODE_SET_MASK(newOptFieldVal));
1030                 break;
1031             case EDMA3_DRV_OPT_FIELD_TCC :
1032                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
1033                             |
1034                             (EDMA3_DRV_OPT_TCC_SET_MASK(newOptFieldVal));
1035                 break;
1036             case EDMA3_DRV_OPT_FIELD_TCINTEN :
1037                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCINTEN_CLR_MASK)
1038                             |
1039                             (EDMA3_DRV_OPT_TCINTEN_SET_MASK(newOptFieldVal));
1040                 break;
1041             case EDMA3_DRV_OPT_FIELD_ITCINTEN :
1042                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCINTEN_CLR_MASK)
1043                             |
1044                             (EDMA3_DRV_OPT_ITCINTEN_SET_MASK(newOptFieldVal));
1045                 break;
1046             case EDMA3_DRV_OPT_FIELD_TCCHEN :
1047                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCHEN_CLR_MASK)
1048                             |
1049                             (EDMA3_DRV_OPT_TCCHEN_SET_MASK(newOptFieldVal));
1050                 break;
1051             case EDMA3_DRV_OPT_FIELD_ITCCHEN :
1052                 newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCCHEN_CLR_MASK)
1053                             |
1054                             (EDMA3_DRV_OPT_ITCCHEN_SET_MASK(newOptFieldVal));
1055                 break;
1056             default:
1057                 break;
1058             }
1060         *(&globalRegs->PARAMENTRY[paRAMId].OPT) = newOptVal;
1061         }
1063 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1064     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1065                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1066                 EDMA3_DVT_dCOUNTER,
1067                 EDMA3_DVT_dNONE,
1068                 EDMA3_DVT_dNONE));
1069 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1071     return result;
1072     }
1074 EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
1075                     uint32_t lCh,
1076                     EDMA3_DRV_OptField optField,
1077                     uint32_t *optFieldVal)
1078     {
1079     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1080     EDMA3_DRV_Instance *drvInst = NULL;
1081     EDMA3_DRV_Object *drvObject = NULL;
1082     uint32_t optVal = 0;
1083     int32_t paRAMId = 0;
1084     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1085         uint32_t edma3Id;
1087 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1088     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1089                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1090                 EDMA3_DVT_dCOUNTER,
1091                 EDMA3_DVT_dNONE,
1092                 EDMA3_DVT_dNONE));
1093 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1095         /* If parameter checking is enabled... */
1096 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1097     if (((hEdma == NULL) || (optFieldVal == NULL))
1098         || (((int32_t)optField < (int32_t)EDMA3_DRV_OPT_FIELD_SAM)
1099         || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
1100         {
1101         result = EDMA3_DRV_E_INVALID_PARAM;
1102         }
1103 #endif
1105         /* Check if the parameters are OK. */
1106         if (EDMA3_DRV_SOK == result)
1107         {
1108         drvInst = (EDMA3_DRV_Instance *)hEdma;
1109         drvObject = drvInst->pDrvObjectHandle;
1111         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1112             {
1113             result = EDMA3_DRV_E_INVALID_PARAM;
1114             }
1115         else
1116             {
1117             edma3Id = drvObject->phyCtrllerInstId;
1118             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1119                 }
1120                 }
1122     if (EDMA3_DRV_SOK == result)
1123     {
1124         /* If parameter checking is enabled... */
1125 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1126     if (lCh > edma3_log_ch_max_val [edma3Id])
1127         {
1128         result = EDMA3_DRV_E_INVALID_PARAM;
1129         }
1130 #endif
1131     }
1133         if (EDMA3_DRV_SOK == result)
1134         {
1135         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1136         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1137             {
1138             result = EDMA3_DRV_E_INVALID_PARAM;
1139             }
1140                 }
1142     if (EDMA3_DRV_SOK == result)
1143         {
1144         optVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1146         switch (optField)
1147             {
1148             case EDMA3_DRV_OPT_FIELD_SAM :
1149                 *optFieldVal = EDMA3_DRV_OPT_SAM_GET_MASK(optVal);
1150                 break;
1151             case EDMA3_DRV_OPT_FIELD_DAM :
1152                 *optFieldVal = EDMA3_DRV_OPT_DAM_GET_MASK(optVal);
1153                 break;
1154             case EDMA3_DRV_OPT_FIELD_SYNCDIM :
1155                 *optFieldVal = EDMA3_DRV_OPT_SYNCDIM_GET_MASK(optVal);
1156                 break;
1157             case EDMA3_DRV_OPT_FIELD_STATIC :
1158                 *optFieldVal = EDMA3_DRV_OPT_STATIC_GET_MASK(optVal);
1159                 break;
1160             case EDMA3_DRV_OPT_FIELD_FWID :
1161                 *optFieldVal = EDMA3_DRV_OPT_FWID_GET_MASK(optVal);
1162                 break;
1163             case EDMA3_DRV_OPT_FIELD_TCCMODE :
1164                 *optFieldVal = EDMA3_DRV_OPT_TCCMODE_GET_MASK(optVal);
1165                 break;
1166             case EDMA3_DRV_OPT_FIELD_TCC :
1167                 *optFieldVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
1168                 break;
1169             case EDMA3_DRV_OPT_FIELD_TCINTEN :
1170                 *optFieldVal = EDMA3_DRV_OPT_TCINTEN_GET_MASK(optVal);
1171                 break;
1172             case EDMA3_DRV_OPT_FIELD_ITCINTEN :
1173                 *optFieldVal = EDMA3_DRV_OPT_ITCINTEN_GET_MASK(optVal);
1174                 break;
1175             case EDMA3_DRV_OPT_FIELD_TCCHEN :
1176                 *optFieldVal = EDMA3_DRV_OPT_TCCHEN_GET_MASK(optVal);
1177                 break;
1178             case EDMA3_DRV_OPT_FIELD_ITCCHEN :
1179                 *optFieldVal = EDMA3_DRV_OPT_ITCCHEN_GET_MASK(optVal);
1180                 break;
1181             default:
1182                 break;
1183             }
1184         }
1186 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1187     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1188                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1189                 EDMA3_DVT_dCOUNTER,
1190                 EDMA3_DVT_dNONE,
1191                 EDMA3_DVT_dNONE));
1192 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1194     return result;
1195     }
1197 EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
1198                     uint32_t lCh,
1199                     uint32_t srcAddr,
1200                     EDMA3_DRV_AddrMode addrMode,
1201                     EDMA3_DRV_FifoWidth fifoWidth)
1202     {
1203     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1204     uint32_t opt = 0;
1205     EDMA3_DRV_Instance *drvInst = NULL;
1206     EDMA3_DRV_Object *drvObject = NULL;
1207     int32_t paRAMId = 0;
1208     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1209     uint32_t mappedEvtQ = 0;
1210     uint32_t defaultBurstSize = 0;
1211         uint32_t edma3Id;
1213 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1214     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1215                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1216                 EDMA3_DVT_dCOUNTER,
1217                 EDMA3_DVT_dNONE,
1218                 EDMA3_DVT_dNONE));
1219 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1221         /* If parameter checking is enabled... */
1222 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1223     if ((hEdma == NULL)
1224         || ((((int32_t)addrMode < (int32_t)EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
1225         || (((int32_t)fifoWidth < (int32_t)EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
1226         {
1227         result = EDMA3_DRV_E_INVALID_PARAM;
1228         }
1230     /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
1231     if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1232         && ((srcAddr & 0x1FU) != 0x0))
1233         {
1234         /** Memory is not 32 bytes aligned */
1235         result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
1236         }
1237 #endif
1239         /* Check if the parameters are OK. */
1240         if (EDMA3_DRV_SOK == result)
1241         {
1242         drvInst = (EDMA3_DRV_Instance *)hEdma;
1243         drvObject = drvInst->pDrvObjectHandle;
1245         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1246             {
1247             result =  EDMA3_DRV_E_INVALID_PARAM;
1248             }
1249         else
1250             {
1251             edma3Id = drvObject->phyCtrllerInstId;
1252             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1253                 }
1254                 }
1256         if (EDMA3_DRV_SOK == result)
1257     {
1258         /* If parameter checking is enabled... */
1259 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1260     if (lCh > edma3_log_ch_max_val [edma3Id])
1261         {
1262         result = EDMA3_DRV_E_INVALID_PARAM;
1263         }
1264 #endif
1265     }
1267         if (EDMA3_DRV_SOK == result)
1268         {
1269         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1270         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1271             {
1272             result = EDMA3_DRV_E_INVALID_PARAM;
1273             }
1274                 }
1276         if (EDMA3_DRV_SOK == result)
1277         {
1278         /**
1279           * If request is for FIFO mode, check whether the FIFO size
1280           * is supported by the Transfer Controller which will be used for
1281           * this transfer or not.
1282           */
1283         if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1284             {
1285             if (lCh <= edma3_dma_ch_max_val [edma3Id])
1286                 {
1287                 mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3U])
1288                                 & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
1289                                   >> ((lCh%8U)*4U);
1290                 }
1291             else
1292                 {
1293                 if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
1294                      &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
1295                     {
1296                     mappedEvtQ = ((globalRegs->QDMAQNUM)
1297                                     & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
1298                                    >> (lCh*4U);
1299                     }
1300                 }
1302             /**
1303                * mappedEvtQ contains the event queue and hence the TC which will
1304                * process this transfer request. Check whether this TC supports the
1305                * FIFO size or not.
1306                */
1307             defaultBurstSize = (uint32_t)1U << fifoWidth;
1308             if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
1309                 {
1310                 result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
1311                 }
1312             }
1313         }
1315         if (EDMA3_DRV_SOK == result)
1316         {
1317         /* Set Src Address */
1318         *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
1319                     (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;
1321         opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1323         /* Set SAM */
1324         opt &= EDMA3_DRV_OPT_SAM_CLR_MASK;
1325         opt |= EDMA3_DRV_OPT_SAM_SET_MASK(addrMode);
1326         /* Set FIFO Width */
1327         opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
1328         opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
1330         /* Set the OPT */
1331         *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1332         }
1334 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1335     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1336                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1337                 EDMA3_DVT_dCOUNTER,
1338                 EDMA3_DVT_dNONE,
1339                 EDMA3_DVT_dNONE));
1340 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1342     return result;
1343     }
1345 EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
1346                     uint32_t lCh,
1347                     uint32_t destAddr,
1348                     EDMA3_DRV_AddrMode addrMode,
1349                     EDMA3_DRV_FifoWidth fifoWidth)
1350     {
1351     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1352     uint32_t opt = 0;
1353     EDMA3_DRV_Instance *drvInst = NULL;
1354     EDMA3_DRV_Object *drvObject = NULL;
1355     int32_t paRAMId = 0;
1356     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1357     uint32_t mappedEvtQ = 0;
1358     uint32_t defaultBurstSize = 0;
1359         uint32_t edma3Id;
1361 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1362     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1363                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1364                 EDMA3_DVT_dCOUNTER,
1365                 EDMA3_DVT_dNONE,
1366                 EDMA3_DVT_dNONE));
1367 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1369         /* If parameter checking is enabled... */
1370 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1371     if ((hEdma == NULL)
1372         || ((((int32_t)addrMode < (int32_t)EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
1373         || (((int32_t)fifoWidth < (int32_t)EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
1374         {
1375         result = EDMA3_DRV_E_INVALID_PARAM;
1376         }
1378     /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
1379     if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1380         && ((destAddr & 0x1FU)!=0x0))
1381         {
1382         /** Memory is not 32 bytes aligned */
1383         result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
1384         }
1385 #endif
1387         /* Check if the parameters are OK. */
1388         if (EDMA3_DRV_SOK == result)
1389         {
1390         drvInst = (EDMA3_DRV_Instance *)hEdma;
1391         drvObject = drvInst->pDrvObjectHandle;
1393         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1394             {
1395             result =  EDMA3_DRV_E_INVALID_PARAM;
1396             }
1397         else
1398             {
1399             edma3Id = drvObject->phyCtrllerInstId;
1400             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1401                 }
1402                 }
1404         if (EDMA3_DRV_SOK == result)
1405     {
1406         /* If parameter checking is enabled... */
1407 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1408     if (lCh > edma3_log_ch_max_val [edma3Id])
1409         {
1410         result = EDMA3_DRV_E_INVALID_PARAM;
1411         }
1412 #endif
1413     }
1414         
1415         if (EDMA3_DRV_SOK == result)
1416         {
1417         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1418         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1419             {
1420             result = EDMA3_DRV_E_INVALID_PARAM;
1421             }
1422                 }
1424     if (EDMA3_DRV_SOK == result)
1425         {
1426         /**
1427           * If request is for FIFO mode, check whether the FIFO size
1428           * is supported by the Transfer Controller which will be used for
1429           * this transfer or not.
1430           */
1431         if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1432             {
1433             if (lCh <= edma3_dma_ch_max_val [edma3Id])
1434                 {
1435                 mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3U])
1436                                 & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
1437                                   >> ((lCh%8U)*4U);
1438                 }
1439             else
1440                 {
1441                 if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
1442                      &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
1443                     {
1444                     mappedEvtQ = ((globalRegs->QDMAQNUM)
1445                                     & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
1446                                    >> (lCh*4U);
1447                     }
1448                 }
1450             /**
1451                * mappedEvtQ contains the event queue and hence the TC which will
1452                * process this transfer request. Check whether this TC supports the
1453                * FIFO size or not.
1454                */
1455             defaultBurstSize = (uint32_t)1U << fifoWidth;
1456             if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
1457                 {
1458                 result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
1459                 }
1460             }
1461         }
1463     if (EDMA3_DRV_SOK == result)
1464         {
1465         /* Set the Dest address */
1466         *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
1467                     (uint32_t)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;
1469         opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1471         /* Set DAM */
1472         opt &= EDMA3_DRV_OPT_DAM_CLR_MASK;
1473         opt |= EDMA3_DRV_OPT_DAM_SET_MASK(addrMode);
1474         /* Set FIFO Width */
1475         opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
1476         opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
1478         /* Set the OPT */
1479         *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1480         }
1482 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1483     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1484                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1485                 EDMA3_DVT_dCOUNTER,
1486                 EDMA3_DVT_dNONE,
1487                 EDMA3_DVT_dNONE));
1488 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1490     return result;
1491     }
1493 EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
1494                     uint32_t lCh,
1495                     int32_t srcBIdx, int32_t srcCIdx)
1496     {
1497     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1498     uint32_t srcDstBidx;
1499     uint32_t srcDstCidx;
1500     EDMA3_DRV_Instance *drvInst = NULL;
1501     EDMA3_DRV_Object *drvObject = NULL;
1502     int32_t paRAMId = 0;
1503     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1504         uint32_t edma3Id;
1506 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1507     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1508                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1509                 EDMA3_DVT_dCOUNTER,
1510                 EDMA3_DVT_dNONE,
1511                 EDMA3_DVT_dNONE));
1512 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1514         /* If parameter checking is enabled... */
1515 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1516     if (hEdma == NULL)
1517         {
1518         result = EDMA3_DRV_E_INVALID_PARAM;
1519         }
1521     if (((srcBIdx > EDMA3_DRV_SRCBIDX_MAX_VAL)
1522         || (srcBIdx < EDMA3_DRV_SRCBIDX_MIN_VAL))
1523         || ((srcCIdx > EDMA3_DRV_SRCCIDX_MAX_VAL)
1524         || (srcCIdx < EDMA3_DRV_SRCCIDX_MIN_VAL)))
1525         {
1526         result = EDMA3_DRV_E_INVALID_PARAM;
1527         }
1528 #endif
1530         /* Check if the parameters are OK. */
1531         if (EDMA3_DRV_SOK == result)
1532         {
1533         drvInst = (EDMA3_DRV_Instance *)hEdma;
1534         drvObject = drvInst->pDrvObjectHandle;
1536         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1537             {
1538             result =  EDMA3_DRV_E_INVALID_PARAM;
1539             }
1540         else
1541             {
1542             edma3Id = drvObject->phyCtrllerInstId;
1543             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1544                 }
1545                 }
1547         if (EDMA3_DRV_SOK == result)
1548     {
1549         /* If parameter checking is enabled... */
1550 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1551     if (lCh > edma3_log_ch_max_val [edma3Id])
1552         {
1553         result = EDMA3_DRV_E_INVALID_PARAM;
1554         }
1555 #endif
1556     }
1558         if (EDMA3_DRV_SOK == result)
1559         {
1560         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1561         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1562             {
1563             result = EDMA3_DRV_E_INVALID_PARAM;
1564             }
1565                 else
1566                 {
1567                 /* Get SrcDestBidx PaRAM Set entry */
1568                 srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1569                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
1571                 srcDstBidx &= 0xFFFF0000U;
1572                 /* Update it */
1573                 srcDstBidx |= ((uint32_t)srcBIdx & (uint32_t)0xFFFF);
1575                 /* Store it back */
1576                 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1577                             + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
1579                 /* Get SrcDestCidx PaRAM Set entry */
1580                 srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1581                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
1583                 srcDstCidx &= 0xFFFF0000U;
1584                 /* Update it */
1585                 srcDstCidx |= ((uint32_t)srcCIdx & (uint32_t)0xFFFF);
1587                 /* Store it back */
1588                 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1589                             + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
1590                 }
1591                 }
1593 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1594     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1595                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1596                 EDMA3_DVT_dCOUNTER,
1597                 EDMA3_DVT_dNONE,
1598                 EDMA3_DVT_dNONE));
1599 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1601     return result;
1602     }
1604 EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, uint32_t lCh,
1605                             int32_t destBIdx, int32_t destCIdx)
1606     {
1607     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1608     uint32_t srcDstBidx;
1609     uint32_t srcDstCidx;
1610     EDMA3_DRV_Instance *drvInst = NULL;
1611     EDMA3_DRV_Object *drvObject = NULL;
1612     int32_t paRAMId = 0;
1613     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1614         uint32_t edma3Id;
1616 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1617     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1618                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1619                 EDMA3_DVT_dCOUNTER,
1620                 EDMA3_DVT_dNONE,
1621                 EDMA3_DVT_dNONE));
1622 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1624         /* If parameter checking is enabled... */
1625 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1626     if (hEdma == NULL)
1627         {
1628         result = EDMA3_DRV_E_INVALID_PARAM;
1629         }
1631     if (((destBIdx > EDMA3_DRV_DSTBIDX_MAX_VAL)
1632         || (destBIdx < EDMA3_DRV_DSTBIDX_MIN_VAL))
1633         || ((destCIdx > EDMA3_DRV_DSTCIDX_MAX_VAL)
1634         || (destCIdx < EDMA3_DRV_DSTCIDX_MIN_VAL)))
1635         {
1636         result = EDMA3_DRV_E_INVALID_PARAM;
1637         }
1638 #endif
1640         /* Check if the parameters are OK. */
1641         if (EDMA3_DRV_SOK == result)
1642         {
1643         drvInst = (EDMA3_DRV_Instance *)hEdma;
1644         drvObject = drvInst->pDrvObjectHandle;
1646         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1647             {
1648             result =  EDMA3_DRV_E_INVALID_PARAM;
1649             }
1650         else
1651             {
1652             edma3Id = drvObject->phyCtrllerInstId;
1653             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1654                 }
1655                 }
1657         if (EDMA3_DRV_SOK == result)
1658     {
1659         /* If parameter checking is enabled... */
1660 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1661     if (lCh > edma3_log_ch_max_val [edma3Id])
1662         {
1663         result = EDMA3_DRV_E_INVALID_PARAM;
1664         }
1665 #endif
1666     }
1668         if (EDMA3_DRV_SOK == result)
1669         {
1670         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1671         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1672             {
1673             result = EDMA3_DRV_E_INVALID_PARAM;
1674             }
1675                 else
1676             {
1677             /* Get SrcDestBidx PaRAM Set entry */
1678             srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1679                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
1681             srcDstBidx &= 0xFFFFU;
1682             /* Update it */
1683             srcDstBidx |= (((uint32_t)destBIdx & (uint32_t)0xFFFF) << 16U);
1685             /* Store it back */
1686             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1687                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
1689             /* Get SrcDestCidx PaRAM Set entry */
1690             srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1691                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
1693             srcDstCidx &= 0xFFFFU;
1694             /* Update it */
1695             srcDstCidx |= (((uint32_t)destCIdx & (uint32_t)0xFFFF) << 16U);
1697             /* Store it back */
1698             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1699                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
1700             }
1701         }
1703 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1704     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1705                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1706                 EDMA3_DVT_dCOUNTER,
1707                 EDMA3_DVT_dNONE,
1708                 EDMA3_DVT_dNONE));
1709 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1711     return result;
1712     }
1714 EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
1715         uint32_t lCh, uint32_t aCnt, uint32_t bCnt, uint32_t cCnt,
1716         uint32_t bCntReload, EDMA3_DRV_SyncType syncType)
1717     {
1718     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1719     uint32_t abCnt = 0;
1720     uint32_t linkBCntReld = 0;
1721     uint32_t opt = 0;
1722     EDMA3_DRV_Instance *drvInst = NULL;
1723     EDMA3_DRV_Object *drvObject = NULL;
1724     int32_t paRAMId = 0;
1725     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1726         uint32_t edma3Id;
1728 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1729     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1730                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1731                 EDMA3_DVT_dCOUNTER,
1732                 EDMA3_DVT_dNONE,
1733                 EDMA3_DVT_dNONE));
1734 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1736         /* If parameter checking is enabled... */
1737 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1738     if (hEdma == NULL)
1739         {
1740         result = EDMA3_DRV_E_INVALID_PARAM;
1741         }
1743     if ((((aCnt > EDMA3_DRV_ACNT_MAX_VAL)
1744         || (bCnt > EDMA3_DRV_BCNT_MAX_VAL))
1745         || ((cCnt > EDMA3_DRV_CCNT_MAX_VAL)
1746         || (bCntReload > EDMA3_DRV_BCNTRELD_MAX_VAL)))
1747         || (((int32_t)syncType < (int32_t)EDMA3_DRV_SYNC_A) || (syncType > EDMA3_DRV_SYNC_AB)))
1748         {
1749         result = EDMA3_DRV_E_INVALID_PARAM;
1750         }
1751 #endif
1753         /* Check if the parameters are OK. */
1754         if (EDMA3_DRV_SOK == result)
1755         {
1756         drvInst = (EDMA3_DRV_Instance *)hEdma;
1757         drvObject = drvInst->pDrvObjectHandle;
1759         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1760             {
1761             result =  EDMA3_DRV_E_INVALID_PARAM;
1762             }
1763         else
1764             {
1765             edma3Id = drvObject->phyCtrllerInstId;
1766             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1767                 }
1768                 }
1770         if (EDMA3_DRV_SOK == result)
1771     {
1772         /* If parameter checking is enabled... */
1773 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1774     if (lCh > edma3_log_ch_max_val [edma3Id])
1775         {
1776         result = EDMA3_DRV_E_INVALID_PARAM;
1777         }
1778 #endif
1779     }
1781         if (EDMA3_DRV_SOK == result)
1782         {
1783         paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1784         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1785             {
1786             result = EDMA3_DRV_E_INVALID_PARAM;
1787             }
1788                 else
1789                 {
1790                 abCnt = aCnt | ((bCnt&0xFFFFU) << 16U);
1792             /* Set aCnt and bCnt */
1793             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1794                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;
1796             /* Set cCnt */
1797             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1798                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;
1801             linkBCntReld = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1802                                                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
1804             linkBCntReld |= ((bCntReload & 0xFFFFU) << 16U);
1806             /* Set bCntReload */
1807             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1808                         + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;
1810             opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1812             /* Set Sync Type */
1813             opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK;
1814             opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK(syncType);
1816             *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1817             }
1818         }
1820 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1821     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1822                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1823                 EDMA3_DVT_dCOUNTER,
1824                 EDMA3_DVT_dNONE,
1825                 EDMA3_DVT_dNONE));
1826 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1828     return result;
1829     }
1831 EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
1832                                         uint32_t lCh,
1833                                         EDMA3_DRV_TrigMode trigMode)
1834     {
1835     EDMA3_DRV_Instance *drvInst = NULL;
1836     EDMA3_DRV_Object *drvObject = NULL;
1837     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1838     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1839         uint32_t edma3Id;
1841 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1842     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1843                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1844                 EDMA3_DVT_dCOUNTER,
1845                 EDMA3_DVT_dNONE,
1846                 EDMA3_DVT_dNONE));
1847 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1849         /* If parameter checking is enabled... */
1850 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1851     if (hEdma == NULL)
1852         {
1853         result = EDMA3_DRV_E_INVALID_PARAM;
1854         }
1855 #endif
1857         if (EDMA3_DRV_SOK == result)
1858         {
1859         drvInst = (EDMA3_DRV_Instance *)hEdma;
1860         drvObject = drvInst->pDrvObjectHandle;
1862         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1863             {
1864             result = EDMA3_DRV_E_INVALID_PARAM;
1865             }
1866         else
1867             {
1868             edma3Id = drvObject->phyCtrllerInstId;
1869             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1870                 }
1871                 }
1873     if (EDMA3_DRV_SOK == result)
1874         {
1875         /* If parameter checking is enabled... */
1876 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1877     if (lCh > edma3_log_ch_max_val [edma3Id])
1878         {
1879         result = EDMA3_DRV_E_INVALID_PARAM;
1880         }
1882     /* Trigger type is Manual */
1883     if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
1884         && (lCh > edma3_dma_ch_max_val [edma3Id]))
1885         {
1886         /* Channel Id lies outside DMA channel range */
1887         result = EDMA3_DRV_E_INVALID_PARAM;
1888         }
1890     /* Trigger type is QDMA */
1891     if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
1892         && ((lCh < edma3_qdma_ch_min_val[edma3Id])
1893         || (lCh > edma3_qdma_ch_max_val[edma3Id])))
1894         {
1895         /* Channel Id lies outside QDMA channel range */
1896         result = EDMA3_DRV_E_INVALID_PARAM;
1897         }
1899         /* Trigger type is Event */
1900     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
1901         && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
1902          & ((uint32_t)1U<<(lCh%32U))) == FALSE))
1903         {
1904         /* Channel was not mapped to any Hw Event. */
1905         result = EDMA3_DRV_E_INVALID_PARAM;
1906         }
1907 #endif
1908         }
1909                 
1910         if (EDMA3_DRV_SOK == result)
1911         {
1912         switch (trigMode)
1913             {
1914             case EDMA3_DRV_TRIG_MODE_MANUAL :
1915                 {
1916                 if (lCh < 32U)
1917                     {
1918                     drvInst->shadowRegs->ESR = (1UL << lCh);
1919                     }
1920                 else
1921                     {
1922                     drvInst->shadowRegs->ESRH = (1UL << (lCh-32U));
1923                     }
1924                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1925                                                                                                         EDMA3_DRV_TRIG_MODE_MANUAL;
1926                 }
1927                 break;
1929             case EDMA3_DRV_TRIG_MODE_QDMA :
1930                 {
1931                 drvInst->shadowRegs->QEESR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
1932                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1933                                                                                                                 EDMA3_DRV_TRIG_MODE_QDMA;
1934                 }
1935                 break;
1937             case EDMA3_DRV_TRIG_MODE_EVENT :
1938                 {
1939                 if (lCh < 32U)
1940                    {
1941                     /*clear SECR to clean any previous NULL request */
1942                     drvInst->shadowRegs->SECR = (1UL << lCh);
1944                     /*clear EMCR to clean any previous NULL request */
1945                     globalRegs->EMCR = (1UL << lCh);
1947                     drvInst->shadowRegs->EESR = (1UL << lCh);
1948                     }
1949                 else
1950                     {
1951                     /*clear SECR to clean any previous NULL request */
1952                     drvInst->shadowRegs->SECRH = (1UL << (lCh-32U));
1954                     /*clear EMCR to clean any previous NULL request */
1955                     globalRegs->EMCRH = (1UL << (lCh-32U));
1957                     drvInst->shadowRegs->EESRH = (1UL << (lCh-32U));
1958                     }
1960                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1961                                                                                                                 EDMA3_DRV_TRIG_MODE_EVENT;
1962                 }
1963                 break;
1965             default :
1966                 result = EDMA3_DRV_E_INVALID_PARAM;
1967                 break;
1968             }
1969         }
1971 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1972         EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1973                     EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1974                     EDMA3_DVT_dCOUNTER,
1975                     EDMA3_DVT_dNONE,
1976                     EDMA3_DVT_dNONE));
1977 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1979     return result;
1980     }
1982 EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
1983                                 uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
1985     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1986     EDMA3_DRV_Instance *drvInst = NULL;
1987     EDMA3_DRV_Object *drvObject = NULL;
1988     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1989         uint32_t edma3Id;
1991 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1992     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1993                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1994                 EDMA3_DVT_dCOUNTER,
1995                 EDMA3_DVT_dNONE,
1996                 EDMA3_DVT_dNONE));
1997 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1999         /* If parameter checking is enabled... */
2000 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2001     if (hEdma == NULL)
2002         {
2003         result = EDMA3_DRV_E_INVALID_PARAM;
2004         }
2005 #endif
2007         /* Check if the parameters are OK. */
2008         if (EDMA3_DRV_SOK == result)
2009         {
2010         drvInst = (EDMA3_DRV_Instance *)hEdma;
2011         drvObject = drvInst->pDrvObjectHandle;
2013         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
2014             {
2015             result = EDMA3_DRV_E_INVALID_PARAM;
2016             }
2017         else
2018             {
2019             edma3Id = drvObject->phyCtrllerInstId;
2020             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
2021                 }
2022                 }
2023         if (EDMA3_DRV_SOK == result)
2024         {
2025         /* If parameter checking is enabled... */
2026 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2027     if (lCh > edma3_log_ch_max_val [edma3Id])
2028         {
2029         result = EDMA3_DRV_E_INVALID_PARAM;
2030         }
2032     /* Trigger type is Manual */
2033     if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
2034         && (lCh > edma3_dma_ch_max_val [edma3Id]))
2035         {
2036         /* Channel Id lies outside DMA channel range */
2037         result = EDMA3_DRV_E_INVALID_PARAM;
2038         }
2040     /* Trigger type is QDMA */
2041     if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
2042         && ((lCh < edma3_qdma_ch_min_val[edma3Id])
2043         || (lCh > edma3_qdma_ch_max_val[edma3Id])))
2044         {
2045         /* Channel Id lies outside QDMA channel range */
2046         result = EDMA3_DRV_E_INVALID_PARAM;
2047         }
2049         /* Trigger type is Event */
2050     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
2051         && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
2052          & ((uint32_t)1U<<(lCh%32U))) == FALSE))
2053         {
2054         /* Channel was not mapped to any Hw Event. */
2055         result = EDMA3_DRV_E_INVALID_PARAM;
2056         }
2057 #endif
2058         }
2059                 
2060         if (EDMA3_DRV_SOK == result)
2061         {
2062         switch (trigMode)
2063             {
2064             case EDMA3_DRV_TRIG_MODE_MANUAL :
2065                 {
2066                 if (lCh < 32U)
2067                     {
2068                     if((drvInst->shadowRegs->SER & ((uint32_t)1U<<lCh))!=FALSE)
2069                         {
2070                         drvInst->shadowRegs->SECR = (1U<<lCh);
2071                         }
2072                     if((globalRegs->EMR & ((uint32_t)1U<<lCh))!=FALSE)
2073                         {
2074                         globalRegs->EMCR = (1U<<lCh);
2075                         }
2076                     }
2077                 else
2078                     {
2079                     if((drvInst->shadowRegs->SERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2080                         {
2081                         drvInst->shadowRegs->SECRH = (1U<<(lCh-32U));
2082                         }
2084                     if((globalRegs->EMRH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2085                         {
2086                         globalRegs->EMCRH = (1U<<(lCh-32U));
2087                         }
2088                     }
2089                 }
2090                 break;
2092             case EDMA3_DRV_TRIG_MODE_QDMA :
2093                 {
2094                 drvInst->shadowRegs->QEECR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
2095                 }
2096                 break;
2098             case EDMA3_DRV_TRIG_MODE_EVENT :
2099                 {
2100                 if (lCh < 32U)
2101                     {
2102                     drvInst->shadowRegs->EECR = (1U << lCh);
2104                     if((drvInst->shadowRegs->ER & ((uint32_t)1U<<lCh))!=FALSE)
2105                         {
2106                         drvInst->shadowRegs->ECR = (1U<<lCh);
2107                         }
2108                     if((drvInst->shadowRegs->SER & ((uint32_t)1U<<lCh))!=FALSE)
2109                         {
2110                         drvInst->shadowRegs->SECR = (1U<<lCh);
2111                         }
2112                     if((globalRegs->EMR & ((uint32_t)1U<<lCh))!=FALSE)
2113                         {
2114                         globalRegs->EMCR = (1U<<lCh);
2115                         }
2116                     }
2117                 else
2118                     {
2119                     drvInst->shadowRegs->EECRH = (1U << (lCh-32U));
2120                     if((drvInst->shadowRegs->ERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2121                         {
2122                         drvInst->shadowRegs->ECRH = (1U<<(lCh-32U));
2123                         }
2125                     if((drvInst->shadowRegs->SERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2126                         {
2127                         drvInst->shadowRegs->SECRH = (1U<<(lCh-32U));
2128                         }
2130                     if((globalRegs->EMRH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
2131                         {
2132                         globalRegs->EMCRH = (1U<<(lCh-32U));
2133                         }
2134                     }
2135                 }
2136                 break;
2138             default :
2139                 result = EDMA3_DRV_E_INVALID_PARAM;
2140                 break;
2141             }
2142         }
2144 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2145     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2146                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
2147                 EDMA3_DVT_dCOUNTER,
2148                 EDMA3_DVT_dNONE,
2149                 EDMA3_DVT_dNONE));
2150 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2152     return result;
2153     }
2155 EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
2156                                 uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
2158     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
2159     EDMA3_DRV_Instance *drvInst = NULL;
2160     EDMA3_DRV_Object *drvObject = NULL;
2161         uint32_t edma3Id;
2163 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2164     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2165                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
2166                 EDMA3_DVT_dCOUNTER,
2167                 EDMA3_DVT_dNONE,
2168                 EDMA3_DVT_dNONE));
2169 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2171         /* If parameter checking is enabled... */
2172 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2173     if (hEdma == NULL)
2174         {
2175         result = EDMA3_DRV_E_INVALID_PARAM;
2176         }
2177 #endif
2179         /* Check if the parameters are OK. */
2180         if (EDMA3_DRV_SOK == result)
2181         {
2182         drvInst = (EDMA3_DRV_Instance *)hEdma;
2183         drvObject = drvInst->pDrvObjectHandle;
2185         if (drvObject == NULL)
2186             {
2187             result = EDMA3_DRV_E_INVALID_PARAM;
2188             }
2189         else
2190             {
2191             edma3Id = drvObject->phyCtrllerInstId;
2192                 }
2193                 }
2195     if (EDMA3_DRV_SOK == result)
2196         {
2197         /* If parameter checking is enabled... */
2198 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2199     if (lCh > edma3_log_ch_max_val [edma3Id])
2200         {
2201         result = EDMA3_DRV_E_INVALID_PARAM;
2202         }
2204     /* Trigger type is QDMA */
2205     if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
2206         && ((lCh < edma3_qdma_ch_min_val[edma3Id])
2207         || (lCh > edma3_qdma_ch_max_val[edma3Id])))
2208         {
2209         /* Channel Id lies outside QDMA channel range */
2210         result = EDMA3_DRV_E_INVALID_PARAM;
2211         }
2213         /* Trigger type is Event */
2214     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
2215         && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
2216          & ((uint32_t)1U<<(lCh%32U))) == FALSE))
2217         {
2218         /* Channel was not mapped to any Hw Event. */
2219         result = EDMA3_DRV_E_INVALID_PARAM;
2220         }
2221 #endif
2222         }
2223                 
2224         if (EDMA3_DRV_SOK == result)
2225         {
2226         switch (trigMode)
2227             {
2228             case EDMA3_DRV_TRIG_MODE_QDMA:
2229                 {
2230                 drvInst->shadowRegs->QEECR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
2231                 }
2232                 break;
2234             case EDMA3_DRV_TRIG_MODE_EVENT:
2235                 {
2236                 if (lCh < 32U)
2237                     {
2238                         drvInst->shadowRegs->EECR = (1U << lCh);
2239                     }
2240                 else
2241                     {
2242                         drvInst->shadowRegs->EECRH = (1U << (lCh-32U));
2243                     }
2244                 }
2245                 break;
2247             default :
2248                 result = EDMA3_DRV_E_INVALID_PARAM;
2249                 break;
2250             }
2251         }
2253 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2254     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2255                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
2256                 EDMA3_DVT_dCOUNTER,
2257                 EDMA3_DVT_dNONE,
2258                 EDMA3_DVT_dNONE));
2259 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2261     return result;
2262     }
2264 /* Definitions of Local functions - Start */
2265 /** Remove various mappings and do cleanup for DMA/QDMA channels */
2266 static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
2267                                  uint32_t channelId)
2268     {
2269         uint32_t intState=0;
2270     EDMA3_DRV_Instance *drvInst = NULL;
2271     EDMA3_DRV_Object *drvObject = NULL;
2272     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
2273     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
2274     EDMA3_RM_ResDesc channelObj;
2275         uint32_t edma3Id;
2277         assert (hEdma != NULL);
2279     drvInst = (EDMA3_DRV_Instance *)hEdma;
2280     drvObject = drvInst->pDrvObjectHandle;
2282     if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
2283         {
2284         result = EDMA3_DRV_E_INVALID_PARAM;
2285         }
2286     else
2287         {
2288         edma3Id = drvObject->phyCtrllerInstId;
2289         globalRegs = (volatile EDMA3_CCRL_Regs *)
2290                                 (drvObject->gblCfgParams.globalRegs);
2291         }
2293     if (EDMA3_DRV_SOK == result)
2294     {
2295         assert (channelId <= edma3_log_ch_max_val [edma3Id]);
2296     }
2298     if (EDMA3_DRV_SOK == result)
2299     {
2301     /**
2302      * Disable any ongoing transfer on the channel, if transfer was
2303      * enabled earlier.
2304      */
2305     if (EDMA3_DRV_TRIG_MODE_NONE !=
2306         edma3DrvChBoundRes[edma3Id][channelId].trigMode)
2307         {
2308         result = EDMA3_DRV_disableTransfer(hEdma, channelId,
2309             edma3DrvChBoundRes[edma3Id][channelId].trigMode);
2310         }
2311     }
2312         
2313     if (EDMA3_DRV_SOK == result)
2314         {
2315         /*
2316         * Unregister the TCC Callback function and disable the interrupts.
2317         */
2318         if (channelId < drvObject->gblCfgParams.numDmaChannels)
2319             {
2320             /* DMA channel */
2321             channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
2322             channelObj.resId = channelId;
2323             }
2324         else
2325             {
2326             /* QDMA channel */
2327             channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
2328             channelObj.resId = channelId - edma3_qdma_ch_min_val[edma3Id];
2329             }
2331         result = EDMA3_RM_unregisterTccCb(drvInst->resMgrInstance,
2332                     (EDMA3_RM_ResDesc *)&channelObj);
2333         }
2335     if (result == EDMA3_RM_SOK)
2336         {
2337         edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT, &intState);
2339         if (channelId <= edma3_dma_ch_max_val [edma3Id])
2340             {
2341             /* DMA channel */
2342 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
2343             /* Remove the channel to Event Queue mapping */
2344             globalRegs->DMAQNUM[channelId >> 3U] &=
2345                             EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
2346 #endif
2347             /**
2348              * If DMA channel to PaRAM Set mapping exists,
2349              * remove it too.
2350              */
2351             if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
2352                 {
2353                 globalRegs->DCHMAP[channelId] &=
2354                                         EDMA3_RM_DCH_PARAM_CLR_MASK;
2355                 }
2356             }
2357         else
2358             {
2359             /* QDMA channel */
2360 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
2361             /* Remove the channel to Event Queue mapping */
2362             globalRegs->QDMAQNUM = (globalRegs->QDMAQNUM) &
2363                 (EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-edma3_qdma_ch_min_val[edma3Id]));
2364 #endif
2365             /* Remove the channel to PARAM set mapping */
2366             /* Unmap PARAM Set Number for specified channelId */
2367             globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
2368                                         EDMA3_RM_QCH_PARAM_CLR_MASK;
2370             /* Reset the Trigger Word */
2371             globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
2372                                         EDMA3_RM_QCH_TRWORD_CLR_MASK;
2373             }
2375         edma3OsProtectExit(edma3Id,
2376                                                         (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
2377                                                         intState);
2378         }
2380     return result;
2381     }
2382 uint32_t EDMA3_DRV_getVersion (void)
2384     return EDMA3_LLD_DRV_VERSION_ID;
2387 const char* EDMA3_DRV_getVersionStr (void)
2389     return edma3LldVersionStr;
2391 /* Definitions of Local functions - End */
2393 /* End of File */