1 /*
2 * edma3_drv_basic.c
3 *
4 * EDMA3 Driver Basic Interface Implementation. This file contains
5 * beginner-level EDMA3 Driver APIs which are required to:
6 * a) Request/free a DMA, QDMA and Link channel.
7 * b) Program various fields in the PaRAM Set like source/destination
8 * parameters, transfer parameters etc.
9 * c) Enable/disable a transfer.
10 * These APIs are provided to program a DMA/QDMA channel for simple use-cases
11 * and don't expose all the features of EDMA3 hardware. Users who want to go
12 * beyond this and have complete control on the EDMA3 hardware are advised
13 * to refer edma3_drv_adv.c source file.
14 *
15 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
16 *
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 *
22 * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 *
25 * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the
28 * distribution.
29 *
30 * Neither the name of Texas Instruments Incorporated nor the names of
31 * its contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
48 /* EDMa3 Driver Internal Header Files */
49 #include <ti/sdo/edma3/drv/src/edma3.h>
50 /* Resource Manager Internal Header Files */
51 #include <ti/sdo/edma3/rm/src/edma3resmgr.h>
53 /* Instrumentation Header File */
54 #ifdef EDMA3_INSTRUMENTATION_ENABLED
55 #include <ti/sdo/edma3/rm/src/edma3_log.h>
56 #endif
58 /* For assert() */
59 /**
60 * Define NDEBUG to ignore assert().
61 * NDEBUG should be defined before including assert.h header file.
62 */
63 #include <assert.h>
66 /* Externel Variables */
67 /*---------------------------------------------------------------------------*/
68 /**
69 * Maximum Resource Manager Instances supported by the EDMA3 Package.
70 */
71 extern const uint32_t EDMA3_MAX_RM_INSTANCES;
74 /**
75 * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
76 *
77 * Typically one RM object will cater to one EDMA3 HW controller
78 * and will have all the global config information.
79 */
80 extern EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
83 /**
84 * \brief Region Specific Configuration structure for
85 * EDMA3 controller, to provide region specific Information.
86 *
87 * This configuration info can also be provided by the user at run-time,
88 * while calling EDMA3_RM_open (). If not provided at run-time,
89 * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
90 * for the specified platform.
91 */
92 #ifdef BUILD_C6XDSP
93 extern far EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
94 #else
95 extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
96 #endif
98 /**
99 * Handles of EDMA3 Resource Manager Instances.
100 *
101 * Used to maintain information of the EDMA3 RM Instances
102 * for each HW controller.
103 * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per
104 * EDMA3 HW.
105 */
106 #ifdef BUILD_C6XDSP
107 extern far EDMA3_RM_Instance *ptrRMIArray;
108 #else
109 extern EDMA3_RM_Instance *ptrRMIArray;
110 #endif
112 /** Local MemSet function */
113 extern void edma3MemZero(void *dst, uint32_t len);
114 /** Local MemCpy function */
115 extern void edma3MemCpy(void *dst, const void *src, uint32_t len);
117 /**
118 * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
119 *
120 * Typically one object will cater to one EDMA3 HW controller
121 * and will have all regions' (ARM, DSP etc) specific config information.
122 */
123 extern EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES];
126 /**
127 * Handles of EDMA3 Driver Instances.
128 *
129 * Used to maintain information of the EDMA3 Driver Instances for
130 * each region, for each HW controller.
131 * There could be as many Driver Instances as there are shadow
132 * regions. Multiple EDMA3 Driver instances on the same shadow
133 * region are NOT allowed.
134 */
135 extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
138 /**
139 * \brief Resources bound to a Channel
140 *
141 * When a request for a channel is made, the resources PaRAM Set and TCC
142 * get bound to that channel. This information is needed internally by the
143 * driver when a request is made to free the channel (Since it is the
144 * responsibility of the driver to free up the channel-associated resources
145 * from the Resource Manager layer).
146 */
147 extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
149 /** Max of DMA Channels */
150 extern uint32_t edma3_dma_ch_max_val[];
151 /** Min of Link Channels */
152 extern uint32_t edma3_link_ch_min_val[];
153 /** Max of Link Channels */
154 extern uint32_t edma3_link_ch_max_val[];
155 /** Min of QDMA Channels */
156 extern uint32_t edma3_qdma_ch_min_val[];
157 /** Max of QDMA Channels */
158 extern uint32_t edma3_qdma_ch_max_val[];
159 /** Max of Logical Channels */
160 extern uint32_t edma3_log_ch_max_val[];
162 /* Local functions prototypes */
163 /*---------------------------------------------------------------------------*/
164 /** Remove various mappings and do cleanup for DMA/QDMA channels */
165 static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
166 uint32_t channelId);
168 /** @brief Global Variable which describes the EDMA3 LLD Version Information */
169 const char edma3LldVersionStr[] = EDMA3_LLD_DRV_VERSION_STR ":" __DATE__ ":" __TIME__;
170 /*---------------------------------------------------------------------------*/
172 EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
173 uint32_t *pLCh,
174 uint32_t *pTcc,
175 EDMA3_RM_EventQueue evtQueue,
176 EDMA3_RM_TccCallback tccCb,
177 void *cbData)
178 {
179 EDMA3_RM_ResDesc resObj;
180 EDMA3_RM_ResDesc channelObj;
181 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
182 EDMA3_DRV_Instance *drvInst = NULL;
183 EDMA3_DRV_Object *drvObject = NULL;
184 uint32_t mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP;
185 int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
186 EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
187 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
188 int32_t mappedPaRAMId;
189 uint32_t edma3Id;
190 uint32_t freeDmaQdmaChannel = FALSE;
191 uint32_t mapXbarEvtToChanFlag = FALSE;
192 uint32_t xBarEvtBeforeMap = 0;
194 #ifdef EDMA3_INSTRUMENTATION_ENABLED
195 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
196 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
197 EDMA3_DVT_dCOUNTER,
198 EDMA3_DVT_dNONE,
199 EDMA3_DVT_dNONE));
200 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
203 /* If parameter checking is enabled... */
204 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
205 if ((pLCh == NULL) || (hEdma == NULL))
206 {
207 result = EDMA3_DRV_E_INVALID_PARAM;
208 }
209 #endif
211 if (EDMA3_DRV_SOK == result)
212 {
213 drvInst = (EDMA3_DRV_Instance *)hEdma;
214 drvObject = drvInst->pDrvObjectHandle;
216 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
217 {
218 result = EDMA3_DRV_E_INVALID_PARAM;
219 }
220 }
222 if ( drvInst->mapXbarToChan != NULL)
223 {
224 xBarEvtBeforeMap = *pLCh;
225 edma3Id = drvObject->phyCtrllerInstId;
226 if ((xBarEvtBeforeMap > edma3_dma_ch_max_val [edma3Id]) &&
227 (xBarEvtBeforeMap < EDMA3_DRV_DMA_CHANNEL_ANY) &&
228 ((*pLCh) == (*pTcc)))
229 {
230 result = drvInst->mapXbarToChan(xBarEvtBeforeMap,
231 pLCh,
232 &drvInst->drvXbarToEvtMapConfig);
233 if (EDMA3_DRV_SOK == result)
234 {
235 *pTcc = *pLCh;
236 mapXbarEvtToChanFlag = TRUE;
237 }
238 }
239 }
241 if (EDMA3_DRV_SOK == result)
242 {
243 edma3Id = drvObject->phyCtrllerInstId;
244 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
246 /* Identify the request type and validate the appropriate arguments.
247 * Starting in the order of PaRAM Set availability,
248 * check for a specific DMA channel request first.
249 */
250 if ((*pLCh) <= edma3_dma_ch_max_val [edma3Id])
251 {
252 /* A 'Specific' DMA channel is requested */
253 chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
254 /* Fill the resObj structure as well */
255 resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
256 resObj.resId = *pLCh;
258 /* Check the TCC and Event Queue number */
259 if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
260 || (pTcc == NULL))
261 {
262 result = EDMA3_DRV_E_INVALID_PARAM;
263 }
264 }
266 if ((*pLCh) == EDMA3_DRV_DMA_CHANNEL_ANY)
267 {
268 /* 'Any' DMA channel is requested */
269 chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
270 resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
271 resObj.resId = EDMA3_RM_RES_ANY;
273 /* Check the TCC and Event Queue number */
274 if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
275 || (pTcc == NULL))
276 {
277 result = EDMA3_DRV_E_INVALID_PARAM;
278 }
279 }
281 if (((*pLCh) >= edma3_link_ch_min_val[edma3Id]) &&
282 ((*pLCh) <= edma3_link_ch_max_val[edma3Id]))
283 {
284 /* A 'Specific' Link channel is requested, TCC may or may not be
285 * required.
286 */
287 /* Save the PaRAM Id for future use */
288 paRAMId = *pLCh;
290 if (pTcc != NULL)
291 {
292 if (*pTcc < drvObject->gblCfgParams.numTccs)
293 {
294 /* Argument passed as *pTcc is a valid TCC number */
295 chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
296 resObj.type = EDMA3_RM_RES_PARAM_SET;
297 }
298 else
299 {
300 /* Argument passed as *pTcc is Invalid TCC number */
301 result = EDMA3_DRV_E_INVALID_PARAM;
302 }
303 }
304 else
305 {
306 /* pTcc is NULL, only Link Channel required */
307 chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
308 resObj.type = EDMA3_RM_RES_PARAM_SET;
309 }
310 }
312 if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)
313 {
314 /* 'Any' Link channel is requested, TCC is not required */
315 chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
316 resObj.type = EDMA3_RM_RES_PARAM_SET;
317 }
319 if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL_WITH_TCC)
320 {
321 if (pTcc != NULL)
322 {
323 /* 'Any' Link channel is requested, TCC is required */
324 if (*pTcc < drvObject->gblCfgParams.numTccs)
325 {
326 /* Argument passed as *pTcc is a valid TCC number */
327 chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
328 resObj.type = EDMA3_RM_RES_PARAM_SET;
329 }
330 else
331 {
332 /* Argument passed as *pTcc is Invalid TCC number */
333 result = EDMA3_DRV_E_INVALID_PARAM;
334 }
335 }
336 else
337 {
338 /* pTcc is NULL */
339 result = EDMA3_DRV_E_INVALID_PARAM;
340 }
341 }
343 if (((*pLCh) >= EDMA3_DRV_QDMA_CHANNEL_0) &&
344 ((*pLCh) <= EDMA3_DRV_QDMA_CHANNEL_7))
345 {
346 /* A 'Specific' QDMA channel is requested */
347 chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
348 resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
349 resObj.resId = *pLCh - EDMA3_DRV_QDMA_CHANNEL_0;
351 /* Check the TCC and Event Queue number */
352 if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
353 || (pTcc == NULL))
354 {
355 result = EDMA3_DRV_E_INVALID_PARAM;
356 }
357 }
359 if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY)
360 {
361 /* 'Any' QDMA channel is requested */
362 chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
363 resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
364 resObj.resId = EDMA3_RM_RES_ANY;
366 /* Check the TCC and Event Queue number */
367 if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
368 || (pTcc == NULL))
369 {
370 result = EDMA3_DRV_E_INVALID_PARAM;
371 }
372 }
374 if (EDMA3_DRV_CHANNEL_TYPE_NONE == chType)
375 {
376 /* Invalid request */
377 result = EDMA3_DRV_E_INVALID_PARAM;
378 }
379 }
381 /* Step 1: Allocate the DMA/QDMA channel first, if required */
382 if (EDMA3_DRV_SOK == result)
383 {
384 switch (chType)
385 {
386 case EDMA3_DRV_CHANNEL_TYPE_DMA:
387 result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
388 (EDMA3_RM_ResDesc *)&resObj);
389 if (result == EDMA3_RM_SOK)
390 {
391 *pLCh = resObj.resId;
393 mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
394 if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP)
395 {
396 paRAMId = mappedPaRAMId;
397 }
399 if (*pTcc == EDMA3_DRV_TCC_ANY)
400 {
401 mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];
402 if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP)
403 {
404 mappedTcc = EDMA3_RM_RES_ANY;
405 }
406 }
407 else
408 {
409 mappedTcc = *pTcc;
410 }
412 /* Save the Resource Type/ID for TCC registeration */
413 channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
414 channelObj.resId = *pLCh;
416 /* Free DMA channel in case the function fails in future */
417 freeDmaQdmaChannel = TRUE;
418 }
419 else
420 {
421 result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;
422 }
424 break;
426 case EDMA3_DRV_CHANNEL_TYPE_QDMA:
427 result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
428 (EDMA3_RM_ResDesc *)&resObj);
429 if (result == EDMA3_DRV_SOK)
430 {
431 (*pLCh) = resObj.resId + edma3_qdma_ch_min_val[edma3Id];
433 if (*pTcc == EDMA3_DRV_TCC_ANY)
434 {
435 mappedTcc = EDMA3_RM_RES_ANY;
436 }
437 else
438 {
439 mappedTcc = *pTcc;
440 }
442 /* Save the Resource Type/ID for TCC registeration */
443 channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
444 channelObj.resId = resObj.resId;
446 /* Free DMA channel in case the function fails in future */
447 freeDmaQdmaChannel = TRUE;
448 }
449 else
450 {
451 result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
452 }
453 break;
455 default:
456 break;
457 }
458 }
460 /* Step 2: Allocate the PaRAM Set */
461 if (EDMA3_DRV_SOK == result)
462 {
463 resObj.type = EDMA3_RM_RES_PARAM_SET;
464 resObj.resId = (uint32_t)paRAMId;
465 result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
466 }
468 if (EDMA3_DRV_SOK == result)
469 {
470 paRAMId = (int32_t)resObj.resId;
472 if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
473 {
474 /* Link channel number should be same as the PaRAM Set */
475 *pLCh = resObj.resId;
476 edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
477 edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
478 }
480 if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK_TCC)
481 {
482 /* Link channel number should be same as the PaRAM Set */
483 *pLCh = resObj.resId;
484 edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
485 edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
487 /* save the tcc now */
488 edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
490 /* Set TCC in ParamSet.OPT field */
491 globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;
492 globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
493 }
494 }
495 else
496 {
497 /* PaRAM allocation failed, free the previously allocated DMA/QDMA
498 * channel, if required
499 */
500 if ((chType == EDMA3_DRV_CHANNEL_TYPE_DMA
501 || chType == EDMA3_DRV_CHANNEL_TYPE_QDMA) &&
502 (TRUE == freeDmaQdmaChannel))
503 {
504 EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
505 }
506 }
508 /* Step 3: Allocate TCC only for DMA/QDMA channels */
509 if ((EDMA3_DRV_SOK == result) &&
510 (chType == EDMA3_DRV_CHANNEL_TYPE_DMA || chType == EDMA3_DRV_CHANNEL_TYPE_QDMA))
511 {
512 resObj.type = EDMA3_RM_RES_TCC;
513 resObj.resId = mappedTcc;
514 result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
516 if (EDMA3_DRV_SOK == result)
517 {
518 *pTcc = resObj.resId;
520 /* Save TCC and PaRAM set */
521 edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
522 edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
524 switch (chType)
525 {
526 case EDMA3_DRV_CHANNEL_TYPE_DMA:
527 {
528 /* Step 4: Register the callback function, if required */
529 if (NULL != tccCb)
530 {
531 result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
532 (EDMA3_RM_ResDesc *)&channelObj,
533 *pTcc, tccCb, cbData);
534 }
535 if (result != EDMA3_DRV_SOK)
536 {
537 EDMA3_DRV_freeChannel (hEdma, *pLCh);
538 result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
539 }
540 else
541 {
542 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
543 uint32_t intState = 0;
544 edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
545 &intState);
546 /* Step 5: Associate DMA Channel to Event Queue */
547 globalRegs->DMAQNUM[(*pLCh) >> 3u] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
548 globalRegs->DMAQNUM[(*pLCh) >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh), evtQueue);
550 edma3OsProtectExit(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
551 intState);
552 #endif
554 /* Step 6: Map PaRAM Set to DMA Channel */
555 if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
556 {
557 globalRegs->DCHMAP[*pLCh] &= EDMA3_DRV_DCH_PARAM_CLR_MASK;
558 globalRegs->DCHMAP[*pLCh] |= EDMA3_DRV_DCH_PARAM_SET_MASK(paRAMId);
559 }
561 /* Step 7: Set TCC in ParamSet.OPT field */
562 globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;
563 globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
565 edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
566 }
567 }
568 break;
570 case EDMA3_DRV_CHANNEL_TYPE_QDMA:
571 {
572 uint32_t qdmaChannel = channelObj.resId;
574 /* Step 4: Register the callback function, if required */
575 if (NULL != tccCb)
576 {
577 result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
578 (EDMA3_RM_ResDesc *)&channelObj,
579 *pTcc, tccCb, cbData);
580 }
581 if (result != EDMA3_DRV_SOK)
582 {
583 EDMA3_DRV_freeChannel (hEdma, *pLCh);
584 result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
585 }
586 else
587 {
588 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
589 uint32_t intState = 0;
590 edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
591 &intState);
592 /* Step 5: Associate QDMA Channel to Event Queue */
593 globalRegs->QDMAQNUM &= EDMA3_DRV_QDMAQNUM_CLR_MASK(qdmaChannel);
594 globalRegs->QDMAQNUM |= EDMA3_DRV_QDMAQNUM_SET_MASK(qdmaChannel, evtQueue);
596 edma3OsProtectExit(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
597 intState);
598 #endif
600 /* Step 6: Map PaRAM Set to DMA Channel and set the Default Trigger Word */
601 globalRegs->QCHMAP[qdmaChannel] &= EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK;
602 globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_PARAM_SET_MASK(paRAMId);
603 globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT);
605 /* Step 7: Set TCC in ParamSet.OPT field */
606 globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;
607 globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
609 edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
611 /* Step 8: Enable the QDMA Channel */
612 drvInst->shadowRegs->QEESR = 1u << qdmaChannel;
613 }
614 }
615 break;
616 default:
617 break;
618 }
619 }
620 else
621 {
622 /* TCC allocation failed, free the PaRAM Set, */
623 resObj.type = EDMA3_RM_RES_PARAM_SET;
624 resObj.resId = (uint32_t)paRAMId;
625 EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
627 /* And free the DMA/QDMA channel */
628 EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
630 result = EDMA3_DRV_E_TCC_UNAVAIL;
631 }
632 }
633 if ((drvInst->configScrMapXbarToEvt != NULL) &&
634 (mapXbarEvtToChanFlag == TRUE))
635 {
636 drvInst->configScrMapXbarToEvt(xBarEvtBeforeMap, *pLCh);
637 }
639 #ifdef EDMA3_INSTRUMENTATION_ENABLED
640 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
641 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
642 EDMA3_DVT_dCOUNTER,
643 EDMA3_DVT_dNONE,
644 EDMA3_DVT_dNONE));
645 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
647 return result;
648 }
650 EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
651 uint32_t channelId)
652 {
653 EDMA3_RM_ResDesc resObj;
654 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
655 EDMA3_DRV_Instance *drvInst = NULL;
656 EDMA3_DRV_Object *drvObject = NULL;
657 int32_t paRAMId;
658 uint32_t tcc;
659 EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
660 uint32_t edma3Id;
662 #ifdef EDMA3_INSTRUMENTATION_ENABLED
663 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
664 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
665 EDMA3_DVT_dCOUNTER,
666 EDMA3_DVT_dNONE,
667 EDMA3_DVT_dNONE));
668 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
670 /* If parameter checking is enabled... */
671 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
672 if (hEdma == NULL)
673 {
674 result = EDMA3_DRV_E_INVALID_PARAM;
675 }
676 #endif
678 if (EDMA3_DRV_SOK == result)
679 {
680 drvInst = (EDMA3_DRV_Instance *)hEdma;
681 drvObject = drvInst->pDrvObjectHandle;
683 if (drvObject == NULL)
684 {
685 result = EDMA3_DRV_E_INVALID_PARAM;
686 }
687 else
688 {
689 edma3Id = drvObject->phyCtrllerInstId;
690 }
691 }
693 if (EDMA3_DRV_SOK == result)
694 {
695 /* Check the channel type */
696 if (channelId <= edma3_dma_ch_max_val [edma3Id])
697 {
698 /* DMA Channel */
699 chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
700 }
702 if ((channelId >= edma3_link_ch_min_val[edma3Id])
703 && (channelId <= edma3_link_ch_max_val[edma3Id]))
704 {
705 /* LINK Channel */
706 chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
707 }
709 if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
710 && (channelId <= edma3_qdma_ch_max_val[edma3Id]))
711 {
712 /* QDMA Channel */
713 chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
714 }
716 if (chType == EDMA3_DRV_CHANNEL_TYPE_NONE)
717 {
718 result = EDMA3_DRV_E_INVALID_PARAM;
719 }
720 }
723 if (EDMA3_DRV_SOK == result)
724 {
725 if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
726 {
727 /* LINK Channel */
728 resObj.type = EDMA3_RM_RES_PARAM_SET;
730 /* Get the PaRAM id from the book-keeping info. */
731 resObj.resId = (uint32_t)(edma3DrvChBoundRes[edma3Id][channelId].paRAMId);
733 result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
734 (EDMA3_RM_ResDesc *)&resObj);
736 if (EDMA3_DRV_SOK == result)
737 {
738 edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
739 }
740 }
741 else
742 {
743 /* DMA/QDMA Channel */
744 paRAMId = edma3DrvChBoundRes[edma3Id][channelId].paRAMId;
745 tcc = edma3DrvChBoundRes[edma3Id][channelId].tcc;
747 /* Check the paRAMId and tcc values first */
748 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
749 {
750 result = EDMA3_DRV_E_INVALID_PARAM;
751 }
753 if (tcc >= drvObject->gblCfgParams.numTccs)
754 {
755 result = EDMA3_DRV_E_INVALID_PARAM;
756 }
758 if (EDMA3_DRV_SOK == result)
759 {
760 /* Disable the transfer and remove various mappings. */
761 result = edma3RemoveMapping(hEdma, channelId);
762 }
764 if (EDMA3_DRV_SOK == result)
765 {
766 /* Now Free the PARAM set and TCC */
767 resObj.type = EDMA3_RM_RES_PARAM_SET;
768 resObj.resId = (uint32_t)paRAMId;
769 result = EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
771 if (EDMA3_DRV_SOK == result)
772 {
773 /* PaRAM Set Freed */
774 edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
776 /* Free the TCC */
777 resObj.type = EDMA3_RM_RES_TCC;
778 resObj.resId = tcc;
779 result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
780 (EDMA3_RM_ResDesc *)&resObj);
781 }
783 if (EDMA3_DRV_SOK == result)
784 {
785 /* TCC Freed. */
786 edma3DrvChBoundRes[edma3Id][channelId].tcc = EDMA3_MAX_TCC;
788 /* Now free the DMA/QDMA Channel in the end. */
789 if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)
790 {
791 resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
792 resObj.resId = (channelId - edma3_qdma_ch_min_val[edma3Id]);
793 result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
794 (EDMA3_RM_ResDesc *)&resObj);
795 }
796 else
797 {
798 resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
799 resObj.resId = channelId;
800 result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
801 (EDMA3_RM_ResDesc *)&resObj);
802 }
803 }
804 }
805 }
806 }
808 #ifdef EDMA3_INSTRUMENTATION_ENABLED
809 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
810 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
811 EDMA3_DVT_dCOUNTER,
812 EDMA3_DVT_dNONE,
813 EDMA3_DVT_dNONE));
814 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
816 return result;
817 }
819 EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
820 uint32_t channelId)
821 {
822 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
823 EDMA3_DRV_Instance *drvInst = NULL;
824 EDMA3_DRV_Object *drvObject = NULL;
825 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
826 uint32_t count;
827 uint32_t value = 0;
828 uint32_t edma3Id;
830 #ifdef EDMA3_INSTRUMENTATION_ENABLED
831 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
832 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
833 EDMA3_DVT_dCOUNTER,
834 EDMA3_DVT_dNONE,
835 EDMA3_DVT_dNONE));
836 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
838 /* If parameter checking is enabled... */
839 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
840 if (hEdma == NULL)
841 {
842 result = EDMA3_DRV_E_INVALID_PARAM;
843 }
844 #endif
846 /* Check if the parameters are OK. */
847 if (EDMA3_DRV_SOK == result)
848 {
849 drvInst = (EDMA3_DRV_Instance *)hEdma;
850 drvObject = drvInst->pDrvObjectHandle;
852 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
853 {
854 result = EDMA3_DRV_E_INVALID_PARAM;
855 }
856 else
857 {
858 edma3Id = drvObject->phyCtrllerInstId;
860 /* If parameter checking is enabled... */
861 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
862 if (channelId > edma3_dma_ch_max_val [edma3Id])
863 {
864 result = EDMA3_DRV_E_INVALID_PARAM;
865 }
866 #endif
868 /* Check if the parameters are OK. */
869 if (EDMA3_DRV_SOK == result)
870 {
871 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
873 #ifdef EDMA3_DRV_DEBUG
874 EDMA3_DRV_PRINTF("EMR =%l\r\n", globalRegs->EMR);
875 #endif
876 if(channelId < 32u)
877 {
878 /* Disables the DMA channels */
879 drvInst->shadowRegs->EECR = (1u << channelId);
880 /* Write to EMCR to clear the corresponding EMR bit */
881 globalRegs->EMCR = (1u << channelId);
882 /* Clears the SER */
883 drvInst->shadowRegs->SECR = (1u << channelId);
884 }
885 else
886 {
887 #ifdef EDMA3_DRV_DEBUG
888 EDMA3_DRV_PRINTF("EMRH =%l\r\n", globalRegs->EMRH);
889 #endif
890 /* Disables the DMA channels */
891 drvInst->shadowRegs->EECRH = (1u << (channelId - 32u));
892 /* Write to EMCR to clear the corresponding EMR bit */
893 globalRegs->EMCRH = (1u << (channelId - 32u));
894 /* Clears the SER */
895 drvInst->shadowRegs->SECRH = (1u << (channelId - 32u));
896 }
898 /* Clear the global CC Error Register */
899 for (count = 0; count < drvObject->gblCfgParams.numEvtQueue; count++)
900 {
901 value |= (1u << count);
902 }
904 globalRegs->CCERRCLR = (EDMA3_CCRL_CCERR_TCCERR_MASK | value);
905 }
906 }
907 }
909 #ifdef EDMA3_INSTRUMENTATION_ENABLED
910 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
911 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
912 EDMA3_DVT_dCOUNTER,
913 EDMA3_DVT_dNONE,
914 EDMA3_DVT_dNONE));
915 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
917 return result;
918 }
920 EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
921 uint32_t lCh,
922 EDMA3_DRV_OptField optField,
923 uint32_t newOptFieldVal)
924 {
925 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
926 EDMA3_DRV_Instance *drvInst = NULL;
927 EDMA3_DRV_Object *drvObject = NULL;
928 uint32_t newOptVal = 0;
929 uint32_t oldOptVal = 0;
930 int32_t paRAMId = 0;
931 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
932 uint32_t edma3Id;
934 #ifdef EDMA3_INSTRUMENTATION_ENABLED
935 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
936 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
937 EDMA3_DVT_dCOUNTER,
938 EDMA3_DVT_dNONE,
939 EDMA3_DVT_dNONE));
940 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
942 /* If parameter checking is enabled... */
943 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
944 if ((hEdma == NULL)
945 || (((int32_t)optField < (int32_t)EDMA3_DRV_OPT_FIELD_SAM)
946 || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
947 {
948 result = EDMA3_DRV_E_INVALID_PARAM;
949 }
950 #endif
952 /* Check if the parameters are OK. */
953 if (EDMA3_DRV_SOK == result)
954 {
955 drvInst = (EDMA3_DRV_Instance *)hEdma;
956 drvObject = drvInst->pDrvObjectHandle;
958 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
959 {
960 result = EDMA3_DRV_E_INVALID_PARAM;
961 }
962 else
963 {
964 edma3Id = drvObject->phyCtrllerInstId;
965 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
966 }
967 }
969 /* If parameter checking is enabled... */
970 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
971 if (lCh > edma3_log_ch_max_val [edma3Id])
972 {
973 result = EDMA3_DRV_E_INVALID_PARAM;
974 }
975 #endif
977 if (EDMA3_DRV_SOK == result)
978 {
979 paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
980 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
981 {
982 result = EDMA3_DRV_E_INVALID_PARAM;
983 }
984 }
986 if (EDMA3_DRV_SOK == result)
987 {
988 oldOptVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
990 switch (optField)
991 {
992 case EDMA3_DRV_OPT_FIELD_SAM :
993 newOptVal = (oldOptVal & EDMA3_DRV_OPT_SAM_CLR_MASK)
994 |
995 (EDMA3_DRV_OPT_SAM_SET_MASK(newOptFieldVal));
996 break;
997 case EDMA3_DRV_OPT_FIELD_DAM :
998 newOptVal = (oldOptVal & EDMA3_DRV_OPT_DAM_CLR_MASK)
999 |
1000 (EDMA3_DRV_OPT_DAM_SET_MASK(newOptFieldVal));
1001 break;
1002 case EDMA3_DRV_OPT_FIELD_SYNCDIM :
1003 newOptVal = (oldOptVal & EDMA3_DRV_OPT_SYNCDIM_CLR_MASK)
1004 |
1005 (EDMA3_DRV_OPT_SYNCDIM_SET_MASK(newOptFieldVal));
1006 break;
1007 case EDMA3_DRV_OPT_FIELD_STATIC :
1008 newOptVal = (oldOptVal & EDMA3_DRV_OPT_STATIC_CLR_MASK)
1009 |
1010 (EDMA3_DRV_OPT_STATIC_SET_MASK(newOptFieldVal));
1011 break;
1012 case EDMA3_DRV_OPT_FIELD_FWID :
1013 newOptVal = (oldOptVal & EDMA3_DRV_OPT_FWID_CLR_MASK)
1014 |
1015 (EDMA3_DRV_OPT_FWID_SET_MASK(newOptFieldVal));
1016 break;
1017 case EDMA3_DRV_OPT_FIELD_TCCMODE :
1018 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCMODE_CLR_MASK)
1019 |
1020 (EDMA3_DRV_OPT_TCCMODE_SET_MASK(newOptFieldVal));
1021 break;
1022 case EDMA3_DRV_OPT_FIELD_TCC :
1023 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
1024 |
1025 (EDMA3_DRV_OPT_TCC_SET_MASK(newOptFieldVal));
1026 break;
1027 case EDMA3_DRV_OPT_FIELD_TCINTEN :
1028 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCINTEN_CLR_MASK)
1029 |
1030 (EDMA3_DRV_OPT_TCINTEN_SET_MASK(newOptFieldVal));
1031 break;
1032 case EDMA3_DRV_OPT_FIELD_ITCINTEN :
1033 newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCINTEN_CLR_MASK)
1034 |
1035 (EDMA3_DRV_OPT_ITCINTEN_SET_MASK(newOptFieldVal));
1036 break;
1037 case EDMA3_DRV_OPT_FIELD_TCCHEN :
1038 newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCHEN_CLR_MASK)
1039 |
1040 (EDMA3_DRV_OPT_TCCHEN_SET_MASK(newOptFieldVal));
1041 break;
1042 case EDMA3_DRV_OPT_FIELD_ITCCHEN :
1043 newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCCHEN_CLR_MASK)
1044 |
1045 (EDMA3_DRV_OPT_ITCCHEN_SET_MASK(newOptFieldVal));
1046 break;
1047 default:
1048 break;
1049 }
1051 *(&globalRegs->PARAMENTRY[paRAMId].OPT) = newOptVal;
1052 }
1054 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1055 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1056 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1057 EDMA3_DVT_dCOUNTER,
1058 EDMA3_DVT_dNONE,
1059 EDMA3_DVT_dNONE));
1060 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1062 return result;
1063 }
1065 EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
1066 uint32_t lCh,
1067 EDMA3_DRV_OptField optField,
1068 uint32_t *optFieldVal)
1069 {
1070 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1071 EDMA3_DRV_Instance *drvInst = NULL;
1072 EDMA3_DRV_Object *drvObject = NULL;
1073 uint32_t optVal = 0;
1074 int32_t paRAMId = 0;
1075 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1076 uint32_t edma3Id;
1078 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1079 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1080 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1081 EDMA3_DVT_dCOUNTER,
1082 EDMA3_DVT_dNONE,
1083 EDMA3_DVT_dNONE));
1084 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1086 /* If parameter checking is enabled... */
1087 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1088 if (((hEdma == NULL) || (optFieldVal == NULL))
1089 || (((int32_t)optField < (int32_t)EDMA3_DRV_OPT_FIELD_SAM)
1090 || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
1091 {
1092 result = EDMA3_DRV_E_INVALID_PARAM;
1093 }
1094 #endif
1096 /* Check if the parameters are OK. */
1097 if (EDMA3_DRV_SOK == result)
1098 {
1099 drvInst = (EDMA3_DRV_Instance *)hEdma;
1100 drvObject = drvInst->pDrvObjectHandle;
1102 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1103 {
1104 result = EDMA3_DRV_E_INVALID_PARAM;
1105 }
1106 else
1107 {
1108 edma3Id = drvObject->phyCtrllerInstId;
1109 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1110 }
1111 }
1113 /* If parameter checking is enabled... */
1114 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1115 if (lCh > edma3_log_ch_max_val [edma3Id])
1116 {
1117 result = EDMA3_DRV_E_INVALID_PARAM;
1118 }
1119 #endif
1121 if (EDMA3_DRV_SOK == result)
1122 {
1123 paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1124 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1125 {
1126 result = EDMA3_DRV_E_INVALID_PARAM;
1127 }
1128 }
1130 if (EDMA3_DRV_SOK == result)
1131 {
1132 optVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1134 switch (optField)
1135 {
1136 case EDMA3_DRV_OPT_FIELD_SAM :
1137 *optFieldVal = EDMA3_DRV_OPT_SAM_GET_MASK(optVal);
1138 break;
1139 case EDMA3_DRV_OPT_FIELD_DAM :
1140 *optFieldVal = EDMA3_DRV_OPT_DAM_GET_MASK(optVal);
1141 break;
1142 case EDMA3_DRV_OPT_FIELD_SYNCDIM :
1143 *optFieldVal = EDMA3_DRV_OPT_SYNCDIM_GET_MASK(optVal);
1144 break;
1145 case EDMA3_DRV_OPT_FIELD_STATIC :
1146 *optFieldVal = EDMA3_DRV_OPT_STATIC_GET_MASK(optVal);
1147 break;
1148 case EDMA3_DRV_OPT_FIELD_FWID :
1149 *optFieldVal = EDMA3_DRV_OPT_FWID_GET_MASK(optVal);
1150 break;
1151 case EDMA3_DRV_OPT_FIELD_TCCMODE :
1152 *optFieldVal = EDMA3_DRV_OPT_TCCMODE_GET_MASK(optVal);
1153 break;
1154 case EDMA3_DRV_OPT_FIELD_TCC :
1155 *optFieldVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
1156 break;
1157 case EDMA3_DRV_OPT_FIELD_TCINTEN :
1158 *optFieldVal = EDMA3_DRV_OPT_TCINTEN_GET_MASK(optVal);
1159 break;
1160 case EDMA3_DRV_OPT_FIELD_ITCINTEN :
1161 *optFieldVal = EDMA3_DRV_OPT_ITCINTEN_GET_MASK(optVal);
1162 break;
1163 case EDMA3_DRV_OPT_FIELD_TCCHEN :
1164 *optFieldVal = EDMA3_DRV_OPT_TCCHEN_GET_MASK(optVal);
1165 break;
1166 case EDMA3_DRV_OPT_FIELD_ITCCHEN :
1167 *optFieldVal = EDMA3_DRV_OPT_ITCCHEN_GET_MASK(optVal);
1168 break;
1169 default:
1170 break;
1171 }
1172 }
1174 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1175 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1176 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1177 EDMA3_DVT_dCOUNTER,
1178 EDMA3_DVT_dNONE,
1179 EDMA3_DVT_dNONE));
1180 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1182 return result;
1183 }
1185 EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
1186 uint32_t lCh,
1187 uint32_t srcAddr,
1188 EDMA3_DRV_AddrMode addrMode,
1189 EDMA3_DRV_FifoWidth fifoWidth)
1190 {
1191 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1192 uint32_t opt = 0;
1193 EDMA3_DRV_Instance *drvInst = NULL;
1194 EDMA3_DRV_Object *drvObject = NULL;
1195 int32_t paRAMId = 0;
1196 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1197 uint32_t mappedEvtQ = 0;
1198 uint32_t defaultBurstSize = 0;
1199 uint32_t edma3Id;
1201 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1202 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1203 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1204 EDMA3_DVT_dCOUNTER,
1205 EDMA3_DVT_dNONE,
1206 EDMA3_DVT_dNONE));
1207 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1209 /* If parameter checking is enabled... */
1210 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1211 if ((hEdma == NULL)
1212 || ((((int32_t)addrMode < (int32_t)EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
1213 || (((int32_t)fifoWidth < (int32_t)EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
1214 {
1215 result = EDMA3_DRV_E_INVALID_PARAM;
1216 }
1218 /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
1219 if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1220 && ((srcAddr & 0x1Fu) != NULL))
1221 {
1222 /** Memory is not 32 bytes aligned */
1223 result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
1224 }
1225 #endif
1227 /* Check if the parameters are OK. */
1228 if (EDMA3_DRV_SOK == result)
1229 {
1230 drvInst = (EDMA3_DRV_Instance *)hEdma;
1231 drvObject = drvInst->pDrvObjectHandle;
1233 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1234 {
1235 result = EDMA3_DRV_E_INVALID_PARAM;
1236 }
1237 else
1238 {
1239 edma3Id = drvObject->phyCtrllerInstId;
1240 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1241 }
1242 }
1244 /* If parameter checking is enabled... */
1245 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1246 if (lCh > edma3_log_ch_max_val [edma3Id])
1247 {
1248 result = EDMA3_DRV_E_INVALID_PARAM;
1249 }
1250 #endif
1252 if (EDMA3_DRV_SOK == result)
1253 {
1254 paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1255 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1256 {
1257 result = EDMA3_DRV_E_INVALID_PARAM;
1258 }
1259 }
1261 if (EDMA3_DRV_SOK == result)
1262 {
1263 /**
1264 * If request is for FIFO mode, check whether the FIFO size
1265 * is supported by the Transfer Controller which will be used for
1266 * this transfer or not.
1267 */
1268 if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1269 {
1270 if (lCh <= edma3_dma_ch_max_val [edma3Id])
1271 {
1272 mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])
1273 & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
1274 >> ((lCh%8u)*4u);
1275 }
1276 else
1277 {
1278 if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
1279 &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
1280 {
1281 mappedEvtQ = ((globalRegs->QDMAQNUM)
1282 & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
1283 >> (lCh*4u);
1284 }
1285 }
1287 /**
1288 * mappedEvtQ contains the event queue and hence the TC which will
1289 * process this transfer request. Check whether this TC supports the
1290 * FIFO size or not.
1291 */
1292 defaultBurstSize = 1u << fifoWidth;
1293 if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
1294 {
1295 result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
1296 }
1297 }
1298 }
1300 if (EDMA3_DRV_SOK == result)
1301 {
1302 /* Set Src Address */
1303 *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
1304 (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;
1306 opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1308 /* Set SAM */
1309 opt &= EDMA3_DRV_OPT_SAM_CLR_MASK;
1310 opt |= EDMA3_DRV_OPT_SAM_SET_MASK(addrMode);
1311 /* Set FIFO Width */
1312 opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
1313 opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
1315 /* Set the OPT */
1316 *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1317 }
1319 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1320 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1321 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1322 EDMA3_DVT_dCOUNTER,
1323 EDMA3_DVT_dNONE,
1324 EDMA3_DVT_dNONE));
1325 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1327 return result;
1328 }
1330 EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
1331 uint32_t lCh,
1332 uint32_t destAddr,
1333 EDMA3_DRV_AddrMode addrMode,
1334 EDMA3_DRV_FifoWidth fifoWidth)
1335 {
1336 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1337 uint32_t opt = 0;
1338 EDMA3_DRV_Instance *drvInst = NULL;
1339 EDMA3_DRV_Object *drvObject = NULL;
1340 int32_t paRAMId = 0;
1341 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1342 uint32_t mappedEvtQ = 0;
1343 uint32_t defaultBurstSize = 0;
1344 uint32_t edma3Id;
1346 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1347 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1348 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1349 EDMA3_DVT_dCOUNTER,
1350 EDMA3_DVT_dNONE,
1351 EDMA3_DVT_dNONE));
1352 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1354 /* If parameter checking is enabled... */
1355 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1356 if ((hEdma == NULL)
1357 || ((((int32_t)addrMode < (int32_t)EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
1358 || (((int32_t)fifoWidth < (int32_t)EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
1359 {
1360 result = EDMA3_DRV_E_INVALID_PARAM;
1361 }
1363 /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
1364 if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1365 && ((destAddr & 0x1Fu)!=NULL))
1366 {
1367 /** Memory is not 32 bytes aligned */
1368 result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
1369 }
1370 #endif
1372 /* Check if the parameters are OK. */
1373 if (EDMA3_DRV_SOK == result)
1374 {
1375 drvInst = (EDMA3_DRV_Instance *)hEdma;
1376 drvObject = drvInst->pDrvObjectHandle;
1378 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1379 {
1380 result = EDMA3_DRV_E_INVALID_PARAM;
1381 }
1382 else
1383 {
1384 edma3Id = drvObject->phyCtrllerInstId;
1385 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1386 }
1387 }
1389 /* If parameter checking is enabled... */
1390 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1391 if (lCh > edma3_log_ch_max_val [edma3Id])
1392 {
1393 result = EDMA3_DRV_E_INVALID_PARAM;
1394 }
1395 #endif
1397 if (EDMA3_DRV_SOK == result)
1398 {
1399 paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1400 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1401 {
1402 result = EDMA3_DRV_E_INVALID_PARAM;
1403 }
1404 }
1406 if (EDMA3_DRV_SOK == result)
1407 {
1408 /**
1409 * If request is for FIFO mode, check whether the FIFO size
1410 * is supported by the Transfer Controller which will be used for
1411 * this transfer or not.
1412 */
1413 if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
1414 {
1415 if (lCh <= edma3_dma_ch_max_val [edma3Id])
1416 {
1417 mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])
1418 & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
1419 >> ((lCh%8u)*4u);
1420 }
1421 else
1422 {
1423 if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
1424 &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
1425 {
1426 mappedEvtQ = ((globalRegs->QDMAQNUM)
1427 & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
1428 >> (lCh*4u);
1429 }
1430 }
1432 /**
1433 * mappedEvtQ contains the event queue and hence the TC which will
1434 * process this transfer request. Check whether this TC supports the
1435 * FIFO size or not.
1436 */
1437 defaultBurstSize = 1u << fifoWidth;
1438 if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
1439 {
1440 result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
1441 }
1442 }
1443 }
1445 if (EDMA3_DRV_SOK == result)
1446 {
1447 /* Set the Dest address */
1448 *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
1449 (uint32_t)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;
1451 opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1453 /* Set DAM */
1454 opt &= EDMA3_DRV_OPT_DAM_CLR_MASK;
1455 opt |= EDMA3_DRV_OPT_DAM_SET_MASK(addrMode);
1456 /* Set FIFO Width */
1457 opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
1458 opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
1460 /* Set the OPT */
1461 *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1462 }
1464 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1465 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1466 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1467 EDMA3_DVT_dCOUNTER,
1468 EDMA3_DVT_dNONE,
1469 EDMA3_DVT_dNONE));
1470 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1472 return result;
1473 }
1475 EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
1476 uint32_t lCh,
1477 int32_t srcBIdx, int32_t srcCIdx)
1478 {
1479 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1480 uint32_t srcDstBidx;
1481 uint32_t srcDstCidx;
1482 EDMA3_DRV_Instance *drvInst = NULL;
1483 EDMA3_DRV_Object *drvObject = NULL;
1484 int32_t paRAMId = 0;
1485 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1486 uint32_t edma3Id;
1488 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1489 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1490 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1491 EDMA3_DVT_dCOUNTER,
1492 EDMA3_DVT_dNONE,
1493 EDMA3_DVT_dNONE));
1494 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1496 /* If parameter checking is enabled... */
1497 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1498 if (hEdma == NULL)
1499 {
1500 result = EDMA3_DRV_E_INVALID_PARAM;
1501 }
1503 if (((srcBIdx > EDMA3_DRV_SRCBIDX_MAX_VAL)
1504 || (srcBIdx < EDMA3_DRV_SRCBIDX_MIN_VAL))
1505 || ((srcCIdx > EDMA3_DRV_SRCCIDX_MAX_VAL)
1506 || (srcCIdx < EDMA3_DRV_SRCCIDX_MIN_VAL)))
1507 {
1508 result = EDMA3_DRV_E_INVALID_PARAM;
1509 }
1510 #endif
1512 /* Check if the parameters are OK. */
1513 if (EDMA3_DRV_SOK == result)
1514 {
1515 drvInst = (EDMA3_DRV_Instance *)hEdma;
1516 drvObject = drvInst->pDrvObjectHandle;
1518 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1519 {
1520 result = EDMA3_DRV_E_INVALID_PARAM;
1521 }
1522 else
1523 {
1524 edma3Id = drvObject->phyCtrllerInstId;
1525 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1526 }
1527 }
1529 /* If parameter checking is enabled... */
1530 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1531 if (lCh > edma3_log_ch_max_val [edma3Id])
1532 {
1533 result = EDMA3_DRV_E_INVALID_PARAM;
1534 }
1535 #endif
1537 if (EDMA3_DRV_SOK == result)
1538 {
1539 paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1540 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1541 {
1542 result = EDMA3_DRV_E_INVALID_PARAM;
1543 }
1544 else
1545 {
1546 /* Get SrcDestBidx PaRAM Set entry */
1547 srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1548 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
1550 srcDstBidx &= 0xFFFF0000u;
1551 /* Update it */
1552 srcDstBidx |= (uint32_t)(srcBIdx & 0xFFFF);
1554 /* Store it back */
1555 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1556 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
1558 /* Get SrcDestCidx PaRAM Set entry */
1559 srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1560 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
1562 srcDstCidx &= 0xFFFF0000u;
1563 /* Update it */
1564 srcDstCidx |= (uint32_t)(srcCIdx & 0xFFFF);
1566 /* Store it back */
1567 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1568 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
1569 }
1570 }
1572 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1573 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1574 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1575 EDMA3_DVT_dCOUNTER,
1576 EDMA3_DVT_dNONE,
1577 EDMA3_DVT_dNONE));
1578 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1580 return result;
1581 }
1583 EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, uint32_t lCh,
1584 int32_t destBIdx, int32_t destCIdx)
1585 {
1586 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1587 uint32_t srcDstBidx;
1588 uint32_t srcDstCidx;
1589 EDMA3_DRV_Instance *drvInst = NULL;
1590 EDMA3_DRV_Object *drvObject = NULL;
1591 int32_t paRAMId = 0;
1592 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1593 uint32_t edma3Id;
1595 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1596 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1597 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1598 EDMA3_DVT_dCOUNTER,
1599 EDMA3_DVT_dNONE,
1600 EDMA3_DVT_dNONE));
1601 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1603 /* If parameter checking is enabled... */
1604 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1605 if (hEdma == NULL)
1606 {
1607 result = EDMA3_DRV_E_INVALID_PARAM;
1608 }
1610 if (((destBIdx > EDMA3_DRV_DSTBIDX_MAX_VAL)
1611 || (destBIdx < EDMA3_DRV_DSTBIDX_MIN_VAL))
1612 || ((destCIdx > EDMA3_DRV_DSTCIDX_MAX_VAL)
1613 || (destCIdx < EDMA3_DRV_DSTCIDX_MIN_VAL)))
1614 {
1615 result = EDMA3_DRV_E_INVALID_PARAM;
1616 }
1617 #endif
1619 /* Check if the parameters are OK. */
1620 if (EDMA3_DRV_SOK == result)
1621 {
1622 drvInst = (EDMA3_DRV_Instance *)hEdma;
1623 drvObject = drvInst->pDrvObjectHandle;
1625 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1626 {
1627 result = EDMA3_DRV_E_INVALID_PARAM;
1628 }
1629 else
1630 {
1631 edma3Id = drvObject->phyCtrllerInstId;
1632 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1633 }
1634 }
1636 /* If parameter checking is enabled... */
1637 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1638 if (lCh > edma3_log_ch_max_val [edma3Id])
1639 {
1640 result = EDMA3_DRV_E_INVALID_PARAM;
1641 }
1642 #endif
1644 if (EDMA3_DRV_SOK == result)
1645 {
1646 paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1647 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1648 {
1649 result = EDMA3_DRV_E_INVALID_PARAM;
1650 }
1651 else
1652 {
1653 /* Get SrcDestBidx PaRAM Set entry */
1654 srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1655 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
1657 srcDstBidx &= 0xFFFFu;
1658 /* Update it */
1659 srcDstBidx |= (uint32_t)((destBIdx & 0xFFFF) << 16u);
1661 /* Store it back */
1662 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1663 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
1665 /* Get SrcDestCidx PaRAM Set entry */
1666 srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1667 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
1669 srcDstCidx &= 0xFFFFu;
1670 /* Update it */
1671 srcDstCidx |= (uint32_t)((destCIdx & 0xFFFF) << 16u);
1673 /* Store it back */
1674 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1675 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
1676 }
1677 }
1679 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1680 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1681 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1682 EDMA3_DVT_dCOUNTER,
1683 EDMA3_DVT_dNONE,
1684 EDMA3_DVT_dNONE));
1685 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1687 return result;
1688 }
1690 EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
1691 uint32_t lCh, uint32_t aCnt, uint32_t bCnt, uint32_t cCnt,
1692 uint32_t bCntReload, EDMA3_DRV_SyncType syncType)
1693 {
1694 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1695 uint32_t abCnt = 0;
1696 uint32_t linkBCntReld = 0;
1697 uint32_t opt = 0;
1698 EDMA3_DRV_Instance *drvInst = NULL;
1699 EDMA3_DRV_Object *drvObject = NULL;
1700 int32_t paRAMId = 0;
1701 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1702 uint32_t edma3Id;
1704 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1705 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1706 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1707 EDMA3_DVT_dCOUNTER,
1708 EDMA3_DVT_dNONE,
1709 EDMA3_DVT_dNONE));
1710 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1712 /* If parameter checking is enabled... */
1713 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1714 if (hEdma == NULL)
1715 {
1716 result = EDMA3_DRV_E_INVALID_PARAM;
1717 }
1719 if ((((aCnt > EDMA3_DRV_ACNT_MAX_VAL)
1720 || (bCnt > EDMA3_DRV_BCNT_MAX_VAL))
1721 || ((cCnt > EDMA3_DRV_CCNT_MAX_VAL)
1722 || (bCntReload > EDMA3_DRV_BCNTRELD_MAX_VAL)))
1723 || (((int32_t)syncType < (int32_t)EDMA3_DRV_SYNC_A) || (syncType > EDMA3_DRV_SYNC_AB)))
1724 {
1725 result = EDMA3_DRV_E_INVALID_PARAM;
1726 }
1727 #endif
1729 /* Check if the parameters are OK. */
1730 if (EDMA3_DRV_SOK == result)
1731 {
1732 drvInst = (EDMA3_DRV_Instance *)hEdma;
1733 drvObject = drvInst->pDrvObjectHandle;
1735 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1736 {
1737 result = EDMA3_DRV_E_INVALID_PARAM;
1738 }
1739 else
1740 {
1741 edma3Id = drvObject->phyCtrllerInstId;
1742 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1743 }
1744 }
1746 /* If parameter checking is enabled... */
1747 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1748 if (lCh > edma3_log_ch_max_val [edma3Id])
1749 {
1750 result = EDMA3_DRV_E_INVALID_PARAM;
1751 }
1752 #endif
1754 if (EDMA3_DRV_SOK == result)
1755 {
1756 paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
1757 if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
1758 {
1759 result = EDMA3_DRV_E_INVALID_PARAM;
1760 }
1761 else
1762 {
1763 abCnt = aCnt | ((bCnt&0xFFFFu) << 16u);
1765 /* Set aCnt and bCnt */
1766 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1767 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;
1769 /* Set cCnt */
1770 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1771 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;
1774 linkBCntReld = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
1775 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
1777 linkBCntReld |= ((bCntReload & 0xFFFFu) << 16u);
1779 /* Set bCntReload */
1780 *((&globalRegs->PARAMENTRY[paRAMId].OPT)
1781 + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;
1783 opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
1785 /* Set Sync Type */
1786 opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK;
1787 opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK(syncType);
1789 *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
1790 }
1791 }
1793 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1794 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1795 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1796 EDMA3_DVT_dCOUNTER,
1797 EDMA3_DVT_dNONE,
1798 EDMA3_DVT_dNONE));
1799 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1801 return result;
1802 }
1804 EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
1805 uint32_t lCh,
1806 EDMA3_DRV_TrigMode trigMode)
1807 {
1808 EDMA3_DRV_Instance *drvInst = NULL;
1809 EDMA3_DRV_Object *drvObject = NULL;
1810 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1811 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1812 uint32_t edma3Id;
1814 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1815 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1816 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1817 EDMA3_DVT_dCOUNTER,
1818 EDMA3_DVT_dNONE,
1819 EDMA3_DVT_dNONE));
1820 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1822 /* If parameter checking is enabled... */
1823 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1824 if (hEdma == NULL)
1825 {
1826 result = EDMA3_DRV_E_INVALID_PARAM;
1827 }
1828 #endif
1830 if (EDMA3_DRV_SOK == result)
1831 {
1832 drvInst = (EDMA3_DRV_Instance *)hEdma;
1833 drvObject = drvInst->pDrvObjectHandle;
1835 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1836 {
1837 result = EDMA3_DRV_E_INVALID_PARAM;
1838 }
1839 else
1840 {
1841 edma3Id = drvObject->phyCtrllerInstId;
1842 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1843 }
1844 }
1846 /* If parameter checking is enabled... */
1847 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1848 if (lCh > edma3_log_ch_max_val [edma3Id])
1849 {
1850 result = EDMA3_DRV_E_INVALID_PARAM;
1851 }
1853 /* Trigger type is Manual */
1854 if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
1855 && (lCh > edma3_dma_ch_max_val [edma3Id]))
1856 {
1857 /* Channel Id lies outside DMA channel range */
1858 result = EDMA3_DRV_E_INVALID_PARAM;
1859 }
1861 /* Trigger type is QDMA */
1862 if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
1863 && ((lCh < edma3_qdma_ch_min_val[edma3Id])
1864 || (lCh > edma3_qdma_ch_max_val[edma3Id])))
1865 {
1866 /* Channel Id lies outside QDMA channel range */
1867 result = EDMA3_DRV_E_INVALID_PARAM;
1868 }
1870 /* Trigger type is Event */
1871 if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
1872 && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
1873 & (1u<<(lCh%32u))) == FALSE))
1874 {
1875 /* Channel was not mapped to any Hw Event. */
1876 result = EDMA3_DRV_E_INVALID_PARAM;
1877 }
1878 #endif
1880 if (EDMA3_DRV_SOK == result)
1881 {
1882 switch (trigMode)
1883 {
1884 case EDMA3_DRV_TRIG_MODE_MANUAL :
1885 {
1886 if (lCh < 32u)
1887 {
1888 drvInst->shadowRegs->ESR = (1UL << lCh);
1889 }
1890 else
1891 {
1892 drvInst->shadowRegs->ESRH = (1UL << (lCh-32u));
1893 }
1894 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1895 EDMA3_DRV_TRIG_MODE_MANUAL;
1896 }
1897 break;
1899 case EDMA3_DRV_TRIG_MODE_QDMA :
1900 {
1901 drvInst->shadowRegs->QEESR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
1902 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1903 EDMA3_DRV_TRIG_MODE_QDMA;
1904 }
1905 break;
1907 case EDMA3_DRV_TRIG_MODE_EVENT :
1908 {
1909 if (lCh < 32u)
1910 {
1911 /*clear SECR to clean any previous NULL request */
1912 drvInst->shadowRegs->SECR = (1UL << lCh);
1914 /*clear EMCR to clean any previous NULL request */
1915 globalRegs->EMCR = (1UL << lCh);
1917 drvInst->shadowRegs->EESR = (1UL << lCh);
1918 }
1919 else
1920 {
1921 /*clear SECR to clean any previous NULL request */
1922 drvInst->shadowRegs->SECRH = (1UL << (lCh-32u));
1924 /*clear EMCR to clean any previous NULL request */
1925 globalRegs->EMCRH = (1UL << (lCh-32u));
1927 drvInst->shadowRegs->EESRH = (1UL << (lCh-32u));
1928 }
1930 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
1931 EDMA3_DRV_TRIG_MODE_EVENT;
1932 }
1933 break;
1935 default :
1936 result = EDMA3_DRV_E_INVALID_PARAM;
1937 break;
1938 }
1939 }
1941 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1942 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1943 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
1944 EDMA3_DVT_dCOUNTER,
1945 EDMA3_DVT_dNONE,
1946 EDMA3_DVT_dNONE));
1947 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1949 return result;
1950 }
1952 EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
1953 uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
1954 {
1955 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
1956 EDMA3_DRV_Instance *drvInst = NULL;
1957 EDMA3_DRV_Object *drvObject = NULL;
1958 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
1959 uint32_t edma3Id;
1961 #ifdef EDMA3_INSTRUMENTATION_ENABLED
1962 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
1963 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
1964 EDMA3_DVT_dCOUNTER,
1965 EDMA3_DVT_dNONE,
1966 EDMA3_DVT_dNONE));
1967 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
1969 /* If parameter checking is enabled... */
1970 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1971 if (hEdma == NULL)
1972 {
1973 result = EDMA3_DRV_E_INVALID_PARAM;
1974 }
1975 #endif
1977 /* Check if the parameters are OK. */
1978 if (EDMA3_DRV_SOK == result)
1979 {
1980 drvInst = (EDMA3_DRV_Instance *)hEdma;
1981 drvObject = drvInst->pDrvObjectHandle;
1983 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
1984 {
1985 result = EDMA3_DRV_E_INVALID_PARAM;
1986 }
1987 else
1988 {
1989 edma3Id = drvObject->phyCtrllerInstId;
1990 globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
1991 }
1992 }
1994 /* If parameter checking is enabled... */
1995 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
1996 if (lCh > edma3_log_ch_max_val [edma3Id])
1997 {
1998 result = EDMA3_DRV_E_INVALID_PARAM;
1999 }
2001 /* Trigger type is Manual */
2002 if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
2003 && (lCh > edma3_dma_ch_max_val [edma3Id]))
2004 {
2005 /* Channel Id lies outside DMA channel range */
2006 result = EDMA3_DRV_E_INVALID_PARAM;
2007 }
2009 /* Trigger type is QDMA */
2010 if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
2011 && ((lCh < edma3_qdma_ch_min_val[edma3Id])
2012 || (lCh > edma3_qdma_ch_max_val[edma3Id])))
2013 {
2014 /* Channel Id lies outside QDMA channel range */
2015 result = EDMA3_DRV_E_INVALID_PARAM;
2016 }
2018 /* Trigger type is Event */
2019 if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
2020 && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
2021 & (1u<<(lCh%32u))) == FALSE))
2022 {
2023 /* Channel was not mapped to any Hw Event. */
2024 result = EDMA3_DRV_E_INVALID_PARAM;
2025 }
2026 #endif
2028 if (EDMA3_DRV_SOK == result)
2029 {
2030 switch (trigMode)
2031 {
2032 case EDMA3_DRV_TRIG_MODE_MANUAL :
2033 {
2034 if (lCh < 32u)
2035 {
2036 if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)
2037 {
2038 drvInst->shadowRegs->SECR = (1u<<lCh);
2039 }
2040 if((globalRegs->EMR & (1u<<lCh))!=FALSE)
2041 {
2042 globalRegs->EMCR = (1u<<lCh);
2043 }
2044 }
2045 else
2046 {
2047 if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)
2048 {
2049 drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));
2050 }
2052 if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)
2053 {
2054 globalRegs->EMCRH = (1u<<(lCh-32u));
2055 }
2056 }
2057 }
2058 break;
2060 case EDMA3_DRV_TRIG_MODE_QDMA :
2061 {
2062 drvInst->shadowRegs->QEECR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
2063 }
2064 break;
2066 case EDMA3_DRV_TRIG_MODE_EVENT :
2067 {
2068 if (lCh < 32u)
2069 {
2070 drvInst->shadowRegs->EECR = (1u << lCh);
2072 if((drvInst->shadowRegs->ER & (1u<<lCh))!=FALSE)
2073 {
2074 drvInst->shadowRegs->ECR = (1u<<lCh);
2075 }
2076 if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)
2077 {
2078 drvInst->shadowRegs->SECR = (1u<<lCh);
2079 }
2080 if((globalRegs->EMR & (1u<<lCh))!=FALSE)
2081 {
2082 globalRegs->EMCR = (1u<<lCh);
2083 }
2084 }
2085 else
2086 {
2087 drvInst->shadowRegs->EECRH = (1u << (lCh-32u));
2088 if((drvInst->shadowRegs->ERH & (1u<<(lCh-32u)))!=FALSE)
2089 {
2090 drvInst->shadowRegs->ECRH = (1u<<(lCh-32u));
2091 }
2093 if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)
2094 {
2095 drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));
2096 }
2098 if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)
2099 {
2100 globalRegs->EMCRH = (1u<<(lCh-32u));
2101 }
2102 }
2103 }
2104 break;
2106 default :
2107 result = EDMA3_DRV_E_INVALID_PARAM;
2108 break;
2109 }
2110 }
2112 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2113 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2114 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
2115 EDMA3_DVT_dCOUNTER,
2116 EDMA3_DVT_dNONE,
2117 EDMA3_DVT_dNONE));
2118 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2120 return result;
2121 }
2123 EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
2124 uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
2125 {
2126 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
2127 EDMA3_DRV_Instance *drvInst = NULL;
2128 EDMA3_DRV_Object *drvObject = NULL;
2129 uint32_t edma3Id;
2131 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2132 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2133 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
2134 EDMA3_DVT_dCOUNTER,
2135 EDMA3_DVT_dNONE,
2136 EDMA3_DVT_dNONE));
2137 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2139 /* If parameter checking is enabled... */
2140 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2141 if (hEdma == NULL)
2142 {
2143 result = EDMA3_DRV_E_INVALID_PARAM;
2144 }
2145 #endif
2147 /* Check if the parameters are OK. */
2148 if (EDMA3_DRV_SOK == result)
2149 {
2150 drvInst = (EDMA3_DRV_Instance *)hEdma;
2151 drvObject = drvInst->pDrvObjectHandle;
2153 if (drvObject == NULL)
2154 {
2155 result = EDMA3_DRV_E_INVALID_PARAM;
2156 }
2157 else
2158 {
2159 edma3Id = drvObject->phyCtrllerInstId;
2160 }
2161 }
2163 /* If parameter checking is enabled... */
2164 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
2165 if (lCh > edma3_log_ch_max_val [edma3Id])
2166 {
2167 result = EDMA3_DRV_E_INVALID_PARAM;
2168 }
2170 /* Trigger type is QDMA */
2171 if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
2172 && ((lCh < edma3_qdma_ch_min_val[edma3Id])
2173 || (lCh > edma3_qdma_ch_max_val[edma3Id])))
2174 {
2175 /* Channel Id lies outside QDMA channel range */
2176 result = EDMA3_DRV_E_INVALID_PARAM;
2177 }
2179 /* Trigger type is Event */
2180 if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
2181 && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
2182 & (1u<<(lCh%32u))) == FALSE))
2183 {
2184 /* Channel was not mapped to any Hw Event. */
2185 result = EDMA3_DRV_E_INVALID_PARAM;
2186 }
2187 #endif
2189 if (EDMA3_DRV_SOK == result)
2190 {
2191 switch (trigMode)
2192 {
2193 case EDMA3_DRV_TRIG_MODE_QDMA:
2194 {
2195 drvInst->shadowRegs->QEECR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
2196 }
2197 break;
2199 case EDMA3_DRV_TRIG_MODE_EVENT:
2200 {
2201 if (lCh < 32u)
2202 drvInst->shadowRegs->EECR = (1u << lCh);
2203 else
2204 drvInst->shadowRegs->EECRH = (1u << (lCh-32u));
2205 }
2206 break;
2208 default :
2209 result = EDMA3_DRV_E_INVALID_PARAM;
2210 break;
2211 }
2212 }
2214 #ifdef EDMA3_INSTRUMENTATION_ENABLED
2215 EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
2216 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
2217 EDMA3_DVT_dCOUNTER,
2218 EDMA3_DVT_dNONE,
2219 EDMA3_DVT_dNONE));
2220 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
2222 return result;
2223 }
2225 /* Definitions of Local functions - Start */
2226 /** Remove various mappings and do cleanup for DMA/QDMA channels */
2227 static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
2228 uint32_t channelId)
2229 {
2230 uint32_t intState=0;
2231 EDMA3_DRV_Instance *drvInst = NULL;
2232 EDMA3_DRV_Object *drvObject = NULL;
2233 EDMA3_DRV_Result result = EDMA3_DRV_SOK;
2234 volatile EDMA3_CCRL_Regs *globalRegs = NULL;
2235 EDMA3_RM_ResDesc channelObj;
2236 uint32_t edma3Id;
2238 assert (hEdma != NULL);
2240 drvInst = (EDMA3_DRV_Instance *)hEdma;
2241 drvObject = drvInst->pDrvObjectHandle;
2243 if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
2244 {
2245 result = EDMA3_DRV_E_INVALID_PARAM;
2246 }
2247 else
2248 {
2249 edma3Id = drvObject->phyCtrllerInstId;
2250 globalRegs = (volatile EDMA3_CCRL_Regs *)
2251 (drvObject->gblCfgParams.globalRegs);
2252 }
2254 assert (channelId <= edma3_log_ch_max_val [edma3Id]);
2257 /**
2258 * Disable any ongoing transfer on the channel, if transfer was
2259 * enabled earlier.
2260 */
2261 if (EDMA3_DRV_TRIG_MODE_NONE !=
2262 edma3DrvChBoundRes[edma3Id][channelId].trigMode)
2263 {
2264 result = EDMA3_DRV_disableTransfer(hEdma, channelId,
2265 edma3DrvChBoundRes[edma3Id][channelId].trigMode);
2266 }
2268 if (EDMA3_DRV_SOK == result)
2269 {
2270 /*
2271 * Unregister the TCC Callback function and disable the interrupts.
2272 */
2273 if (channelId < drvObject->gblCfgParams.numDmaChannels)
2274 {
2275 /* DMA channel */
2276 channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
2277 channelObj.resId = channelId;
2278 }
2279 else
2280 {
2281 /* QDMA channel */
2282 channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
2283 channelObj.resId = channelId - edma3_qdma_ch_min_val[edma3Id];
2284 }
2286 result = EDMA3_RM_unregisterTccCb(drvInst->resMgrInstance,
2287 (EDMA3_RM_ResDesc *)&channelObj);
2288 }
2290 if (result == EDMA3_RM_SOK)
2291 {
2292 edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT, &intState);
2294 if (channelId <= edma3_dma_ch_max_val [edma3Id])
2295 {
2296 /* DMA channel */
2297 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
2298 /* Remove the channel to Event Queue mapping */
2299 globalRegs->DMAQNUM[channelId >> 3u] &=
2300 EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
2301 #endif
2302 /**
2303 * If DMA channel to PaRAM Set mapping exists,
2304 * remove it too.
2305 */
2306 if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
2307 {
2308 globalRegs->DCHMAP[channelId] &=
2309 EDMA3_RM_DCH_PARAM_CLR_MASK;
2310 }
2311 }
2312 else
2313 {
2314 /* QDMA channel */
2315 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
2316 /* Remove the channel to Event Queue mapping */
2317 globalRegs->QDMAQNUM = (globalRegs->QDMAQNUM) &
2318 (EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-edma3_qdma_ch_min_val[edma3Id]));
2319 #endif
2320 /* Remove the channel to PARAM set mapping */
2321 /* Unmap PARAM Set Number for specified channelId */
2322 globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
2323 EDMA3_RM_QCH_PARAM_CLR_MASK;
2325 /* Reset the Trigger Word */
2326 globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
2327 EDMA3_RM_QCH_TRWORD_CLR_MASK;
2328 }
2330 edma3OsProtectExit(edma3Id,
2331 EDMA3_OS_PROTECT_INTERRUPT,
2332 intState);
2333 }
2335 return result;
2336 }
2337 uint32_t EDMA3_DRV_getVersion (void)
2338 {
2339 return EDMA3_LLD_DRV_VERSION_ID;
2340 }
2342 const char* EDMA3_DRV_getVersionStr (void)
2343 {
2344 return edma3LldVersionStr;
2345 }
2346 /* Definitions of Local functions - End */
2348 /* End of File */