packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__instanceinitconfig.html

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  26 <h1>EDMA3_RM_InstanceInitConfig Struct Reference<br>
  27 <small>
  28 [<a class="el" href="group__Edma3RMMain.html">Interface Definition for EDMA3 Resource Manager Layer</a>]</small>
  29 </h1><!-- doxytag: class="EDMA3_RM_InstanceInitConfig" -->Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information.
  30 <a href="#_details">More...</a>
  31 <p>
  32 <code>#include &lt;<a class="el" href="edma3__rm_8h-source.html">edma3_rm.h</a>&gt;</code>
  33 <p>
  34 <table border="0" cellpadding="0" cellspacing="0">
  35 <tr><td></td></tr>
  36 <tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
  37 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__RM__InstanceInitConfig.html#195712f03e6c92f0a386dd036422f956">ownPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
  38
  39 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__RM__InstanceInitConfig.html#fea6ae753bce07d64d92f6521bb489e5">ownDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
  40
  41 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__RM__InstanceInitConfig.html#836f8f25e8a2e01d6649034b7cc92d50">ownQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
  42
  43 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__RM__InstanceInitConfig.html#38b3b42404f41e978c3b682ccf63fa8f">ownTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
  44
  45 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__RM__InstanceInitConfig.html#b97d5476ee84765b1cb26216af673cfc">resvdPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
  46
  47 <tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved PaRAM Sets.  <a href="#b97d5476ee84765b1cb26216af673cfc"></a><br></td></tr>
  48 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__RM__InstanceInitConfig.html#6df76275220d03b4b42c9161b4d670ff">resvdDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
  49
  50 <tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved DMA channels.  <a href="#6df76275220d03b4b42c9161b4d670ff"></a><br></td></tr>
  51 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__RM__InstanceInitConfig.html#e7909518f9ba93b32c496193e797bf3b">resvdQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
  52
  53 <tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved QDMA channels.  <a href="#e7909518f9ba93b32c496193e797bf3b"></a><br></td></tr>
  54 <tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__RM__InstanceInitConfig.html#7996562a8045cf6b7f33e40aa9b49313">resvdTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
  55
  56 <tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved TCCs.  <a href="#7996562a8045cf6b7f33e40aa9b49313"></a><br></td></tr>
  57 </table>
  58 <hr><a name="_details"></a><h2>Detailed Description</h2>
  59 Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information.
  60 <p>
  61 This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 RM instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_RM_open ().<p>
  62 Owned resources: ****************<p>
  63 EDMA3 RM Instances are tied to different shadow regions and hence different masters. Regions could be:<p>
  64 a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc.<p>
  65 User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 RM Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences.<p>
  66 Reserved resources: *******************<p>
  67 During EDMA3 RM initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose.<p>
  68 User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id<p>
  69 For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id.<p>
  70 During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id.<p>
  71 Same logic applies for QDMA channels and TCCs.<p>
  72 For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 RM automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set. <hr><h2>Field Documentation</h2>
  73 <a class="anchor" name="195712f03e6c92f0a386dd036422f956"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownPaRAMSets" ref="195712f03e6c92f0a386dd036422f956" args="[EDMA3_MAX_PARAM_DWRDS]" -->
  74 <div class="memitem">
  75 <div class="memproto">
  76       <table class="memname">
  77         <tr>
  78           <td class="memname">unsigned int <a class="el" href="structEDMA3__RM__InstanceInitConfig.html#195712f03e6c92f0a386dd036422f956">EDMA3_RM_InstanceInitConfig::ownPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]          </td>
  79         </tr>
  80       </table>
  81 </div>
  82 <div class="memdoc">
  83
  84 <p>
  85 PaRAM Sets owned by the EDMA3 RM Instance.
  86 <p>Referenced by <a class="el" href="edma3resmgr_8c-source.html#l03743">EDMA3_RM_allocContiguousResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01151">EDMA3_RM_allocResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01758">EDMA3_RM_freeResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l03108">EDMA3_RM_mapEdmaChannel()</a>, <a class="el" href="edma3resmgr_8c-source.html#l03265">EDMA3_RM_mapQdmaChannel()</a>, and <a class="el" href="edma3resmgr_8c-source.html#l00690">EDMA3_RM_open()</a>.</p>
  87
  88 </div>
  89 </div><p>
  90 <a class="anchor" name="fea6ae753bce07d64d92f6521bb489e5"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownDmaChannels" ref="fea6ae753bce07d64d92f6521bb489e5" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
  91 <div class="memitem">
  92 <div class="memproto">
  93       <table class="memname">
  94         <tr>
  95           <td class="memname">unsigned int <a class="el" href="structEDMA3__RM__InstanceInitConfig.html#fea6ae753bce07d64d92f6521bb489e5">EDMA3_RM_InstanceInitConfig::ownDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]          </td>
  96         </tr>
  97       </table>
  98 </div>
  99 <div class="memdoc">
 100
 101 <p>
 102 DMA Channels owned by the EDMA3 RM Instance.
 103 <p>Referenced by <a class="el" href="edma3resmgr_8c-source.html#l03743">EDMA3_RM_allocContiguousResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01151">EDMA3_RM_allocResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l02751">EDMA3_RM_freeLogicalChannel()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01758">EDMA3_RM_freeResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l03108">EDMA3_RM_mapEdmaChannel()</a>, <a class="el" href="edma3resmgr_8c-source.html#l00690">EDMA3_RM_open()</a>, <a class="el" href="edma3resmgr_8c-source.html#l05984">edma3CCErrHandler()</a>, and <a class="el" href="edma3resmgr_8c-source.html#l06687">edma3ShadowRegionInit()</a>.</p>
 104
 105 </div>
 106 </div><p>
 107 <a class="anchor" name="836f8f25e8a2e01d6649034b7cc92d50"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownQdmaChannels" ref="836f8f25e8a2e01d6649034b7cc92d50" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
 108 <div class="memitem">
 109 <div class="memproto">
 110       <table class="memname">
 111         <tr>
 112           <td class="memname">unsigned int <a class="el" href="structEDMA3__RM__InstanceInitConfig.html#836f8f25e8a2e01d6649034b7cc92d50">EDMA3_RM_InstanceInitConfig::ownQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]          </td>
 113         </tr>
 114       </table>
 115 </div>
 116 <div class="memdoc">
 117
 118 <p>
 119 QDMA Channels owned by the EDMA3 RM Instance.
 120 <p>Referenced by <a class="el" href="edma3resmgr_8c-source.html#l03743">EDMA3_RM_allocContiguousResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01151">EDMA3_RM_allocResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l02751">EDMA3_RM_freeLogicalChannel()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01758">EDMA3_RM_freeResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l03265">EDMA3_RM_mapQdmaChannel()</a>, <a class="el" href="edma3resmgr_8c-source.html#l00690">EDMA3_RM_open()</a>, <a class="el" href="edma3resmgr_8c-source.html#l05984">edma3CCErrHandler()</a>, and <a class="el" href="edma3resmgr_8c-source.html#l06687">edma3ShadowRegionInit()</a>.</p>
 121
 122 </div>
 123 </div><p>
 124 <a class="anchor" name="38b3b42404f41e978c3b682ccf63fa8f"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownTccs" ref="38b3b42404f41e978c3b682ccf63fa8f" args="[EDMA3_MAX_TCC_DWRDS]" -->
 125 <div class="memitem">
 126 <div class="memproto">
 127       <table class="memname">
 128         <tr>
 129           <td class="memname">unsigned int <a class="el" href="structEDMA3__RM__InstanceInitConfig.html#38b3b42404f41e978c3b682ccf63fa8f">EDMA3_RM_InstanceInitConfig::ownTccs</a>[EDMA3_MAX_TCC_DWRDS]          </td>
 130         </tr>
 131       </table>
 132 </div>
 133 <div class="memdoc">
 134
 135 <p>
 136 TCCs owned by the EDMA3 RM Instance.
 137 <p>Referenced by <a class="el" href="edma3resmgr_8c-source.html#l03743">EDMA3_RM_allocContiguousResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01151">EDMA3_RM_allocResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01758">EDMA3_RM_freeResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l00690">EDMA3_RM_open()</a>, and <a class="el" href="edma3resmgr_8c-source.html#l06687">edma3ShadowRegionInit()</a>.</p>
 138
 139 </div>
 140 </div><p>
 141 <a class="anchor" name="b97d5476ee84765b1cb26216af673cfc"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdPaRAMSets" ref="b97d5476ee84765b1cb26216af673cfc" args="[EDMA3_MAX_PARAM_DWRDS]" -->
 142 <div class="memitem">
 143 <div class="memproto">
 144       <table class="memname">
 145         <tr>
 146           <td class="memname">unsigned int <a class="el" href="structEDMA3__RM__InstanceInitConfig.html#b97d5476ee84765b1cb26216af673cfc">EDMA3_RM_InstanceInitConfig::resvdPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]          </td>
 147         </tr>
 148       </table>
 149 </div>
 150 <div class="memdoc">
 151
 152 <p>
 153 Reserved PaRAM Sets.
 154 <p>
 155 PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set using 'EDMA3_RM_PARAM_ANY' as resource/channel id.
 156 <p>Referenced by <a class="el" href="edma3resmgr_8c-source.html#l03743">EDMA3_RM_allocContiguousResource()</a>, <a class="el" href="edma3resmgr_8c-source.html#l01151">EDMA3_RM_allocResource()</a>, and <a class="el" href="edma3resmgr_8c-source.html#l00690">EDMA3_RM_open()</a>.</p>
 157
 158 </div>
 159 </div><p>
 160 <a class="anchor" name="6df76275220d03b4b42c9161b4d670ff"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdDmaChannels" ref="6df76275220d03b4b42c9161b4d670ff" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
 161 <div class="memitem">
 162 <div class="memproto">
 163       <table class="memname">
 164         <tr>
 165           <td class="memname">unsigned int <a class="el" href="structEDMA3__RM__InstanceInitConfig.html#6df76275220d03b4b42c9161b4d670ff">EDMA3_RM_InstanceInitConfig::resvdDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]          </td>
 166         </tr>
 167       </table>
 168 </div>
 169 <div class="memdoc">
 170
 171 <p>
 172 Reserved DMA channels.
 173 <p>
 174 DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id.
 175 <p>Referenced by <a class="el" href="edma3resmgr_8c-source.html#l03743">EDMA3_RM_allocContiguousResource()</a>, and <a class="el" href="edma3resmgr_8c-source.html#l01151">EDMA3_RM_allocResource()</a>.</p>
 176
 177 </div>
 178 </div><p>
 179 <a class="anchor" name="e7909518f9ba93b32c496193e797bf3b"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdQdmaChannels" ref="e7909518f9ba93b32c496193e797bf3b" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
 180 <div class="memitem">
 181 <div class="memproto">
 182       <table class="memname">
 183         <tr>
 184           <td class="memname">unsigned int <a class="el" href="structEDMA3__RM__InstanceInitConfig.html#e7909518f9ba93b32c496193e797bf3b">EDMA3_RM_InstanceInitConfig::resvdQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]          </td>
 185         </tr>
 186       </table>
 187 </div>
 188 <div class="memdoc">
 189
 190 <p>
 191 Reserved QDMA channels.
 192 <p>
 193 QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id.
 194 <p>Referenced by <a class="el" href="edma3resmgr_8c-source.html#l03743">EDMA3_RM_allocContiguousResource()</a>, and <a class="el" href="edma3resmgr_8c-source.html#l01151">EDMA3_RM_allocResource()</a>.</p>
 195
 196 </div>
 197 </div><p>
 198 <a class="anchor" name="7996562a8045cf6b7f33e40aa9b49313"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdTccs" ref="7996562a8045cf6b7f33e40aa9b49313" args="[EDMA3_MAX_TCC_DWRDS]" -->
 199 <div class="memitem">
 200 <div class="memproto">
 201       <table class="memname">
 202         <tr>
 203           <td class="memname">unsigned int <a class="el" href="structEDMA3__RM__InstanceInitConfig.html#7996562a8045cf6b7f33e40aa9b49313">EDMA3_RM_InstanceInitConfig::resvdTccs</a>[EDMA3_MAX_TCC_DWRDS]          </td>
 204         </tr>
 205       </table>
 206 </div>
 207 <div class="memdoc">
 208
 209 <p>
 210 Reserved TCCs.
 211 <p>
 212 TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_RM_TCC_ANY' as resource/channel id.
 213 <p>Referenced by <a class="el" href="edma3resmgr_8c-source.html#l03743">EDMA3_RM_allocContiguousResource()</a>, and <a class="el" href="edma3resmgr_8c-source.html#l01151">EDMA3_RM_allocResource()</a>.</p>
 214
 215 </div>
 216 </div><p>
 217 <hr>The documentation for this struct was generated from the following file:<ul>
 218 <li><a class="el" href="edma3__rm_8h-source.html">edma3_rm.h</a></ul>
 219 </div>
 220 <hr size="1"><address style="text-align: right;"><small>Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by&nbsp;
 221 <a href="http://www.doxygen.org/index.html">
 222 <img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.6 </small></address>
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