2fc06f2c1349f062a82984274e3823f15024d5a4
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / bios6_edma3_rm_sample_da830_cfg.c
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28 *******************************************************************************/
30 /** \file   bios6_edma3_rm_sample_da830_cfg.c
32     \brief  SoC specific EDMA3 hardware related information like number of
33             transfer controllers, various interrupt ids etc. It is used while
34             interrupts enabling / disabling. It needs to be ported for different
35             SoCs.
37     (C) Copyright 2008, Texas Instruments, Inc
39     \version    1.0   Anuj Aggarwal         - Created
41  */
43 #include <ti/sdo/edma3/rm/edma3_rm.h>
46 /* DA830 Specific EDMA3 Information */
48 /** Number of Event Queues available */
49 #define EDMA3_NUM_EVTQUE                                (2u)
51 /** Number of Transfer Controllers available */
52 #define EDMA3_NUM_TC                                    (2u)
54 /** Interrupt no. for Transfer Completion */
55 #define EDMA3_CC_XFER_COMPLETION_INT                    (8u)
57 /** Interrupt no. for CC Error */
58 #define EDMA3_CC_ERROR_INT                              (56u)
60 /** Interrupt no. for TCs Error */
61 #define EDMA3_TC0_ERROR_INT                             (57u)
62 #define EDMA3_TC1_ERROR_INT                             (58u)
63 #define EDMA3_TC2_ERROR_INT                             (0u)
64 #define EDMA3_TC3_ERROR_INT                             (0u)
65 #define EDMA3_TC4_ERROR_INT                             (0u)
66 #define EDMA3_TC5_ERROR_INT                             (0u)
67 #define EDMA3_TC6_ERROR_INT                             (0u)
68 #define EDMA3_TC7_ERROR_INT                             (0u)
70 /**
71 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
72 * ECM events (SoC specific). These ECM events come
73 * under ECM block XXX (handling those specific ECM events). Normally, block
74 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
75 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
76 * is mapped to a specific HWI_INT YYY in the tcf file.
77 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
78 * to transfer completion interrupt.
79 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
80 * to CC error interrupts.
81 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
82 * to TC error interrupts.
83 */
84 #define EDMA3_HWI_INT_XFER_COMP                                                 (7u)
85 #define EDMA3_HWI_INT_CC_ERR                                                    (8u)
86 #define EDMA3_HWI_INT_TC_ERR                                                    (8u)
89 /**
90  * \brief Mapping of DMA channels 0-31 to Hardware Events from
91  * various peripherals, which use EDMA for data transfer.
92  * All channels need not be mapped, some can be free also.
93  * 1: Mapped
94  * 0: Not mapped
95  *
96  * This mapping will be used to allocate DMA channels when user passes
97  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
98  * copy). The same mapping is used to allocate the TCC when user passes
99  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
100  *
101  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
102  */
103                                                                                                           /* 31     0 */
104 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xCF3FFFFFu)
106 /**
107  * \brief Mapping of DMA channels 32-63 to Hardware Events from
108  * various peripherals, which use EDMA for data transfer.
109  * All channels need not be mapped, some can be free also.
110  * 1: Mapped
111  * 0: Not mapped
112  *
113  * This mapping will be used to allocate DMA channels when user passes
114  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
115  * copy). The same mapping is used to allocate the TCC when user passes
116  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
117  *
118  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
119  */
120 /* DMA channels 32-63 DOES NOT exist in DA830. */
121 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x0u)
123 /* Variable which will be used internally for referring number of Event Queues. */
124 unsigned int numEdma3EvtQue = EDMA3_NUM_EVTQUE;
126 /* Variable which will be used internally for referring number of TCs. */
127 unsigned int numEdma3Tc = EDMA3_NUM_TC;
129 /**
130  * Variable which will be used internally for referring transfer completion
131  * interrupt.
132  */
133 unsigned int ccXferCompInt = EDMA3_CC_XFER_COMPLETION_INT;
135 /**
136  * Variable which will be used internally for referring channel controller's
137  * error interrupt.
138  */
139 unsigned int ccErrorInt = EDMA3_CC_ERROR_INT;
141 /**
142  * Variable which will be used internally for referring transfer controllers'
143  * error interrupts.
144  */
145 unsigned int tcErrorInt[8] =    {
146                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
147                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
148                                 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
149                                 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT
150                                 };
152 /**
153  * Variables which will be used internally for referring the hardware interrupt
154  * for various EDMA3 interrupts.
155  */
156 unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
157 unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
158 unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
161 /* Driver Object Initialization Configuration */
162 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams =
163     {
164     /** Total number of DMA Channels supported by the EDMA3 Controller */
165     32u,
166     /** Total number of QDMA Channels supported by the EDMA3 Controller */
167     8u,
168     /** Total number of TCCs supported by the EDMA3 Controller */
169     32u,
170     /** Total number of PaRAM Sets supported by the EDMA3 Controller */
171     128u,
172     /** Total number of Event Queues in the EDMA3 Controller */
173     2u,
174     /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
175     2u,
176     /** Number of Regions on this EDMA3 controller */
177     4u,
179     /**
180      * \brief Channel mapping existence
181      * A value of 0 (No channel mapping) implies that there is fixed association
182      * for a channel number to a parameter entry number or, in other words,
183      * PaRAM entry n corresponds to channel n.
184      */
185     0u,
187     /** Existence of memory protection feature */
188     0u,
190     /** Global Register Region of CC Registers */
191     (void *)0x01C00000u,
192     /** Transfer Controller (TC) Registers */
193         {
194         (void *)0x01C08000u,
195         (void *)0x01C08400u,
196         (void *)NULL,
197         (void *)NULL,
198         (void *)NULL,
199         (void *)NULL,
200         (void *)NULL,
201         (void *)NULL
202         },
203     /** Interrupt no. for Transfer Completion */
204     EDMA3_CC_XFER_COMPLETION_INT,
205     /** Interrupt no. for CC Error */
206     EDMA3_CC_ERROR_INT,
207     /** Interrupt no. for TCs Error */
208         {
209         EDMA3_TC0_ERROR_INT,
210         EDMA3_TC1_ERROR_INT,
211         EDMA3_TC2_ERROR_INT,
212         EDMA3_TC3_ERROR_INT,
213         EDMA3_TC4_ERROR_INT,
214         EDMA3_TC5_ERROR_INT,
215         EDMA3_TC6_ERROR_INT,
216         EDMA3_TC7_ERROR_INT
217         },
219     /**
220      * \brief EDMA3 TC priority setting
221      *
222      * User can program the priority of the Event Queues
223      * at a system-wide level.  This means that the user can set the
224      * priority of an IO initiated by either of the TCs (Transfer Controllers)
225      * relative to IO initiated by the other bus masters on the
226      * device (ARM, DSP, USB, etc)
227      */
228         {
229         0u,
230         1u,
231         0u,
232         0u,
233         0u,
234         0u,
235         0u,
236         0u
237         },
238     /**
239      * \brief To Configure the Threshold level of number of events
240      * that can be queued up in the Event queues. EDMA3CC error register
241      * (CCERR) will indicate whether or not at any instant of time the
242      * number of events queued up in any of the event queues exceeds
243      * or equals the threshold/watermark value that is set
244      * in the queue watermark threshold register (QWMTHRA).
245      */
246         {
247         16u,
248         16u,
249         0u,
250         0u,
251         0u,
252         0u,
253         0u,
254         0u
255         },
257     /**
258      * \brief To Configure the Default Burst Size (DBS) of TCs.
259      * An optimally-sized command is defined by the transfer controller
260      * default burst size (DBS). Different TCs can have different
261      * DBS values. It is defined in Bytes.
262      */
263         {
264         16u,
265         16u,
266         0u,
267         0u,
268         0u,
269         0u,
270         0u,
271         0u
272         },
274     /**
275      * \brief Mapping from each DMA channel to a Parameter RAM set,
276      * if it exists, otherwise of no use.
277      */
278         {
279         0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
280         8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
281         16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
282         24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
283         /* DMA channels 32-63 DOES NOT exist in DA830. */
284         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
285         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
286         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
287         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
288         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
289         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
290         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
291         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
292         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
293         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
294         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
295         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
296         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
297         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
298         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
299         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
300         },
302      /**
303       * \brief Mapping from each DMA channel to a TCC. This specific
304       * TCC code will be returned when the transfer is completed
305       * on the mapped channel.
306       */
307         {
308         0u, 1u, 2u, 3u,
309         4u, 5u, 6u, 7u,
310         8u, 9u, 10u, 11u,
311         12u, 13u, 14u, 15u,
312         16u, 17u, 18u, 19u,
313         20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
314         24u, 25u, 26u, 27u,
315         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31,
316         /* DMA channels 32-63 DOES NOT exist in DA830. */
317         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
318         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
319         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
320         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
321         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
322         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
323         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
324         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
325         },
327     /**
328      * \brief Mapping of DMA channels to Hardware Events from
329      * various peripherals, which use EDMA for data transfer.
330      * All channels need not be mapped, some can be free also.
331      */
332         {
333         EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
334         EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
335         }
336     };
339 /* Driver Instance Initialization Configuration */
340 EDMA3_RM_InstanceInitConfig sampleInstInitConfig =
341     {
342         /* Resources owned by Region 1 */
343         /* ownPaRAMSets */
344         /* 31     0     63    32     95    64     127   96 */
345         {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
346         /* 159  128     191  160     223  192     255  224 */
347          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
348         /* 287  256     319  288     351  320     383  352 */
349          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
350         /* 415  384     447  416     479  448     511  480 */
351          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
353         /* ownDmaChannels */
354         /* 31     0     63    32 */
355         {0xFFFFFFFFu, 0x00000000u},
357         /* ownQdmaChannels */
358         /* 31     0 */
359         {0x000000FFu},
361         /* ownTccs */
362         /* 31     0     63    32 */
363         {0xFFFFFFFFu, 0x00000000u},
365         /* Resources reserved by Region 1 */
366         /* resvdPaRAMSets */
367         /* 31     0     63    32     95    64     127   96 */
368         {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
369         /* 159  128     191  160     223  192     255  224 */
370          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
371         /* 287  256     319  288     351  320     383  352 */
372          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
373         /* 415  384     447  416     479  448     511  480 */
374          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
376         /* resvdDmaChannels */
377         /* 31                                                       0 */
378         {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
379         /* 63                                                     32 */
380             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1},
382         /* resvdQdmaChannels */
383         /* 31     0 */
384         {0x00000000u},
386         /* resvdTccs */
387         /* 31                                                       0 */
388         {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
389         /* 63                                                     32 */
390             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}
391     };
394 /* End of File */