[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_am335x_cfg.c
1 /*
2 * sample_am335x_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 1u
45 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
47 uint16_t determineProcId(void)
48 {
49 return 1U;
50 }
52 int8_t* getGlobalAddr(int8_t* addr)
53 {
54 return (addr); /* The address is already a global address */
55 }
57 uint16_t isGblConfigRequired(uint32_t dspNum)
58 {
59 (void) dspNum;
60 return 0U;
61 }
63 /* Semaphore handles */
64 EDMA3_OS_Sem_Handle SemHandle[NUM_EDMA3_INSTANCES] = {NULL};
66 /** Total number of DMA Channels supported by the EDMA3 Controller */
67 #define EDMA3_NUM_DMA_CHANNELS (64u)
68 /** Total number of QDMA Channels supported by the EDMA3 Controller */
69 #define EDMA3_NUM_QDMA_CHANNELS (8u)
70 /** Total number of TCCs supported by the EDMA3 Controller */
71 #define EDMA3_NUM_TCC (64u)
72 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
73 #define EDMA3_NUM_PARAMSET (256u)
74 /** Total number of Event Queues in the EDMA3 Controller */
75 #define EDMA3_NUM_EVTQUE (3u)
76 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
77 #define EDMA3_NUM_TC (3u)
78 /** Number of Regions on this EDMA3 controller */
79 #define EDMA3_NUM_REGION (8u)
83 /**
84 * \brief Channel mapping existence
85 * A value of 0 (No channel mapping) implies that there is fixed association
86 * for a channel number to a parameter entry number or, in other words,
87 * PaRAM entry n corresponds to channel n.
88 */
89 #define CHANNEL_MAPPING_EXISTENCE (1u)
90 /** Existence of memory protection feature */
91 #define MEM_PROTECTION_EXISTENCE (1u)
93 /** Global Register Region of CC Registers */
94 #define CC_BASE_ADDRESS (0x49000000u)
95 /** Transfer Controller 0 Registers */
96 #define TC0_BASE_ADDRESS (0x49800000u)
97 /** Transfer Controller 1 Registers */
98 #define TC1_BASE_ADDRESS (0x49900000u)
99 /** Transfer Controller 2 Registers */
100 #define TC2_BASE_ADDRESS (0x49A00000u)
101 /** Transfer Controller 3 Registers */
102 #define TC3_BASE_ADDRESS NULL
103 /** Transfer Controller 4 Registers */
104 #define TC4_BASE_ADDRESS NULL
105 /** Transfer Controller 5 Registers */
106 #define TC5_BASE_ADDRESS NULL
107 /** Transfer Controller 6 Registers */
108 #define TC6_BASE_ADDRESS NULL
109 /** Transfer Controller 7 Registers */
110 #define TC7_BASE_ADDRESS NULL
112 /** Interrupt no. for Transfer Completion */
113 #define EDMA3_CC_XFER_COMPLETION_INT (12u)
114 /** Interrupt no. for CC Error */
115 #define EDMA3_CC_ERROR_INT (14u)
116 /** Interrupt no. for TC 0 Error */
117 #define EDMA3_TC0_ERROR_INT (112u)
118 /** Interrupt no. for TC 1 Error */
119 #define EDMA3_TC1_ERROR_INT (113u)
120 /** Interrupt no. for TC 2 Error */
121 #define EDMA3_TC2_ERROR_INT (114u)
122 /** Interrupt no. for TC 3 Error */
123 #define EDMA3_TC3_ERROR_INT (0u)
124 /** Interrupt no. for TC 4 Error */
125 #define EDMA3_TC4_ERROR_INT (0u)
126 /** Interrupt no. for TC 5 Error */
127 #define EDMA3_TC5_ERROR_INT (0u)
128 /** Interrupt no. for TC 6 Error */
129 #define EDMA3_TC6_ERROR_INT (0u)
130 /** Interrupt no. for TC 7 Error */
131 #define EDMA3_TC7_ERROR_INT (0u)
133 /**
134 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
135 * ECM events (SoC specific). These ECM events come
136 * under ECM block XXX (handling those specific ECM events). Normally, block
137 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
138 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
139 * is mapped to a specific HWI_INT YYY in the tcf file.
140 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
141 * to transfer completion interrupt.
142 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
143 * to CC error interrupts.
144 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
145 * to TC error interrupts.
146 */
147 /* EDMA 0 */
149 #define EDMA3_HWI_INT_XFER_COMP (7U)
150 #define EDMA3_HWI_INT_CC_ERR (7U)
151 #define EDMA3_HWI_INT_TC0_ERR (10U)
152 #define EDMA3_HWI_INT_TC1_ERR (10U)
153 #define EDMA3_HWI_INT_TC2_ERR (10U)
155 /**
156 * \brief Mapping of DMA channels 0-31 to Hardware Events from
157 * various peripherals, which use EDMA for data transfer.
158 * All channels need not be mapped, some can be free also.
159 * 1: Mapped
160 * 0: Not mapped
161 *
162 * This mapping will be used to allocate DMA channels when user passes
163 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
164 * copy). The same mapping is used to allocate the TCC when user passes
165 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
166 *
167 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
168 */
169 /* 31 0 */
170 #define DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFF3F3F0Fu)
173 /**
174 * \brief Mapping of DMA channels 32-63 to Hardware Events from
175 * various peripherals, which use EDMA for data transfer.
176 * All channels need not be mapped, some can be free also.
177 * 1: Mapped
178 * 0: Not mapped
179 *
180 * This mapping will be used to allocate DMA channels when user passes
181 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
182 * copy). The same mapping is used to allocate the TCC when user passes
183 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
184 *
185 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
186 */
187 /* DMA channels 32-63 DOES NOT exist in DA830. */
188 #define DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFFCFFF30u)
190 /* Variable which will be used internally for referring number of Event Queues*/
191 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
193 /* Variable which will be used internally for referring number of TCs. */
194 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
196 /**
197 * Variable which will be used internally for referring transfer completion
198 * interrupt.
199 */
200 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
201 {
202 0u, EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,
203 0u, 0u, 0u, 0u,
204 },
205 };
207 /**
208 * Variable which will be used internally for referring channel controller's
209 * error interrupt.
210 */
211 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
213 /**
214 * Variable which will be used internally for referring transfer controllers'
215 * error interrupts.
216 */
217 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
218 {
219 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
220 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
221 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
222 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
223 }
224 };
226 /**
227 * Variables which will be used internally for referring the hardware interrupt
228 * for various EDMA3 interrupts.
229 */
230 uint32_t hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
231 uint32_t hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
232 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
233 {
234 /* EDMA3 INSTANCE# 0 */
235 {
236 EDMA3_HWI_INT_TC0_ERR,
237 EDMA3_HWI_INT_TC1_ERR,
238 EDMA3_HWI_INT_TC2_ERR,
239 0,
240 0,
241 0,
242 0,
243 0
244 }
245 };
248 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
249 {
250 {
251 /** Total number of DMA Channels supported by the EDMA3 Controller */
252 EDMA3_NUM_DMA_CHANNELS,
253 /** Total number of QDMA Channels supported by the EDMA3 Controller */
254 EDMA3_NUM_QDMA_CHANNELS,
255 /** Total number of TCCs supported by the EDMA3 Controller */
256 EDMA3_NUM_TCC,
257 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
258 EDMA3_NUM_PARAMSET,
259 /** Total number of Event Queues in the EDMA3 Controller */
260 EDMA3_NUM_EVTQUE,
261 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
262 EDMA3_NUM_TC,
263 /** Number of Regions on this EDMA3 controller */
264 EDMA3_NUM_REGION,
266 /**
267 * \brief Channel mapping existence
268 * A value of 0 (No channel mapping) implies that there is fixed association
269 * for a channel number to a parameter entry number or, in other words,
270 * PaRAM entry n corresponds to channel n.
271 */
272 CHANNEL_MAPPING_EXISTENCE,
274 /** Existence of memory protection feature */
275 MEM_PROTECTION_EXISTENCE,
277 /** Global Register Region of CC Registers */
278 (void *)(CC_BASE_ADDRESS),
279 /** Transfer Controller (TC) Registers */
280 {
281 (void *)(TC0_BASE_ADDRESS),
282 (void *)(TC1_BASE_ADDRESS),
283 (void *)(TC2_BASE_ADDRESS),
284 (void *)(TC3_BASE_ADDRESS),
285 (void *)(TC4_BASE_ADDRESS),
286 (void *)(TC5_BASE_ADDRESS),
287 (void *)(TC6_BASE_ADDRESS),
288 (void *)(TC7_BASE_ADDRESS)
289 },
290 /** Interrupt no. for Transfer Completion */
291 EDMA3_CC_XFER_COMPLETION_INT,
292 /** Interrupt no. for CC Error */
293 EDMA3_CC_ERROR_INT,
294 /** Interrupt no. for TCs Error */
295 {
296 EDMA3_TC0_ERROR_INT,
297 EDMA3_TC1_ERROR_INT,
298 EDMA3_TC2_ERROR_INT,
299 EDMA3_TC3_ERROR_INT,
300 EDMA3_TC4_ERROR_INT,
301 EDMA3_TC5_ERROR_INT,
302 EDMA3_TC6_ERROR_INT,
303 EDMA3_TC7_ERROR_INT
304 },
306 /**
307 * \brief EDMA3 TC priority setting
308 *
309 * User can program the priority of the Event Queues
310 * at a system-wide level. This means that the user can set the
311 * priority of an IO initiated by either of the TCs (Transfer Controllers)
312 * relative to IO initiated by the other bus masters on the
313 * device (ARM, DSP, USB, etc)
314 */
315 {
316 0u,
317 1u,
318 2u,
319 0u,
320 0u,
321 0u,
322 0u,
323 0u
324 },
325 /**
326 * \brief To Configure the Threshold level of number of events
327 * that can be queued up in the Event queues. EDMA3CC error register
328 * (CCERR) will indicate whether or not at any instant of time the
329 * number of events queued up in any of the event queues exceeds
330 * or equals the threshold/watermark value that is set
331 * in the queue watermark threshold register (QWMTHRA).
332 */
333 {
334 16u,
335 16u,
336 16u,
337 0u,
338 0u,
339 0u,
340 0u,
341 0u
342 },
344 /**
345 * \brief To Configure the Default Burst Size (DBS) of TCs.
346 * An optimally-sized command is defined by the transfer controller
347 * default burst size (DBS). Different TCs can have different
348 * DBS values. It is defined in Bytes.
349 */
350 {
351 16u,
352 16u,
353 16u,
354 0u,
355 0u,
356 0u,
357 0u,
358 0u
359 },
361 /**
362 * \brief Mapping from each DMA channel to a Parameter RAM set,
363 * if it exists, otherwise of no use.
364 */
365 #ifdef EDMA3_RES_USER_REQ
366 {
367 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
368 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
369 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
370 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
371 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
372 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
373 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
374 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
375 },
376 #else
377 {
378 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
379 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
380 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
381 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
382 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
383 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
384 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
385 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
386 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
387 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
388 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
389 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
390 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
391 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
392 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
393 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
394 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
395 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
396 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
397 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
398 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
399 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
400 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
401 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
402 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
403 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
404 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
405 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
406 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
407 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
408 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
409 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
410 },
411 #endif
413 /**
414 * \brief Mapping from each DMA channel to a TCC. This specific
415 * TCC code will be returned when the transfer is completed
416 * on the mapped channel.
417 */
418 {
419 0u, 1u, 2u, 3u,
420 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
421 8u, 9u, 10u, 11u,
422 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 14u, 15u,
423 16u, 17u, 18u, 19u,
424 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 22u, 23u,
425 24u, 25u, 26u, 27u,
426 28u, 29u, 30u, 31u,
427 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
428 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 38u, 39u,
429 40u, 41u, 42u, 43u,
430 44u, 45u, 46u, 47u,
431 48u, 49u, 50u, 51u,
432 52u, 53u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
433 56u, 57u, 58u, 59u,
434 60u, 61u, 62u, 63u
435 },
437 /**
438 * \brief Mapping of DMA channels to Hardware Events from
439 * various peripherals, which use EDMA for data transfer.
440 * All channels need not be mapped, some can be free also.
441 */
442 {
443 DMA_CHANNEL_TO_EVENT_MAPPING_0,
444 DMA_CHANNEL_TO_EVENT_MAPPING_1
445 }
446 }
447 };
450 /* Default RM Instance Initialization Configuration */
451 EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM_REGION] =
452 {
453 {
454 {
455 /* Resources owned by Region 0 */
456 /* ownPaRAMSets */
457 /* 31 0 63 32 95 64 127 96 */
458 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
459 /* 159 128 191 160 223 192 255 224 */
460 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
461 /* 287 256 319 288 351 320 383 352 */
462 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
463 /* 415 384 447 416 479 448 511 480 */
464 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
466 /* ownDmaChannels */
467 /* 31 0 63 32 */
468 {0x00000000u, 0x00000000u},
470 /* ownQdmaChannels */
471 /* 31 0 */
472 {0x00000000u},
474 /* ownTccs */
475 /* 31 0 63 32 */
476 {0x00000000u, 0x00000000u},
478 /* Resources reserved by Region 0 */
479 /* resvdPaRAMSets */
480 /* 31 0 63 32 95 64 127 96 */
481 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
482 /* 159 128 191 160 223 192 255 224 */
483 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
484 /* 287 256 319 288 351 320 383 352 */
485 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
486 /* 415 384 447 416 479 448 511 480 */
487 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
489 /* resvdDmaChannels */
490 /* 31 0 63 32 */
491 {0x00000000u, 0x00000000u},
493 /* resvdQdmaChannels */
494 /* 31 0 */
495 {0x00000000u},
497 /* resvdTccs */
498 /* 31 0 63 32 */
499 {0x00000000u, 0x00000000u},
500 },
502 {
503 /* Resources owned by Region 1 */
504 /* ownPaRAMSets */
505 #ifdef EDMA3_RES_USER_REQ
506 /* 31 0 63 32 95 64 127 96 */
507 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
508 /* 159 128 191 160 223 192 255 224 */
509 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
510 /* 287 256 319 288 351 320 383 352 */
511 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
512 /* 415 384 447 416 479 448 511 480 */
513 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
514 #else
515 /* 31 0 63 32 95 64 127 96 */
516 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
517 /* 159 128 191 160 223 192 255 224 */
518 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
519 /* 287 256 319 288 351 320 383 352 */
520 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
521 /* 415 384 447 416 479 448 511 480 */
522 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
523 #endif
525 /* ownDmaChannels */
526 /* 31 0 63 32 */
527 {0x00C0C0F0u, 0x003000CFu},
529 /* ownQdmaChannels */
530 /* 31 0 */
531 {0x000000FFu},
533 /* ownTccs */
534 /* 31 0 63 32 */
535 {0x00C0C0F0u, 0x003000CFu},
537 /* Resources reserved by Region 1 */
538 /* resvdPaRAMSets */
539 /* 31 0 63 32 95 64 127 96 */
540 {0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
541 /* 159 128 191 160 223 192 255 224 */
542 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
543 /* 287 256 319 288 351 320 383 352 */
544 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
545 /* 415 384 447 416 479 448 511 480 */
546 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
548 /* resvdDmaChannels */
549 /* 31 0 63 32 */
550 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
552 /* resvdQdmaChannels */
553 /* 31 0 */
554 {0x00000000u},
556 /* resvdTccs */
557 /* 31 0 63 32 */
558 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
559 },
561 {
562 /* Resources owned by Region 2 */
563 /* ownPaRAMSets */
564 /* 31 0 63 32 95 64 127 96 */
565 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
566 /* 159 128 191 160 223 192 255 224 */
567 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
568 /* 287 256 319 288 351 320 383 352 */
569 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
570 /* 415 384 447 416 479 448 511 480 */
571 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
573 /* ownDmaChannels */
574 /* 31 0 63 32 */
575 {0x00000000u, 0x00000000u},
577 /* ownQdmaChannels */
578 /* 31 0 */
579 {0x00000000u},
581 /* ownTccs */
582 /* 31 0 63 32 */
583 {0x00000000u, 0x00000000u},
585 /* Resources reserved by Region 2 */
586 /* resvdPaRAMSets */
587 /* 31 0 63 32 95 64 127 96 */
588 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
589 /* 159 128 191 160 223 192 255 224 */
590 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
591 /* 287 256 319 288 351 320 383 352 */
592 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
593 /* 415 384 447 416 479 448 511 480 */
594 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
596 /* resvdDmaChannels */
597 /* 31 0 63 32 */
598 {0x00000000u, 0x00000000u},
600 /* resvdQdmaChannels */
601 /* 31 0 */
602 {0x00000000u},
604 /* resvdTccs */
605 /* 31 0 63 32 */
606 {0x00000000u, 0x00000000u},
607 },
609 {
610 /* Resources owned by Region 3 */
611 /* ownPaRAMSets */
612 /* 31 0 63 32 95 64 127 96 */
613 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
614 /* 159 128 191 160 223 192 255 224 */
615 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
616 /* 287 256 319 288 351 320 383 352 */
617 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
618 /* 415 384 447 416 479 448 511 480 */
619 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
621 /* ownDmaChannels */
622 /* 31 0 63 32 */
623 {0x00000000u, 0x00000000u},
625 /* ownQdmaChannels */
626 /* 31 0 */
627 {0x00000000u},
629 /* ownTccs */
630 /* 31 0 63 32 */
631 {0x00000000u, 0x00000000u},
633 /* Resources reserved by Region 3 */
634 /* resvdPaRAMSets */
635 /* 31 0 63 32 95 64 127 96 */
636 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
637 /* 159 128 191 160 223 192 255 224 */
638 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
639 /* 287 256 319 288 351 320 383 352 */
640 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
641 /* 415 384 447 416 479 448 511 480 */
642 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
644 /* resvdDmaChannels */
645 /* 31 0 63 32 */
646 {0x00000000u, 0x00000000u},
648 /* resvdQdmaChannels */
649 /* 31 0 */
650 {0x00000000u},
652 /* resvdTccs */
653 /* 31 0 63 32 */
654 {0x00000000u, 0x00000000u},
655 },
657 {
658 /* Resources owned by Region 4 */
659 /* ownPaRAMSets */
660 /* 31 0 63 32 95 64 127 96 */
661 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
662 /* 159 128 191 160 223 192 255 224 */
663 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
664 /* 287 256 319 288 351 320 383 352 */
665 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
666 /* 415 384 447 416 479 448 511 480 */
667 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
669 /* ownDmaChannels */
670 /* 31 0 63 32 */
671 {0x00000000u, 0x00000000u},
673 /* ownQdmaChannels */
674 /* 31 0 */
675 {0x00000000u},
677 /* ownTccs */
678 /* 31 0 63 32 */
679 {0x00000000u, 0x00000000u},
681 /* Resources reserved by Region 4 */
682 /* resvdPaRAMSets */
683 /* 31 0 63 32 95 64 127 96 */
684 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
685 /* 159 128 191 160 223 192 255 224 */
686 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
687 /* 287 256 319 288 351 320 383 352 */
688 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
689 /* 415 384 447 416 479 448 511 480 */
690 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
692 /* resvdDmaChannels */
693 /* 31 0 63 32 */
694 {0x00000000u, 0x00000000u},
696 /* resvdQdmaChannels */
697 /* 31 0 */
698 {0x00000000u},
700 /* resvdTccs */
701 /* 31 0 63 32 */
702 {0x00000000u, 0x00000000u},
703 },
705 {
706 /* Resources owned by Region 5 */
707 /* ownPaRAMSets */
708 /* 31 0 63 32 95 64 127 96 */
709 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
710 /* 159 128 191 160 223 192 255 224 */
711 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
712 /* 287 256 319 288 351 320 383 352 */
713 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
714 /* 415 384 447 416 479 448 511 480 */
715 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
717 /* ownDmaChannels */
718 /* 31 0 63 32 */
719 {0x00000000u, 0x00000000u},
721 /* ownQdmaChannels */
722 /* 31 0 */
723 {0x00000000u},
725 /* ownTccs */
726 /* 31 0 63 32 */
727 {0x00000000u, 0x00000000u},
729 /* Resources reserved by Region 5 */
730 /* resvdPaRAMSets */
731 /* 31 0 63 32 95 64 127 96 */
732 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
733 /* 159 128 191 160 223 192 255 224 */
734 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
735 /* 287 256 319 288 351 320 383 352 */
736 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
737 /* 415 384 447 416 479 448 511 480 */
738 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
740 /* resvdDmaChannels */
741 /* 31 0 63 32 */
742 {0x00000000u, 0x00000000u},
744 /* resvdQdmaChannels */
745 /* 31 0 */
746 {0x00000000u},
748 /* resvdTccs */
749 /* 31 0 63 32 */
750 {0x00000000u, 0x00000000u},
751 },
753 {
754 /* Resources owned by Region 6 */
755 /* ownPaRAMSets */
756 /* 31 0 63 32 95 64 127 96 */
757 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
758 /* 159 128 191 160 223 192 255 224 */
759 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
760 /* 287 256 319 288 351 320 383 352 */
761 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
762 /* 415 384 447 416 479 448 511 480 */
763 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
765 /* ownDmaChannels */
766 /* 31 0 63 32 */
767 {0x00000000u, 0x00000000u},
769 /* ownQdmaChannels */
770 /* 31 0 */
771 {0x00000000u},
773 /* ownTccs */
774 /* 31 0 63 32 */
775 {0x00000000u, 0x00000000u},
777 /* Resources reserved by Region 6 */
778 /* resvdPaRAMSets */
779 /* 31 0 63 32 95 64 127 96 */
780 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
781 /* 159 128 191 160 223 192 255 224 */
782 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
783 /* 287 256 319 288 351 320 383 352 */
784 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
785 /* 415 384 447 416 479 448 511 480 */
786 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
788 /* resvdDmaChannels */
789 /* 31 0 63 32 */
790 {0x00000000u, 0x00000000u},
792 /* resvdQdmaChannels */
793 /* 31 0 */
794 {0x00000000u},
796 /* resvdTccs */
797 /* 31 0 63 32 */
798 {0x00000000u, 0x00000000u},
799 },
801 {
802 /* Resources owned by Region 7 */
803 /* ownPaRAMSets */
804 /* 31 0 63 32 95 64 127 96 */
805 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
806 /* 159 128 191 160 223 192 255 224 */
807 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
808 /* 287 256 319 288 351 320 383 352 */
809 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
810 /* 415 384 447 416 479 448 511 480 */
811 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
813 /* ownDmaChannels */
814 /* 31 0 63 32 */
815 {0x00000000u, 0x00000000u},
817 /* ownQdmaChannels */
818 /* 31 0 */
819 {0x00000000u},
821 /* ownTccs */
822 /* 31 0 63 32 */
823 {0x00000000u, 0x00000000u},
825 /* Resources reserved by Region 7 */
826 /* resvdPaRAMSets */
827 /* 31 0 63 32 95 64 127 96 */
828 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
829 /* 159 128 191 160 223 192 255 224 */
830 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
831 /* 287 256 319 288 351 320 383 352 */
832 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
833 /* 415 384 447 416 479 448 511 480 */
834 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
836 /* resvdDmaChannels */
837 /* 31 0 63 32 */
838 {0x00000000u, 0x00000000u},
840 /* resvdQdmaChannels */
841 /* 31 0 */
842 {0x00000000u},
844 /* resvdTccs */
845 /* 31 0 63 32 */
846 {0x00000000u, 0x00000000u},
847 }
848 }
849 };
851 /* End of File */