[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_c6670_cfg.c
1 /*
2 * sample_c6670_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 3u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 4u
49 //const unsigned int numDsps = NUM_DSPS;
51 #define CGEM_REG_START (0x01800000)
54 extern cregister volatile unsigned int DNUM;
56 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
59 /* Determine the processor id by reading DNUM register. */
60 unsigned short determineProcId()
61 {
62 volatile unsigned int *addr;
63 unsigned int core_no;
65 /* Identify the core number */
66 addr = (unsigned int *)(CGEM_REG_START+0x40000);
67 core_no = ((*addr) & 0x000F0000)>>16;
69 return core_no;
70 }
72 signed char* getGlobalAddr(signed char* addr)
73 {
74 if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
75 {
76 return (addr); /* The address is already a global address */
77 }
79 return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
80 }
81 /** Whether global configuration required for EDMA3 or not.
82 * This configuration should be done only once for the EDMA3 hardware by
83 * any one of the masters (i.e. DSPs).
84 * It can be changed depending on the use-case.
85 */
86 unsigned int gblCfgReqdArray [NUM_DSPS] = {
87 0, /* DSP#0 is Master, will do the global init */
88 1, /* DSP#1 is Slave, will not do the global init */
89 1, /* DSP#2 is Slave, will not do the global init */
90 1, /* DSP#3 is Slave, will not do the global init */
91 };
93 unsigned short isGblConfigRequired(unsigned int dspNum)
94 {
95 return gblCfgReqdArray[dspNum];
96 }
98 /* Semaphore handles */
99 EDMA3_OS_Sem_Handle SemHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
102 /* Variable which will be used internally for referring number of Event Queues. */
103 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
105 /* Variable which will be used internally for referring number of TCs. */
106 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
108 /**
109 * Variable which will be used internally for referring transfer completion
110 * interrupt. Completion interrupts for all the shadow regions and all the
111 * EDMA3 controllers are captured since it is a multi-DSP platform.
112 */
113 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
114 {
115 38u, 39u, 40u, 41u,
116 42u, 43u, 44u, 45u,
117 },
118 {
119 8u, 9u, 10u, 11u,
120 12u, 13u, 14u, 15u,
121 },
122 {
123 24u, 25u, 26u, 27u,
124 28u, 29u, 30u, 31u,
125 },
126 };
128 /**
129 * Variable which will be used internally for referring channel controller's
130 * error interrupt.
131 */
132 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
134 /**
135 * Variable which will be used internally for referring transfer controllers'
136 * error interrupts.
137 */
138 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
139 {
140 34u, 35u, 0u, 0u,
141 0u, 0u, 0u, 0u,
142 },
143 {
144 2u, 3u, 4u, 5u,
145 0u, 0u, 0u, 0u,
146 },
147 {
148 18u, 19u, 20u, 21u,
149 0u, 0u, 0u, 0u,
150 },
151 };
153 /* Driver Object Initialization Configuration */
154 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
155 {
156 {
157 /* EDMA3 INSTANCE# 0 */
158 /** Total number of DMA Channels supported by the EDMA3 Controller */
159 16u,
160 /** Total number of QDMA Channels supported by the EDMA3 Controller */
161 8u,
162 /** Total number of TCCs supported by the EDMA3 Controller */
163 16u,
164 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
165 128u,
166 /** Total number of Event Queues in the EDMA3 Controller */
167 2u,
168 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
169 2u,
170 /** Number of Regions on this EDMA3 controller */
171 8u,
173 /**
174 * \brief Channel mapping existence
175 * A value of 0 (No channel mapping) implies that there is fixed association
176 * for a channel number to a parameter entry number or, in other words,
177 * PaRAM entry n corresponds to channel n.
178 */
179 1u,
181 /** Existence of memory protection feature */
182 1u,
184 /** Global Register Region of CC Registers */
185 (void *)0x02700000u,
186 /** Transfer Controller (TC) Registers */
187 {
188 (void *)0x02760000u,
189 (void *)0x02768000u,
190 (void *)NULL,
191 (void *)NULL,
192 (void *)NULL,
193 (void *)NULL,
194 (void *)NULL,
195 (void *)NULL
196 },
197 /** Interrupt no. for Transfer Completion */
198 38u,
199 /** Interrupt no. for CC Error */
200 32u,
201 /** Interrupt no. for TCs Error */
202 {
203 34u,
204 35u,
205 0u,
206 0u,
207 0u,
208 0u,
209 0u,
210 0u,
211 },
213 /**
214 * \brief EDMA3 TC priority setting
215 *
216 * User can program the priority of the Event Queues
217 * at a system-wide level. This means that the user can set the
218 * priority of an IO initiated by either of the TCs (Transfer Controllers)
219 * relative to IO initiated by the other bus masters on the
220 * device (ARM, DSP, USB, etc)
221 */
222 {
223 0u,
224 1u,
225 0u,
226 0u,
227 0u,
228 0u,
229 0u,
230 0u
231 },
232 /**
233 * \brief To Configure the Threshold level of number of events
234 * that can be queued up in the Event queues. EDMA3CC error register
235 * (CCERR) will indicate whether or not at any instant of time the
236 * number of events queued up in any of the event queues exceeds
237 * or equals the threshold/watermark value that is set
238 * in the queue watermark threshold register (QWMTHRA).
239 */
240 {
241 16u,
242 16u,
243 0u,
244 0u,
245 0u,
246 0u,
247 0u,
248 0u
249 },
251 /**
252 * \brief To Configure the Default Burst Size (DBS) of TCs.
253 * An optimally-sized command is defined by the transfer controller
254 * default burst size (DBS). Different TCs can have different
255 * DBS values. It is defined in Bytes.
256 */
257 {
258 128u,
259 128u,
260 0u,
261 0u,
262 0u,
263 0u,
264 0u,
265 0u
266 },
268 /**
269 * \brief Mapping from each DMA channel to a Parameter RAM set,
270 * if it exists, otherwise of no use.
271 */
272 {
273 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
274 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
275 /* DMA channels 16-63 DOES NOT exist */
276 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
277 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
278 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
279 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
280 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
281 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
282 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
283 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
284 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
285 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
286 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
287 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
288 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
289 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
290 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
291 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
292 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
293 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
294 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
295 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
296 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
297 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
298 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
299 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
300 },
302 /**
303 * \brief Mapping from each DMA channel to a TCC. This specific
304 * TCC code will be returned when the transfer is completed
305 * on the mapped channel.
306 */
307 {
308 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
309 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
310 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
311 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
312 /* DMA channels 16-63 DOES NOT exist */
313 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
314 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
315 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
316 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
317 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
318 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
319 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
320 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
321 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
322 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
323 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
324 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
325 },
327 /**
328 * \brief Mapping of DMA channels to Hardware Events from
329 * various peripherals, which use EDMA for data transfer.
330 * All channels need not be mapped, some can be free also.
331 */
332 {
333 0x00003333u,
334 0x00000000u
335 }
336 },
338 {
339 /* EDMA3 INSTANCE# 1 */
340 /** Total number of DMA Channels supported by the EDMA3 Controller */
341 64u,
342 /** Total number of QDMA Channels supported by the EDMA3 Controller */
343 8u,
344 /** Total number of TCCs supported by the EDMA3 Controller */
345 64u,
346 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
347 512u,
348 /** Total number of Event Queues in the EDMA3 Controller */
349 4u,
350 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
351 4u,
352 /** Number of Regions on this EDMA3 controller */
353 8u,
355 /**
356 * \brief Channel mapping existence
357 * A value of 0 (No channel mapping) implies that there is fixed association
358 * for a channel number to a parameter entry number or, in other words,
359 * PaRAM entry n corresponds to channel n.
360 */
361 1u,
363 /** Existence of memory protection feature */
364 1u,
366 /** Global Register Region of CC Registers */
367 (void *)0x02720000u,
368 /** Transfer Controller (TC) Registers */
369 {
370 (void *)0x02770000u,
371 (void *)0x02778000u,
372 (void *)0x02780000u,
373 (void *)0x02788000u,
374 (void *)NULL,
375 (void *)NULL,
376 (void *)NULL,
377 (void *)NULL
378 },
379 /** Interrupt no. for Transfer Completion */
380 8u,
381 /** Interrupt no. for CC Error */
382 0u,
383 /** Interrupt no. for TCs Error */
384 {
385 2u,
386 3u,
387 4u,
388 5u,
389 0u,
390 0u,
391 0u,
392 0u,
393 },
395 /**
396 * \brief EDMA3 TC priority setting
397 *
398 * User can program the priority of the Event Queues
399 * at a system-wide level. This means that the user can set the
400 * priority of an IO initiated by either of the TCs (Transfer Controllers)
401 * relative to IO initiated by the other bus masters on the
402 * device (ARM, DSP, USB, etc)
403 */
404 {
405 0u,
406 1u,
407 2u,
408 3u,
409 0u,
410 0u,
411 0u,
412 0u
413 },
414 /**
415 * \brief To Configure the Threshold level of number of events
416 * that can be queued up in the Event queues. EDMA3CC error register
417 * (CCERR) will indicate whether or not at any instant of time the
418 * number of events queued up in any of the event queues exceeds
419 * or equals the threshold/watermark value that is set
420 * in the queue watermark threshold register (QWMTHRA).
421 */
422 {
423 16u,
424 16u,
425 16u,
426 16u,
427 0u,
428 0u,
429 0u,
430 0u
431 },
433 /**
434 * \brief To Configure the Default Burst Size (DBS) of TCs.
435 * An optimally-sized command is defined by the transfer controller
436 * default burst size (DBS). Different TCs can have different
437 * DBS values. It is defined in Bytes.
438 */
439 {
440 64u,
441 64u,
442 64u,
443 64u,
444 0u,
445 0u,
446 0u,
447 0u
448 },
450 /**
451 * \brief Mapping from each DMA channel to a Parameter RAM set,
452 * if it exists, otherwise of no use.
453 */
454 {
455 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
456 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
457 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
458 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
459 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
460 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
461 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
462 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
463 },
465 /**
466 * \brief Mapping from each DMA channel to a TCC. This specific
467 * TCC code will be returned when the transfer is completed
468 * on the mapped channel.
469 */
470 {
471 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
472 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
473 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
474 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
475 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
476 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
477 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
478 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
479 },
481 /**
482 * \brief Mapping of DMA channels to Hardware Events from
483 * various peripherals, which use EDMA for data transfer.
484 * All channels need not be mapped, some can be free also.
485 */
486 {
487 0x3FFF3FFFu,
488 0x3FFF3FFFu
489 }
490 },
492 {
493 /* EDMA3 INSTANCE# 2 */
494 /** Total number of DMA Channels supported by the EDMA3 Controller */
495 64u,
496 /** Total number of QDMA Channels supported by the EDMA3 Controller */
497 8u,
498 /** Total number of TCCs supported by the EDMA3 Controller */
499 64u,
500 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
501 512u,
502 /** Total number of Event Queues in the EDMA3 Controller */
503 4u,
504 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
505 4u,
506 /** Number of Regions on this EDMA3 controller */
507 8u,
509 /**
510 * \brief Channel mapping existence
511 * A value of 0 (No channel mapping) implies that there is fixed association
512 * for a channel number to a parameter entry number or, in other words,
513 * PaRAM entry n corresponds to channel n.
514 */
515 1u,
517 /** Existence of memory protection feature */
518 1u,
520 /** Global Register Region of CC Registers */
521 (void *)0x02740000u,
522 /** Transfer Controller (TC) Registers */
523 {
524 (void *)0x02790000u,
525 (void *)0x02798000u,
526 (void *)0x027A0000u,
527 (void *)0x027A8000u,
528 (void *)NULL,
529 (void *)NULL,
530 (void *)NULL,
531 (void *)NULL
532 },
533 /** Interrupt no. for Transfer Completion */
534 24u,
535 /** Interrupt no. for CC Error */
536 16u,
537 /** Interrupt no. for TCs Error */
538 {
539 18u,
540 19u,
541 20u,
542 21u,
543 0u,
544 0u,
545 0u,
546 0u,
547 },
549 /**
550 * \brief EDMA3 TC priority setting
551 *
552 * User can program the priority of the Event Queues
553 * at a system-wide level. This means that the user can set the
554 * priority of an IO initiated by either of the TCs (Transfer Controllers)
555 * relative to IO initiated by the other bus masters on the
556 * device (ARM, DSP, USB, etc)
557 */
558 {
559 0u,
560 1u,
561 2u,
562 3u,
563 0u,
564 0u,
565 0u,
566 0u
567 },
568 /**
569 * \brief To Configure the Threshold level of number of events
570 * that can be queued up in the Event queues. EDMA3CC error register
571 * (CCERR) will indicate whether or not at any instant of time the
572 * number of events queued up in any of the event queues exceeds
573 * or equals the threshold/watermark value that is set
574 * in the queue watermark threshold register (QWMTHRA).
575 */
576 {
577 16u,
578 16u,
579 16u,
580 16u,
581 0u,
582 0u,
583 0u,
584 0u
585 },
587 /**
588 * \brief To Configure the Default Burst Size (DBS) of TCs.
589 * An optimally-sized command is defined by the transfer controller
590 * default burst size (DBS). Different TCs can have different
591 * DBS values. It is defined in Bytes.
592 */
593 {
594 64u,
595 64u,
596 64u,
597 64u,
598 0u,
599 0u,
600 0u,
601 0u
602 },
604 /**
605 * \brief Mapping from each DMA channel to a Parameter RAM set,
606 * if it exists, otherwise of no use.
607 */
608 {
609 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
610 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
611 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
612 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
613 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
614 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
615 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
616 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
617 },
619 /**
620 * \brief Mapping from each DMA channel to a TCC. This specific
621 * TCC code will be returned when the transfer is completed
622 * on the mapped channel.
623 */
624 {
625 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
626 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
627 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
628 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
629 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
630 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
631 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
632 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
633 },
635 /**
636 * \brief Mapping of DMA channels to Hardware Events from
637 * various peripherals, which use EDMA for data transfer.
638 * All channels need not be mapped, some can be free also.
639 */
640 {
641 0x3FFF3FFFu,
642 0x3FFF3FFFu
643 }
644 },
645 };
647 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
648 {
649 /* EDMA3 INSTANCE# 0 */
650 {
651 /* Resources owned/reserved by region 0 */
652 {
653 /* ownPaRAMSets */
654 /* 31 0 63 32 95 64 127 96 */
655 {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,
656 /* 159 128 191 160 223 192 255 224 */
657 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
658 /* 287 256 319 288 351 320 383 352 */
659 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
660 /* 415 384 447 416 479 448 511 480 */
661 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
663 /* ownDmaChannels */
664 /* 31 0 63 32 */
665 {0x0000000Fu, 0x00000000u},
667 /* ownQdmaChannels */
668 /* 31 0 */
669 {0x00000003u},
671 /* ownTccs */
672 /* 31 0 63 32 */
673 {0x0000000Fu, 0x00000000u},
675 /* resvdPaRAMSets */
676 /* 31 0 63 32 95 64 127 96 */
677 {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
678 /* 159 128 191 160 223 192 255 224 */
679 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
680 /* 287 256 319 288 351 320 383 352 */
681 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
682 /* 415 384 447 416 479 448 511 480 */
683 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
685 /* resvdDmaChannels */
686 /* 31 0 */
687 {0x00000003u, 0x00000000u},
689 /* resvdQdmaChannels */
690 /* 31 0 */
691 {0x00000000u},
693 /* resvdTccs */
694 /* 31 0 */
695 {0x00000003u, 0x00000000u},
696 },
698 /* Resources owned/reserved by region 1 */
699 {
700 /* ownPaRAMSets */
701 /* 31 0 63 32 95 64 127 96 */
702 {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
703 /* 159 128 191 160 223 192 255 224 */
704 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
705 /* 287 256 319 288 351 320 383 352 */
706 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
707 /* 415 384 447 416 479 448 511 480 */
708 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
710 /* ownDmaChannels */
711 /* 31 0 63 32 */
712 {0x000000F0u, 0x00000000u},
714 /* ownQdmaChannels */
715 /* 31 0 */
716 {0x0000000Cu},
718 /* ownTccs */
719 /* 31 0 63 32 */
720 {0x000000F0u, 0x00000000u},
722 /* resvdPaRAMSets */
723 /* 31 0 63 32 95 64 127 96 */
724 {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
725 /* 159 128 191 160 223 192 255 224 */
726 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
727 /* 287 256 319 288 351 320 383 352 */
728 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
729 /* 415 384 447 416 479 448 511 480 */
730 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
732 /* resvdDmaChannels */
733 /* 31 0 63 32 */
734 {0x00000030u, 0x00000000u},
736 /* resvdQdmaChannels */
737 /* 31 0 */
738 {0x00000000u},
740 /* resvdTccs */
741 /* 31 0 63 32 */
742 {0x00000030u, 0x00000000u},
743 },
745 /* Resources owned/reserved by region 2 */
746 {
747 /* ownPaRAMSets */
748 /* 31 0 63 32 95 64 127 96 */
749 {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
750 /* 159 128 191 160 223 192 255 224 */
751 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
752 /* 287 256 319 288 351 320 383 352 */
753 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
754 /* 415 384 447 416 479 448 511 480 */
755 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
757 /* ownDmaChannels */
758 /* 31 0 63 32 */
759 {0x00000F00u, 0x00000000u},
761 /* ownQdmaChannels */
762 /* 31 0 */
763 {0x00000030u},
765 /* ownTccs */
766 /* 31 0 63 32 */
767 {0x00000F00u, 0x00000000u},
769 /* resvdPaRAMSets */
770 /* 31 0 63 32 95 64 127 96 */
771 {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
772 /* 159 128 191 160 223 192 255 224 */
773 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
774 /* 287 256 319 288 351 320 383 352 */
775 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
776 /* 415 384 447 416 479 448 511 480 */
777 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
779 /* resvdDmaChannels */
780 /* 31 0 63 32 */
781 {0x00000300u, 0x00000000u},
783 /* resvdQdmaChannels */
784 /* 31 0 */
785 {0x00000000u},
787 /* resvdTccs */
788 /* 31 0 63 32 */
789 {0x00000300u, 0x00000000u},
790 },
792 /* Resources owned/reserved by region 3 */
793 {
794 /* ownPaRAMSets */
795 /* 31 0 63 32 95 64 127 96 */
796 {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
797 /* 159 128 191 160 223 192 255 224 */
798 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
799 /* 287 256 319 288 351 320 383 352 */
800 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
801 /* 415 384 447 416 479 448 511 480 */
802 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
804 /* ownDmaChannels */
805 /* 31 0 63 32 */
806 {0x0000F000u, 0x00000000u},
808 /* ownQdmaChannels */
809 /* 31 0 */
810 {0x000000C0u},
812 /* ownTccs */
813 /* 31 0 63 32 */
814 {0x0000F000u, 0x00000000u},
816 /* resvdPaRAMSets */
817 /* 31 0 63 32 95 64 127 96 */
818 {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
819 /* 159 128 191 160 223 192 255 224 */
820 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
821 /* 287 256 319 288 351 320 383 352 */
822 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
823 /* 415 384 447 416 479 448 511 480 */
824 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
826 /* resvdDmaChannels */
827 /* 31 0 63 32 */
828 {0x00003000u, 0x00000000u},
830 /* resvdQdmaChannels */
831 /* 31 0 */
832 {0x00000000u},
834 /* resvdTccs */
835 /* 31 0 63 32 */
836 {0x00003000u, 0x00000000u},
837 },
839 /* Resources owned/reserved by region 4 */
840 {
841 /* ownPaRAMSets */
842 /* 31 0 63 32 95 64 127 96 */
843 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
844 /* 159 128 191 160 223 192 255 224 */
845 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
846 /* 287 256 319 288 351 320 383 352 */
847 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
848 /* 415 384 447 416 479 448 511 480 */
849 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
851 /* ownDmaChannels */
852 /* 31 0 63 32 */
853 {0x00000000u, 0x00000000u},
855 /* ownQdmaChannels */
856 /* 31 0 */
857 {0x00000000u},
859 /* ownTccs */
860 /* 31 0 63 32 */
861 {0x00000000u, 0x00000000u},
863 /* resvdPaRAMSets */
864 /* 31 0 63 32 95 64 127 96 */
865 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
866 /* 159 128 191 160 223 192 255 224 */
867 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
868 /* 287 256 319 288 351 320 383 352 */
869 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
870 /* 415 384 447 416 479 448 511 480 */
871 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
873 /* resvdDmaChannels */
874 /* 31 0 63 32 */
875 {0x00000000u, 0x00000000u},
877 /* resvdQdmaChannels */
878 /* 31 0 */
879 {0x00000000u},
881 /* resvdTccs */
882 /* 31 0 63 32 */
883 {0x00000000u, 0x00000000u},
884 },
886 /* Resources owned/reserved by region 5 */
887 {
888 /* ownPaRAMSets */
889 /* 31 0 63 32 95 64 127 96 */
890 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
891 /* 159 128 191 160 223 192 255 224 */
892 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
893 /* 287 256 319 288 351 320 383 352 */
894 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
895 /* 415 384 447 416 479 448 511 480 */
896 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
898 /* ownDmaChannels */
899 /* 31 0 63 32 */
900 {0x00000000u, 0x00000000u},
902 /* ownQdmaChannels */
903 /* 31 0 */
904 {0x00000000u},
906 /* ownTccs */
907 /* 31 0 63 32 */
908 {0x00000000u, 0x00000000u},
910 /* resvdPaRAMSets */
911 /* 31 0 63 32 95 64 127 96 */
912 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
913 /* 159 128 191 160 223 192 255 224 */
914 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
915 /* 287 256 319 288 351 320 383 352 */
916 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
917 /* 415 384 447 416 479 448 511 480 */
918 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
920 /* resvdDmaChannels */
921 /* 31 0 63 32 */
922 {0x00000000u, 0x00000000u},
924 /* resvdQdmaChannels */
925 /* 31 0 */
926 {0x00000000u},
928 /* resvdTccs */
929 /* 31 0 63 32 */
930 {0x00000000u, 0x00000000u},
931 },
933 /* Resources owned/reserved by region 6 */
934 {
935 /* ownPaRAMSets */
936 /* 31 0 63 32 95 64 127 96 */
937 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
938 /* 159 128 191 160 223 192 255 224 */
939 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
940 /* 287 256 319 288 351 320 383 352 */
941 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
942 /* 415 384 447 416 479 448 511 480 */
943 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
945 /* ownDmaChannels */
946 /* 31 0 63 32 */
947 {0x00000000u, 0x00000000u},
949 /* ownQdmaChannels */
950 /* 31 0 */
951 {0x00000000u},
953 /* ownTccs */
954 /* 31 0 63 32 */
955 {0x00000000u, 0x00000000u},
957 /* resvdPaRAMSets */
958 /* 31 0 63 32 95 64 127 96 */
959 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
960 /* 159 128 191 160 223 192 255 224 */
961 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
962 /* 287 256 319 288 351 320 383 352 */
963 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
964 /* 415 384 447 416 479 448 511 480 */
965 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
967 /* resvdDmaChannels */
968 /* 31 0 63 32 */
969 {0x00000000u, 0x00000000u},
971 /* resvdQdmaChannels */
972 /* 31 0 */
973 {0x00000000u},
975 /* resvdTccs */
976 /* 31 0 63 32 */
977 {0x00000000u, 0x00000000u},
978 },
980 /* Resources owned/reserved by region 7 */
981 {
982 /* ownPaRAMSets */
983 /* 31 0 63 32 95 64 127 96 */
984 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
985 /* 159 128 191 160 223 192 255 224 */
986 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
987 /* 287 256 319 288 351 320 383 352 */
988 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
989 /* 415 384 447 416 479 448 511 480 */
990 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
992 /* ownDmaChannels */
993 /* 31 0 63 32 */
994 {0x00000000u, 0x00000000u},
996 /* ownQdmaChannels */
997 /* 31 0 */
998 {0x00000000u},
1000 /* ownTccs */
1001 /* 31 0 63 32 */
1002 {0x00000000u, 0x00000000u},
1004 /* resvdPaRAMSets */
1005 /* 31 0 63 32 95 64 127 96 */
1006 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1007 /* 159 128 191 160 223 192 255 224 */
1008 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1009 /* 287 256 319 288 351 320 383 352 */
1010 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1011 /* 415 384 447 416 479 448 511 480 */
1012 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1014 /* resvdDmaChannels */
1015 /* 31 0 63 32 */
1016 {0x00000000u, 0x00000000u},
1018 /* resvdQdmaChannels */
1019 /* 31 0 */
1020 {0x00000000u},
1022 /* resvdTccs */
1023 /* 31 0 63 32 */
1024 {0x00000000u, 0x00000000u},
1025 },
1026 },
1028 /* EDMA3 INSTANCE# 1 */
1029 {
1030 /* Resources owned/reserved by region 0 */
1031 {
1032 /* ownPaRAMSets */
1033 /* 31 0 63 32 95 64 127 96 */
1034 {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1035 /* 159 128 191 160 223 192 255 224 */
1036 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1037 /* 287 256 319 288 351 320 383 352 */
1038 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1039 /* 415 384 447 416 479 448 511 480 */
1040 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1042 /* ownDmaChannels */
1043 /* 31 0 63 32 */
1044 {0x0000FFFFu, 0x00000000u},
1046 /* ownQdmaChannels */
1047 /* 31 0 */
1048 {0x00000003u},
1050 /* ownTccs */
1051 /* 31 0 63 32 */
1052 {0x0000FFFFu, 0x00000000u},
1054 /* resvdPaRAMSets */
1055 /* 31 0 63 32 95 64 127 96 */
1056 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1057 /* 159 128 191 160 223 192 255 224 */
1058 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1059 /* 287 256 319 288 351 320 383 352 */
1060 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1061 /* 415 384 447 416 479 448 511 480 */
1062 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1064 /* resvdDmaChannels */
1065 /* 31 0 63 32 */
1066 {0x00003FFFu, 0x00000000u},
1068 /* resvdQdmaChannels */
1069 /* 31 0 */
1070 {0x00000000u},
1072 /* resvdTccs */
1073 /* 31 0 63 32 */
1074 {0x00003FFFu, 0x00000000u},
1075 },
1077 /* Resources owned/reserved by region 1 */
1078 {
1079 /* ownPaRAMSets */
1080 /* 31 0 63 32 95 64 127 96 */
1081 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1082 /* 159 128 191 160 223 192 255 224 */
1083 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1084 /* 287 256 319 288 351 320 383 352 */
1085 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1086 /* 415 384 447 416 479 448 511 480 */
1087 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1089 /* ownDmaChannels */
1090 /* 31 0 63 32 */
1091 {0xFFFF0000u, 0x00000000u},
1093 /* ownQdmaChannels */
1094 /* 31 0 */
1095 {0x0000000Cu},
1097 /* ownTccs */
1098 /* 31 0 63 32 */
1099 {0xFFFF0000u, 0x00000000u},
1101 /* resvdPaRAMSets */
1102 /* 31 0 63 32 95 64 127 96 */
1103 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1104 /* 159 128 191 160 223 192 255 224 */
1105 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1106 /* 287 256 319 288 351 320 383 352 */
1107 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1108 /* 415 384 447 416 479 448 511 480 */
1109 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1111 /* resvdDmaChannels */
1112 /* 31 0 63 32 */
1113 {0x3FFF0000u, 0x00000000u},
1115 /* resvdQdmaChannels */
1116 /* 31 0 */
1117 {0x00000000u},
1119 /* resvdTccs */
1120 /* 31 0 63 32 */
1121 {0x3FFF0000u, 0x00000000u},
1122 },
1124 /* Resources owned/reserved by region 2 */
1125 {
1126 /* ownPaRAMSets */
1127 /* 31 0 63 32 95 64 127 96 */
1128 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1129 /* 159 128 191 160 223 192 255 224 */
1130 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1131 /* 287 256 319 288 351 320 383 352 */
1132 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1133 /* 415 384 447 416 479 448 511 480 */
1134 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
1136 /* ownDmaChannels */
1137 /* 31 0 63 32 */
1138 {0x00000000u, 0x0000FFFFu},
1140 /* ownQdmaChannels */
1141 /* 31 0 */
1142 {0x00000030u},
1144 /* ownTccs */
1145 /* 31 0 63 32 */
1146 {0x00000000u, 0x0000FFFFu},
1148 /* resvdPaRAMSets */
1149 /* 31 0 63 32 95 64 127 96 */
1150 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
1151 /* 159 128 191 160 223 192 255 224 */
1152 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1153 /* 287 256 319 288 351 320 383 352 */
1154 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1155 /* 415 384 447 416 479 448 511 480 */
1156 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1158 /* resvdDmaChannels */
1159 /* 31 0 63 32 */
1160 {0x00000000u, 0x00003FFFu},
1162 /* resvdQdmaChannels */
1163 /* 31 0 */
1164 {0x00000000u},
1166 /* resvdTccs */
1167 /* 31 0 63 32 */
1168 {0x00000000u, 0x00003FFFu},
1169 },
1171 /* Resources owned/reserved by region 3 */
1172 {
1173 /* ownPaRAMSets */
1174 /* 31 0 63 32 95 64 127 96 */
1175 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
1176 /* 159 128 191 160 223 192 255 224 */
1177 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1178 /* 287 256 319 288 351 320 383 352 */
1179 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1180 /* 415 384 447 416 479 448 511 480 */
1181 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
1183 /* ownDmaChannels */
1184 /* 31 0 63 32 */
1185 {0x00000000u, 0xFFFF0000u},
1187 /* ownQdmaChannels */
1188 /* 31 0 */
1189 {0x000000C0u},
1191 /* ownTccs */
1192 /* 31 0 63 32 */
1193 {0x00000000u, 0xFFFF0000u},
1195 /* resvdPaRAMSets */
1196 /* 31 0 63 32 95 64 127 96 */
1197 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
1198 /* 159 128 191 160 223 192 255 224 */
1199 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1200 /* 287 256 319 288 351 320 383 352 */
1201 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1202 /* 415 384 447 416 479 448 511 480 */
1203 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1205 /* resvdDmaChannels */
1206 /* 31 0 63 32 */
1207 {0x00000000u, 0x3FFF0000u},
1209 /* resvdQdmaChannels */
1210 /* 31 0 */
1211 {0x00000000u},
1213 /* resvdTccs */
1214 /* 31 0 63 32 */
1215 {0x00000000u, 0x3FFF0000u},
1216 },
1218 /* Resources owned/reserved by region 4 */
1219 {
1220 /* ownPaRAMSets */
1221 /* 31 0 63 32 95 64 127 96 */
1222 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1223 /* 159 128 191 160 223 192 255 224 */
1224 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1225 /* 287 256 319 288 351 320 383 352 */
1226 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1227 /* 415 384 447 416 479 448 511 480 */
1228 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1230 /* ownDmaChannels */
1231 /* 31 0 63 32 */
1232 {0x00000000u, 0x00000000u},
1234 /* ownQdmaChannels */
1235 /* 31 0 */
1236 {0x00000000u},
1238 /* ownTccs */
1239 /* 31 0 63 32 */
1240 {0x00000000u, 0x00000000u},
1242 /* resvdPaRAMSets */
1243 /* 31 0 63 32 95 64 127 96 */
1244 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1245 /* 159 128 191 160 223 192 255 224 */
1246 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1247 /* 287 256 319 288 351 320 383 352 */
1248 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1249 /* 415 384 447 416 479 448 511 480 */
1250 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1252 /* resvdDmaChannels */
1253 /* 31 0 63 32 */
1254 {0x00000000u, 0x00000000u},
1256 /* resvdQdmaChannels */
1257 /* 31 0 */
1258 {0x00000000u},
1260 /* resvdTccs */
1261 /* 31 0 63 32 */
1262 {0x00000000u, 0x00000000u},
1263 },
1265 /* Resources owned/reserved by region 5 */
1266 {
1267 /* ownPaRAMSets */
1268 /* 31 0 63 32 95 64 127 96 */
1269 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1270 /* 159 128 191 160 223 192 255 224 */
1271 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1272 /* 287 256 319 288 351 320 383 352 */
1273 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1274 /* 415 384 447 416 479 448 511 480 */
1275 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1277 /* ownDmaChannels */
1278 /* 31 0 63 32 */
1279 {0x00000000u, 0x00000000u},
1281 /* ownQdmaChannels */
1282 /* 31 0 */
1283 {0x00000000u},
1285 /* ownTccs */
1286 /* 31 0 63 32 */
1287 {0x00000000u, 0x00000000u},
1289 /* resvdPaRAMSets */
1290 /* 31 0 63 32 95 64 127 96 */
1291 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1292 /* 159 128 191 160 223 192 255 224 */
1293 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1294 /* 287 256 319 288 351 320 383 352 */
1295 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1296 /* 415 384 447 416 479 448 511 480 */
1297 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1299 /* resvdDmaChannels */
1300 /* 31 0 63 32 */
1301 {0x00000000u, 0x00000000u},
1303 /* resvdQdmaChannels */
1304 /* 31 0 */
1305 {0x00000000u},
1307 /* resvdTccs */
1308 /* 31 0 63 32 */
1309 {0x00000000u, 0x00000000u},
1310 },
1312 /* Resources owned/reserved by region 6 */
1313 {
1314 /* ownPaRAMSets */
1315 /* 31 0 63 32 95 64 127 96 */
1316 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1317 /* 159 128 191 160 223 192 255 224 */
1318 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1319 /* 287 256 319 288 351 320 383 352 */
1320 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1321 /* 415 384 447 416 479 448 511 480 */
1322 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1324 /* ownDmaChannels */
1325 /* 31 0 63 32 */
1326 {0x00000000u, 0x00000000u},
1328 /* ownQdmaChannels */
1329 /* 31 0 */
1330 {0x00000000u},
1332 /* ownTccs */
1333 /* 31 0 63 32 */
1334 {0x00000000u, 0x00000000u},
1336 /* resvdPaRAMSets */
1337 /* 31 0 63 32 95 64 127 96 */
1338 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1339 /* 159 128 191 160 223 192 255 224 */
1340 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1341 /* 287 256 319 288 351 320 383 352 */
1342 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1343 /* 415 384 447 416 479 448 511 480 */
1344 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1346 /* resvdDmaChannels */
1347 /* 31 0 63 32 */
1348 {0x00000000u, 0x00000000u},
1350 /* resvdQdmaChannels */
1351 /* 31 0 */
1352 {0x00000000u},
1354 /* resvdTccs */
1355 /* 31 0 63 32 */
1356 {0x00000000u, 0x00000000u},
1357 },
1359 /* Resources owned/reserved by region 7 */
1360 {
1361 /* ownPaRAMSets */
1362 /* 31 0 63 32 95 64 127 96 */
1363 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1364 /* 159 128 191 160 223 192 255 224 */
1365 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1366 /* 287 256 319 288 351 320 383 352 */
1367 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1368 /* 415 384 447 416 479 448 511 480 */
1369 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1371 /* ownDmaChannels */
1372 /* 31 0 63 32 */
1373 {0x00000000u, 0x00000000u},
1375 /* ownQdmaChannels */
1376 /* 31 0 */
1377 {0x00000000u},
1379 /* ownTccs */
1380 /* 31 0 63 32 */
1381 {0x00000000u, 0x00000000u},
1383 /* resvdPaRAMSets */
1384 /* 31 0 63 32 95 64 127 96 */
1385 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1386 /* 159 128 191 160 223 192 255 224 */
1387 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1388 /* 287 256 319 288 351 320 383 352 */
1389 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1390 /* 415 384 447 416 479 448 511 480 */
1391 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1393 /* resvdDmaChannels */
1394 /* 31 0 63 32 */
1395 {0x00000000u, 0x00000000u},
1397 /* resvdQdmaChannels */
1398 /* 31 0 */
1399 {0x00000000u},
1401 /* resvdTccs */
1402 /* 31 0 63 32 */
1403 {0x00000000u, 0x00000000u},
1404 },
1405 },
1407 /* EDMA3 INSTANCE# 2 */
1408 {
1409 /* Resources owned/reserved by region 0 */
1410 {
1411 /* ownPaRAMSets */
1412 /* 31 0 63 32 95 64 127 96 */
1413 {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1414 /* 159 128 191 160 223 192 255 224 */
1415 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1416 /* 287 256 319 288 351 320 383 352 */
1417 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1418 /* 415 384 447 416 479 448 511 480 */
1419 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1421 /* ownDmaChannels */
1422 /* 31 0 63 32 */
1423 {0x0000FFFFu, 0x00000000u},
1425 /* ownQdmaChannels */
1426 /* 31 0 */
1427 {0x00000003u},
1429 /* ownTccs */
1430 /* 31 0 63 32 */
1431 {0x0000FFFFu, 0x00000000u},
1433 /* resvdPaRAMSets */
1434 /* 31 0 63 32 95 64 127 96 */
1435 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1436 /* 159 128 191 160 223 192 255 224 */
1437 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1438 /* 287 256 319 288 351 320 383 352 */
1439 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1440 /* 415 384 447 416 479 448 511 480 */
1441 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1443 /* resvdDmaChannels */
1444 /* 31 0 63 32 */
1445 {0x00003FFFu, 0x00000000u},
1447 /* resvdQdmaChannels */
1448 /* 31 0 */
1449 {0x00000000u},
1451 /* resvdTccs */
1452 /* 31 0 63 32 */
1453 {0x00003FFFu, 0x00000000u},
1454 },
1456 /* Resources owned/reserved by region 1 */
1457 {
1458 /* ownPaRAMSets */
1459 /* 31 0 63 32 95 64 127 96 */
1460 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1461 /* 159 128 191 160 223 192 255 224 */
1462 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1463 /* 287 256 319 288 351 320 383 352 */
1464 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1465 /* 415 384 447 416 479 448 511 480 */
1466 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1468 /* ownDmaChannels */
1469 /* 31 0 63 32 */
1470 {0xFFFF0000u, 0x00000000u},
1472 /* ownQdmaChannels */
1473 /* 31 0 */
1474 {0x0000000Cu},
1476 /* ownTccs */
1477 /* 31 0 63 32 */
1478 {0xFFFF0000u, 0x00000000u},
1480 /* resvdPaRAMSets */
1481 /* 31 0 63 32 95 64 127 96 */
1482 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1483 /* 159 128 191 160 223 192 255 224 */
1484 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1485 /* 287 256 319 288 351 320 383 352 */
1486 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1487 /* 415 384 447 416 479 448 511 480 */
1488 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1490 /* resvdDmaChannels */
1491 /* 31 0 63 32 */
1492 {0x3FFF0000u, 0x00000000u},
1494 /* resvdQdmaChannels */
1495 /* 31 0 */
1496 {0x00000000u},
1498 /* resvdTccs */
1499 /* 31 0 63 32 */
1500 {0x3FFF0000u, 0x00000000u},
1501 },
1503 /* Resources owned/reserved by region 2 */
1504 {
1505 /* ownPaRAMSets */
1506 /* 31 0 63 32 95 64 127 96 */
1507 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1508 /* 159 128 191 160 223 192 255 224 */
1509 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1510 /* 287 256 319 288 351 320 383 352 */
1511 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1512 /* 415 384 447 416 479 448 511 480 */
1513 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
1515 /* ownDmaChannels */
1516 /* 31 0 63 32 */
1517 {0x00000000u, 0x0000FFFFu},
1519 /* ownQdmaChannels */
1520 /* 31 0 */
1521 {0x00000030u},
1523 /* ownTccs */
1524 /* 31 0 63 32 */
1525 {0x00000000u, 0x0000FFFFu},
1527 /* resvdPaRAMSets */
1528 /* 31 0 63 32 95 64 127 96 */
1529 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
1530 /* 159 128 191 160 223 192 255 224 */
1531 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1532 /* 287 256 319 288 351 320 383 352 */
1533 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1534 /* 415 384 447 416 479 448 511 480 */
1535 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1537 /* resvdDmaChannels */
1538 /* 31 0 63 32 */
1539 {0x00000000u, 0x00003FFFu},
1541 /* resvdQdmaChannels */
1542 /* 31 0 */
1543 {0x00000000u},
1545 /* resvdTccs */
1546 /* 31 0 63 32 */
1547 {0x00000000u, 0x00003FFFu},
1548 },
1550 /* Resources owned/reserved by region 3 */
1551 {
1552 /* ownPaRAMSets */
1553 /* 31 0 63 32 95 64 127 96 */
1554 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
1555 /* 159 128 191 160 223 192 255 224 */
1556 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1557 /* 287 256 319 288 351 320 383 352 */
1558 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1559 /* 415 384 447 416 479 448 511 480 */
1560 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
1562 /* ownDmaChannels */
1563 /* 31 0 63 32 */
1564 {0x00000000u, 0xFFFF0000u},
1566 /* ownQdmaChannels */
1567 /* 31 0 */
1568 {0x000000C0u},
1570 /* ownTccs */
1571 /* 31 0 63 32 */
1572 {0x00000000u, 0xFFFF0000u},
1574 /* resvdPaRAMSets */
1575 /* 31 0 63 32 95 64 127 96 */
1576 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
1577 /* 159 128 191 160 223 192 255 224 */
1578 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1579 /* 287 256 319 288 351 320 383 352 */
1580 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1581 /* 415 384 447 416 479 448 511 480 */
1582 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1584 /* resvdDmaChannels */
1585 /* 31 0 63 32 */
1586 {0x00000000u, 0x3FFF0000u},
1588 /* resvdQdmaChannels */
1589 /* 31 0 */
1590 {0x00000000u},
1592 /* resvdTccs */
1593 /* 31 0 63 32 */
1594 {0x00000000u, 0x3FFF0000u},
1595 },
1597 /* Resources owned/reserved by region 4 */
1598 {
1599 /* ownPaRAMSets */
1600 /* 31 0 63 32 95 64 127 96 */
1601 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1602 /* 159 128 191 160 223 192 255 224 */
1603 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1604 /* 287 256 319 288 351 320 383 352 */
1605 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1606 /* 415 384 447 416 479 448 511 480 */
1607 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1609 /* ownDmaChannels */
1610 /* 31 0 63 32 */
1611 {0x00000000u, 0x00000000u},
1613 /* ownQdmaChannels */
1614 /* 31 0 */
1615 {0x00000000u},
1617 /* ownTccs */
1618 /* 31 0 63 32 */
1619 {0x00000000u, 0x00000000u},
1621 /* resvdPaRAMSets */
1622 /* 31 0 63 32 95 64 127 96 */
1623 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1624 /* 159 128 191 160 223 192 255 224 */
1625 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1626 /* 287 256 319 288 351 320 383 352 */
1627 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1628 /* 415 384 447 416 479 448 511 480 */
1629 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1631 /* resvdDmaChannels */
1632 /* 31 0 63 32 */
1633 {0x00000000u, 0x00000000u},
1635 /* resvdQdmaChannels */
1636 /* 31 0 */
1637 {0x00000000u},
1639 /* resvdTccs */
1640 /* 31 0 63 32 */
1641 {0x00000000u, 0x00000000u},
1642 },
1644 /* Resources owned/reserved by region 5 */
1645 {
1646 /* ownPaRAMSets */
1647 /* 31 0 63 32 95 64 127 96 */
1648 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1649 /* 159 128 191 160 223 192 255 224 */
1650 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1651 /* 287 256 319 288 351 320 383 352 */
1652 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1653 /* 415 384 447 416 479 448 511 480 */
1654 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1656 /* ownDmaChannels */
1657 /* 31 0 63 32 */
1658 {0x00000000u, 0x00000000u},
1660 /* ownQdmaChannels */
1661 /* 31 0 */
1662 {0x00000000u},
1664 /* ownTccs */
1665 /* 31 0 63 32 */
1666 {0x00000000u, 0x00000000u},
1668 /* resvdPaRAMSets */
1669 /* 31 0 63 32 95 64 127 96 */
1670 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1671 /* 159 128 191 160 223 192 255 224 */
1672 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1673 /* 287 256 319 288 351 320 383 352 */
1674 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1675 /* 415 384 447 416 479 448 511 480 */
1676 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1678 /* resvdDmaChannels */
1679 /* 31 0 63 32 */
1680 {0x00000000u, 0x00000000u},
1682 /* resvdQdmaChannels */
1683 /* 31 0 */
1684 {0x00000000u},
1686 /* resvdTccs */
1687 /* 31 0 63 32 */
1688 {0x00000000u, 0x00000000u},
1689 },
1691 /* Resources owned/reserved by region 6 */
1692 {
1693 /* ownPaRAMSets */
1694 /* 31 0 63 32 95 64 127 96 */
1695 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1696 /* 159 128 191 160 223 192 255 224 */
1697 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1698 /* 287 256 319 288 351 320 383 352 */
1699 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1700 /* 415 384 447 416 479 448 511 480 */
1701 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1703 /* ownDmaChannels */
1704 /* 31 0 63 32 */
1705 {0x00000000u, 0x00000000u},
1707 /* ownQdmaChannels */
1708 /* 31 0 */
1709 {0x00000000u},
1711 /* ownTccs */
1712 /* 31 0 63 32 */
1713 {0x00000000u, 0x00000000u},
1715 /* resvdPaRAMSets */
1716 /* 31 0 63 32 95 64 127 96 */
1717 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1718 /* 159 128 191 160 223 192 255 224 */
1719 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1720 /* 287 256 319 288 351 320 383 352 */
1721 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1722 /* 415 384 447 416 479 448 511 480 */
1723 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1725 /* resvdDmaChannels */
1726 /* 31 0 63 32 */
1727 {0x00000000u, 0x00000000u},
1729 /* resvdQdmaChannels */
1730 /* 31 0 */
1731 {0x00000000u},
1733 /* resvdTccs */
1734 /* 31 0 63 32 */
1735 {0x00000000u, 0x00000000u},
1736 },
1738 /* Resources owned/reserved by region 7 */
1739 {
1740 /* ownPaRAMSets */
1741 /* 31 0 63 32 95 64 127 96 */
1742 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1743 /* 159 128 191 160 223 192 255 224 */
1744 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1745 /* 287 256 319 288 351 320 383 352 */
1746 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1747 /* 415 384 447 416 479 448 511 480 */
1748 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1750 /* ownDmaChannels */
1751 /* 31 0 63 32 */
1752 {0x00000000u, 0x00000000u},
1754 /* ownQdmaChannels */
1755 /* 31 0 */
1756 {0x00000000u},
1758 /* ownTccs */
1759 /* 31 0 63 32 */
1760 {0x00000000u, 0x00000000u},
1762 /* resvdPaRAMSets */
1763 /* 31 0 63 32 95 64 127 96 */
1764 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1765 /* 159 128 191 160 223 192 255 224 */
1766 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1767 /* 287 256 319 288 351 320 383 352 */
1768 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1769 /* 415 384 447 416 479 448 511 480 */
1770 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1772 /* resvdDmaChannels */
1773 /* 31 0 63 32 */
1774 {0x00000000u, 0x00000000u},
1776 /* resvdQdmaChannels */
1777 /* 31 0 */
1778 {0x00000000u},
1780 /* resvdTccs */
1781 /* 31 0 63 32 */
1782 {0x00000000u, 0x00000000u},
1783 },
1784 },
1785 };
1787 /* End of File */