71f8a43346f72e2d2eb8934af012ec373fb56cbe
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_c6678_int_reg.c
1 /*
2 * sample_c6678_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/family/c64p/Hwi.h>
41 #include <ti/sysbios/family/c64p/EventCombiner.h>
42 #include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
44 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
46 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
47 extern unsigned int ccErrorInt[];
48 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
49 extern unsigned int numEdma3Tc[];
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
52 {
53 &lisrEdma3TC0ErrHandler0,
54 &lisrEdma3TC1ErrHandler0,
55 &lisrEdma3TC2ErrHandler0,
56 &lisrEdma3TC3ErrHandler0,
57 &lisrEdma3TC4ErrHandler0,
58 &lisrEdma3TC5ErrHandler0,
59 &lisrEdma3TC6ErrHandler0,
60 &lisrEdma3TC7ErrHandler0,
61 };
63 unsigned int hwiInterrupt = 8;
65 /* Host interrupts for transfer completion */
66 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
67 unsigned int ccXferHostInt[3][8] = {
68 {2u, 10u, 18u, 26u, 2u, 10u, 18u, 26u},
69 {3u, 11u, 19u, 27u, 3u, 11u, 19u, 27u},
70 {4u, 12u, 20u, 28u, 4u, 12u, 20u, 28u},
71 };
72 unsigned int edma3ErrHostInt[3][8] = {
73 {5u, 13u, 21u, 29u, 5u, 13u, 21u, 29u},
74 {6u, 14u, 22u, 30u, 6u, 14u, 22u, 30u},
75 {7u, 15u, 23u, 31u, 7u, 15u, 23u, 31u},
76 };
79 extern unsigned int dsp_num;
81 /** To Register the ISRs with the underlying OS, if required */
82 void registerEdma3Interrupts (unsigned int edma3Id)
83 {
84 static UInt32 cookie = 0;
85 Int eventId = 0; /* GEM event id */
86 unsigned int numTc = 0;
87 UInt cpIntcId= 0;
88 if (dsp_num > 3)
89 {
90 cpIntcId = 1;
91 }
93 /* Disabling the global interrupts */
94 cookie = Hwi_disable();
96 /* Transfer completion ISR */
97 CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
98 lisrEdma3ComplHandler0,
99 edma3Id,
100 TRUE);
101 CpIntc_mapSysIntToHostInt(cpIntcId, ccXferCompInt[edma3Id][dsp_num],
102 ccXferHostInt[edma3Id][dsp_num]);
103 CpIntc_enableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
104 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
105 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
106 ccXferHostInt[edma3Id][dsp_num], TRUE);
108 /* CC Error ISR */
109 CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
110 edma3Id, TRUE);
111 CpIntc_mapSysIntToHostInt(cpIntcId, ccErrorInt[edma3Id],
112 edma3ErrHostInt[edma3Id][dsp_num]);
113 /* TC Error ISR */
114 while (numTc < numEdma3Tc[edma3Id])
115 {
116 CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
117 (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
118 edma3Id, TRUE);
119 CpIntc_mapSysIntToHostInt(cpIntcId, tcErrorInt[edma3Id][numTc],
120 edma3ErrHostInt[edma3Id][dsp_num]);
121 numTc++;
122 }
123 /* Enable the host interrupt which is common for both CC and TC error */
124 CpIntc_enableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
125 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
126 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
127 edma3ErrHostInt[edma3Id][dsp_num], TRUE);
129 Hwi_enableInterrupt(hwiInterrupt);
131 /* enable the 'global' switch */
132 CpIntc_enableAllHostInts(cpIntcId);
134 /* Restore interrupts */
135 Hwi_restore(cookie);
136 }
138 /** To Unregister the ISRs with the underlying OS, if previously registered. */
139 void unregisterEdma3Interrupts (unsigned int edma3Id)
140 {
141 static UInt32 cookie = 0;
142 Int eventId = 0; /* GEM event id */
143 UInt cpIntcId= 0;
144 if (dsp_num > 3)
145 {
146 cpIntcId = 1;
147 }
149 /* Disabling the global interrupts */
150 cookie = Hwi_disable();
152 /* Transfer completion ISR */
153 CpIntc_disableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
154 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
155 EventCombiner_disableEvent(eventId);
157 /* CC/TC Error ISR */
158 CpIntc_disableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
159 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
160 EventCombiner_disableEvent(eventId);
162 /* Restore interrupts */
163 Hwi_restore(cookie);
164 }