[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_c6748_cfg.c
1 /*
2 * sample_c6748_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 2u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54 return 1;
55 }
57 unsigned short isGblConfigRequired(unsigned int dspNum)
58 {
59 (void) dspNum;
61 return 1;
62 }
64 /* Semaphore handles */
65 EDMA3_OS_Sem_Handle rmSemHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL};
67 /** Number of PaRAM Sets available */
68 #define EDMA3_NUM_PARAMSET (128u)
69 /** Number of TCCS available */
70 #define EDMA3_NUM_TCC (32u)
72 /** Number of Event Queues available */
73 #define EDMA3_0_NUM_EVTQUE (2u)
74 #define EDMA3_1_NUM_EVTQUE (1u)
76 /** Number of Transfer Controllers available */
77 #define EDMA3_0_NUM_TC (2u)
78 #define EDMA3_1_NUM_TC (1u)
81 /** Interrupt no. for Transfer Completion */
82 #define EDMA3_0_CC_XFER_COMPLETION_INT (8u)
83 #define EDMA3_1_CC_XFER_COMPLETION_INT (91u)
85 /** Interrupt no. for CC Error */
86 #define EDMA3_0_CC_ERROR_INT (56u)
87 #define EDMA3_1_CC_ERROR_INT (92u)
89 /** Interrupt no. for TCs Error */
90 #define EDMA3_0_TC0_ERROR_INT (57u)
91 #define EDMA3_0_TC1_ERROR_INT (58u)
92 #define EDMA3_0_TC2_ERROR_INT (0u)
93 #define EDMA3_0_TC3_ERROR_INT (0u)
94 #define EDMA3_0_TC4_ERROR_INT (0u)
95 #define EDMA3_0_TC5_ERROR_INT (0u)
96 #define EDMA3_0_TC6_ERROR_INT (0u)
97 #define EDMA3_0_TC7_ERROR_INT (0u)
99 #define EDMA3_1_TC0_ERROR_INT (93u)
100 #define EDMA3_1_TC1_ERROR_INT (0u)
101 #define EDMA3_1_TC2_ERROR_INT (0u)
102 #define EDMA3_1_TC3_ERROR_INT (0u)
103 #define EDMA3_1_TC4_ERROR_INT (0u)
104 #define EDMA3_1_TC5_ERROR_INT (0u)
105 #define EDMA3_1_TC6_ERROR_INT (0u)
106 #define EDMA3_1_TC7_ERROR_INT (0u)
108 /**
109 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
110 * ECM events (SoC specific). These ECM events come
111 * under ECM block XXX (handling those specific ECM events). Normally, block
112 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
113 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
114 * is mapped to a specific HWI_INT YYY in the tcf file.
115 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
116 * to transfer completion interrupt.
117 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
118 * to CC error interrupts.
119 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
120 * to TC error interrupts.
121 */
122 /* EDMA 0 */
123 #define EDMA3_0_HWI_INT_XFER_COMP (7u)
124 #define EDMA3_0_HWI_INT_CC_ERR (8u)
125 #define EDMA3_0_HWI_INT_TC0_ERR (8u)
126 #define EDMA3_0_HWI_INT_TC1_ERR (8u)
128 /* EDMA 1 */
129 #define EDMA3_1_HWI_INT_XFER_COMP (9u)
130 #define EDMA3_1_HWI_INT_CC_ERR (9u)
131 #define EDMA3_1_HWI_INT_TC0_ERR (9u)
133 /**
134 * \brief Mapping of DMA channels 0-31 to Hardware Events from
135 * various peripherals, which use EDMA for data transfer.
136 * All channels need not be mapped, some can be free also.
137 * 1: Mapped
138 * 0: Not mapped
139 *
140 * This mapping will be used to allocate DMA channels when user passes
141 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
142 * copy). The same mapping is used to allocate the TCC when user passes
143 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
144 *
145 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
146 */
147 /* 31 0 */
148 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFF3FF3FFu)
149 #define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x3F07FFFFu)
151 /**
152 * \brief Mapping of DMA channels 32-63 to Hardware Events from
153 * various peripherals, which use EDMA for data transfer.
154 * All channels need not be mapped, some can be free also.
155 * 1: Mapped
156 * 0: Not mapped
157 *
158 * This mapping will be used to allocate DMA channels when user passes
159 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
160 * copy). The same mapping is used to allocate the TCC when user passes
161 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
162 *
163 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
164 */
165 /* DMA channels 32-63 DOES NOT exist in C6748. */
166 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u)
167 #define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u)
169 /* Variable which will be used internally for referring number of Event Queues*/
170 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
171 EDMA3_0_NUM_EVTQUE,
172 EDMA3_1_NUM_EVTQUE
173 };
175 /* Variable which will be used internally for referring number of TCs. */
176 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {
177 EDMA3_0_NUM_TC,
178 EDMA3_1_NUM_TC
179 };
181 /**
182 * Variable which will be used internally for referring transfer completion
183 * interrupt.
184 */
185 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
186 {
187 0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
188 },
189 {
190 0u, EDMA3_1_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
191 },
192 };
194 /**
195 * Variable which will be used internally for referring channel controller's
196 * error interrupt.
197 */
198 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
199 EDMA3_0_CC_ERROR_INT,
200 EDMA3_1_CC_ERROR_INT
201 };
203 /**
204 * Variable which will be used internally for referring transfer controllers'
205 * error interrupts.
206 */
207 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
208 {
209 EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
210 EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
211 EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
212 EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
213 },
214 {
215 EDMA3_1_TC0_ERROR_INT, EDMA3_1_TC1_ERROR_INT,
216 EDMA3_1_TC2_ERROR_INT, EDMA3_1_TC3_ERROR_INT,
217 EDMA3_1_TC4_ERROR_INT, EDMA3_1_TC5_ERROR_INT,
218 EDMA3_1_TC6_ERROR_INT, EDMA3_1_TC7_ERROR_INT,
219 }
220 };
222 /**
223 * Variables which will be used internally for referring the hardware interrupt
224 * for various EDMA3 interrupts.
225 */
226 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
227 EDMA3_0_HWI_INT_XFER_COMP,
228 EDMA3_1_HWI_INT_XFER_COMP
229 };
231 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
232 EDMA3_0_HWI_INT_CC_ERR,
233 EDMA3_1_HWI_INT_CC_ERR
234 };
236 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
237 {
238 EDMA3_0_HWI_INT_TC0_ERR,
239 EDMA3_0_HWI_INT_TC1_ERR,
240 },
241 {
242 EDMA3_1_HWI_INT_TC0_ERR,
243 }
244 };
246 /* Driver Object Initialization Configuration */
247 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
248 {
249 {
250 /* EDMA3 INSTANCE# 0 */
251 /** Total number of DMA Channels supported by the EDMA3 Controller */
252 32u,
253 /** Total number of QDMA Channels supported by the EDMA3 Controller */
254 8u,
255 /** Total number of TCCs supported by the EDMA3 Controller */
256 32u,
257 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
258 128u,
259 /** Total number of Event Queues in the EDMA3 Controller */
260 2u,
261 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
262 2u,
263 /** Number of Regions on this EDMA3 controller */
264 4u,
266 /**
267 * \brief Channel mapping existence
268 * A value of 0 (No channel mapping) implies that there is fixed association
269 * for a channel number to a parameter entry number or, in other words,
270 * PaRAM entry n corresponds to channel n.
271 */
272 0u,
274 /** Existence of memory protection feature */
275 0u,
277 /** Global Register Region of CC Registers */
278 (void *)0x01C00000u,
279 /** Transfer Controller (TC) Registers */
280 {
281 (void *)0x01C08000u,
282 (void *)0x01C08400u,
283 (void *)NULL,
284 (void *)NULL,
285 (void *)NULL,
286 (void *)NULL,
287 (void *)NULL,
288 (void *)NULL
289 },
290 /** Interrupt no. for Transfer Completion */
291 EDMA3_0_CC_XFER_COMPLETION_INT,
292 /** Interrupt no. for CC Error */
293 EDMA3_0_CC_ERROR_INT,
294 /** Interrupt no. for TCs Error */
295 {
296 EDMA3_0_TC0_ERROR_INT,
297 EDMA3_0_TC1_ERROR_INT,
298 EDMA3_0_TC2_ERROR_INT,
299 EDMA3_0_TC3_ERROR_INT,
300 EDMA3_0_TC4_ERROR_INT,
301 EDMA3_0_TC5_ERROR_INT,
302 EDMA3_0_TC6_ERROR_INT,
303 EDMA3_0_TC7_ERROR_INT
304 },
306 /**
307 * \brief EDMA3 TC priority setting
308 *
309 * User can program the priority of the Event Queues
310 * at a system-wide level. This means that the user can set the
311 * priority of an IO initiated by either of the TCs (Transfer Controllers)
312 * relative to IO initiated by the other bus masters on the
313 * device (ARM, DSP, USB, etc)
314 */
315 {
316 0u,
317 1u,
318 0u,
319 0u,
320 0u,
321 0u,
322 0u,
323 0u
324 },
325 /**
326 * \brief To Configure the Threshold level of number of events
327 * that can be queued up in the Event queues. EDMA3CC error register
328 * (CCERR) will indicate whether or not at any instant of time the
329 * number of events queued up in any of the event queues exceeds
330 * or equals the threshold/watermark value that is set
331 * in the queue watermark threshold register (QWMTHRA).
332 */
333 {
334 16u,
335 16u,
336 0u,
337 0u,
338 0u,
339 0u,
340 0u,
341 0u
342 },
344 /**
345 * \brief To Configure the Default Burst Size (DBS) of TCs.
346 * An optimally-sized command is defined by the transfer controller
347 * default burst size (DBS). Different TCs can have different
348 * DBS values. It is defined in Bytes.
349 */
350 {
351 16u,
352 16u,
353 0u,
354 0u,
355 0u,
356 0u,
357 0u,
358 0u
359 },
361 /**
362 * \brief Mapping from each DMA channel to a Parameter RAM set,
363 * if it exists, otherwise of no use.
364 */
365 {
366 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
367 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
368 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
369 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
370 /* DMA channels 32-63 DOES NOT exist in C6748. */
371 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
372 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
373 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
374 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
375 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
376 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
377 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
378 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
379 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
380 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
381 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
382 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
383 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
384 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
385 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
386 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
387 },
389 /**
390 * \brief Mapping from each DMA channel to a TCC. This specific
391 * TCC code will be returned when the transfer is completed
392 * on the mapped channel.
393 */
394 {
395 0u, 1u, 2u, 3u,
396 4u, 5u, 6u, 7u,
397 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
398 12u, 13u, 14u, 15u,
399 16u, 17u, 18u, 19u,
400 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
401 24u, 25u, 26u, 27u,
402 28u, 29u, 30u, 31u,
403 /* DMA channels 32-63 DOES NOT exist in C6748. */
404 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
405 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
406 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
407 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
408 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
409 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
410 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
411 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
412 },
414 /**
415 * \brief Mapping of DMA channels to Hardware Events from
416 * various peripherals, which use EDMA for data transfer.
417 * All channels need not be mapped, some can be free also.
418 */
419 {
420 EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
421 EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
422 }
423 },
425 {
426 /* EDMA3 INSTANCE# 1 */
427 /** Total number of DMA Channels supported by the EDMA3 Controller */
428 32u,
429 /** Total number of QDMA Channels supported by the EDMA3 Controller */
430 8u,
431 /** Total number of TCCs supported by the EDMA3 Controller */
432 32u,
433 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
434 128u,
435 /** Total number of Event Queues in the EDMA3 Controller */
436 1u,
437 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
438 1u,
439 /** Number of Regions on this EDMA3 controller */
440 4u,
442 /**
443 * \brief Channel mapping existence
444 * A value of 0 (No channel mapping) implies that there is fixed association
445 * for a channel number to a parameter entry number or, in other words,
446 * PaRAM entry n corresponds to channel n.
447 */
448 0u,
450 /** Existence of memory protection feature */
451 0u,
453 /** Global Register Region of CC Registers */
454 (void *)0x01E30000u,
455 /** Transfer Controller (TC) Registers */
456 {
457 (void *)0x01E38000u,
458 (void *)NULL,
459 (void *)NULL,
460 (void *)NULL,
461 (void *)NULL,
462 (void *)NULL,
463 (void *)NULL,
464 (void *)NULL
465 },
466 /** Interrupt no. for Transfer Completion */
467 EDMA3_1_CC_XFER_COMPLETION_INT,
468 /** Interrupt no. for CC Error */
469 EDMA3_1_CC_ERROR_INT,
470 /** Interrupt no. for TCs Error */
471 {
472 EDMA3_1_TC0_ERROR_INT,
473 EDMA3_1_TC1_ERROR_INT,
474 EDMA3_1_TC2_ERROR_INT,
475 EDMA3_1_TC3_ERROR_INT,
476 EDMA3_1_TC4_ERROR_INT,
477 EDMA3_1_TC5_ERROR_INT,
478 EDMA3_1_TC6_ERROR_INT,
479 EDMA3_1_TC7_ERROR_INT,
480 },
482 /**
483 * \brief EDMA3 TC priority setting
484 *
485 * User can program the priority of the Event Queues
486 * at a system-wide level. This means that the user can set the
487 * priority of an IO initiated by either of the TCs (Transfer Controllers)
488 * relative to IO initiated by the other bus masters on the
489 * device (ARM, DSP, USB, etc)
490 */
491 {
492 0u,
493 0u,
494 0u,
495 0u,
496 0u,
497 0u,
498 0u,
499 0u
500 },
501 /**
502 * \brief To Configure the Threshold level of number of events
503 * that can be queued up in the Event queues. EDMA3CC error register
504 * (CCERR) will indicate whether or not at any instant of time the
505 * number of events queued up in any of the event queues exceeds
506 * or equals the threshold/watermark value that is set
507 * in the queue watermark threshold register (QWMTHRA).
508 */
509 {
510 16u,
511 0u,
512 0u,
513 0u,
514 0u,
515 0u,
516 0u,
517 0u
518 },
520 /**
521 * \brief To Configure the Default Burst Size (DBS) of TCs.
522 * An optimally-sized command is defined by the transfer controller
523 * default burst size (DBS). Different TCs can have different
524 * DBS values. It is defined in Bytes.
525 */
526 {
527 16u,
528 0u,
529 0u,
530 0u,
531 0u,
532 0u,
533 0u,
534 0u
535 },
537 /**
538 * \brief Mapping from each DMA channel to a Parameter RAM set,
539 * if it exists, otherwise of no use.
540 */
541 {
542 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
543 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
544 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
545 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
546 /* DMA channels 32-63 DOES NOT exist in C6748. */
547 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
548 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
549 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
550 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
551 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
552 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
553 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
554 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
555 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
556 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
557 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
558 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
559 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
560 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
561 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
562 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
563 },
565 /**
566 * \brief Mapping from each DMA channel to a TCC. This specific
567 * TCC code will be returned when the transfer is completed
568 * on the mapped channel.
569 */
570 {
571 0u, 1u, 2u, 3u,
572 4u, 5u, 6u, 7u,
573 8u, 9u, 10u, 11u,
574 12u, 13u, 14u, 15u,
575 16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP,
576 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
577 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
578 24u, 25u, 26u, 27u,
579 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
580 /* DMA channels 32-63 DOES NOT exist in C6748. */
581 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
582 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
583 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
584 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
585 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
586 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
587 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
588 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
589 },
591 /**
592 * \brief Mapping of DMA channels to Hardware Events from
593 * various peripherals, which use EDMA for data transfer.
594 * All channels need not be mapped, some can be free also.
595 */
596 {
597 EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
598 EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
599 }
600 },
601 };
604 /* Driver Instance Initialization Configuration */
605 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
606 {
607 /* EDMA3 INSTANCE# 0 */
608 {
609 /* Resources owned/reserved by region 0 */
610 {
611 /* ownPaRAMSets */
612 /* 31 0 63 32 95 64 127 96 */
613 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
614 /* 159 128 191 160 223 192 255 224 */
615 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
616 /* 287 256 319 288 351 320 383 352 */
617 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
618 /* 415 384 447 416 479 448 511 480 */
619 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
621 /* ownDmaChannels */
622 /* 31 0 63 32 */
623 {0x00000000u, 0x00000000u},
625 /* ownQdmaChannels */
626 /* 31 0 */
627 {0x00000000u},
629 /* ownTccs */
630 /* 31 0 63 32 */
631 {0x00000000u, 0x00000000u},
633 /* resvdPaRAMSets */
634 /* 31 0 63 32 95 64 127 96 */
635 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
636 /* 159 128 191 160 223 192 255 224 */
637 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
638 /* 287 256 319 288 351 320 383 352 */
639 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
640 /* 415 384 447 416 479 448 511 480 */
641 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
643 /* resvdDmaChannels */
644 /* 31 0 63 32 */
645 {0x00000000u, 0x00000000u},
647 /* resvdQdmaChannels */
648 /* 31 0 */
649 {0x00000000u},
651 /* resvdTccs */
652 /* 31 0 63 32 */
653 {0x00000000u, 0x00000000u},
654 },
655 /* Resources owned/reserved by region 1 */
656 {
657 /* ownPaRAMSets */
658 /* 31 0 63 32 95 64 127 96 */
659 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
660 /* 159 128 191 160 223 192 255 224 */
661 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
662 /* 287 256 319 288 351 320 383 352 */
663 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
664 /* 415 384 447 416 479 448 511 480 */
665 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
667 /* ownDmaChannels */
668 /* 31 0 63 32 */
669 {0xFFFFFFFFu, 0x00000000u},
671 /* ownQdmaChannels */
672 /* 31 0 */
673 {0x000000FFu},
675 /* ownTccs */
676 /* 31 0 63 32 */
677 {0xFFFFFFFFu, 0x00000000u},
679 /* Resources reserved by Region 1 */
680 /* resvdPaRAMSets */
681 /* 31 0 63 32 95 64 127 96 */
682 {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
683 /* 159 128 191 160 223 192 255 224 */
684 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
685 /* 287 256 319 288 351 320 383 352 */
686 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
687 /* 415 384 447 416 479 448 511 480 */
688 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
690 /* resvdDmaChannels */
691 /* 31 0 */
692 {0xFF3FF3FFu,
693 /* 63..32 */
694 0x00000000u},
696 /* resvdQdmaChannels */
697 /* 31 0 */
698 {0x00000000u},
700 /* resvdTccs */
701 /* 31 0 */
702 {0xFF3FF3FFu,
703 /* 63..32 */
704 0x00000000u},
705 },
706 /* Resources owned/reserved by region 2 */
707 {
708 /* ownPaRAMSets */
709 /* 31 0 63 32 95 64 127 96 */
710 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
711 /* 159 128 191 160 223 192 255 224 */
712 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
713 /* 287 256 319 288 351 320 383 352 */
714 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
715 /* 415 384 447 416 479 448 511 480 */
716 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
718 /* ownDmaChannels */
719 /* 31 0 63 32 */
720 {0x00000000u, 0x00000000u},
722 /* ownQdmaChannels */
723 /* 31 0 */
724 {0x00000000u},
726 /* ownTccs */
727 /* 31 0 63 32 */
728 {0x00000000u, 0x00000000u},
730 /* resvdPaRAMSets */
731 /* 31 0 63 32 95 64 127 96 */
732 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
733 /* 159 128 191 160 223 192 255 224 */
734 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
735 /* 287 256 319 288 351 320 383 352 */
736 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
737 /* 415 384 447 416 479 448 511 480 */
738 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
740 /* resvdDmaChannels */
741 /* 31 0 63 32 */
742 {0x00000000u, 0x00000000u},
744 /* resvdQdmaChannels */
745 /* 31 0 */
746 {0x00000000u},
748 /* resvdTccs */
749 /* 31 0 63 32 */
750 {0x00000000u, 0x00000000u},
751 },
753 /* Resources owned/reserved by region 3 */
754 {
755 /* ownPaRAMSets */
756 /* 31 0 63 32 95 64 127 96 */
757 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
758 /* 159 128 191 160 223 192 255 224 */
759 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
760 /* 287 256 319 288 351 320 383 352 */
761 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
762 /* 415 384 447 416 479 448 511 480 */
763 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
765 /* ownDmaChannels */
766 /* 31 0 63 32 */
767 {0x00000000u, 0x00000000u},
769 /* ownQdmaChannels */
770 /* 31 0 */
771 {0x00000000u},
773 /* ownTccs */
774 /* 31 0 63 32 */
775 {0x00000000u, 0x00000000u},
777 /* resvdPaRAMSets */
778 /* 31 0 63 32 95 64 127 96 */
779 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
780 /* 159 128 191 160 223 192 255 224 */
781 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
782 /* 287 256 319 288 351 320 383 352 */
783 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
784 /* 415 384 447 416 479 448 511 480 */
785 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
787 /* resvdDmaChannels */
788 /* 31 0 63 32 */
789 {0x00000000u, 0x00000000u},
791 /* resvdQdmaChannels */
792 /* 31 0 */
793 {0x00000000u},
795 /* resvdTccs */
796 /* 31 0 63 32 */
797 {0x00000000u, 0x00000000u},
798 },
800 /* Resources owned/reserved by region 4 */
801 {
802 /* ownPaRAMSets */
803 /* 31 0 63 32 95 64 127 96 */
804 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
805 /* 159 128 191 160 223 192 255 224 */
806 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
807 /* 287 256 319 288 351 320 383 352 */
808 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
809 /* 415 384 447 416 479 448 511 480 */
810 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
812 /* ownDmaChannels */
813 /* 31 0 63 32 */
814 {0x00000000u, 0x00000000u},
816 /* ownQdmaChannels */
817 /* 31 0 */
818 {0x00000000u},
820 /* ownTccs */
821 /* 31 0 63 32 */
822 {0x00000000u, 0x00000000u},
824 /* resvdPaRAMSets */
825 /* 31 0 63 32 95 64 127 96 */
826 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
827 /* 159 128 191 160 223 192 255 224 */
828 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
829 /* 287 256 319 288 351 320 383 352 */
830 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
831 /* 415 384 447 416 479 448 511 480 */
832 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
834 /* resvdDmaChannels */
835 /* 31 0 63 32 */
836 {0x00000000u, 0x00000000u},
838 /* resvdQdmaChannels */
839 /* 31 0 */
840 {0x00000000u},
842 /* resvdTccs */
843 /* 31 0 63 32 */
844 {0x00000000u, 0x00000000u},
845 },
847 /* Resources owned/reserved by region 5 */
848 {
849 /* ownPaRAMSets */
850 /* 31 0 63 32 95 64 127 96 */
851 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
852 /* 159 128 191 160 223 192 255 224 */
853 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
854 /* 287 256 319 288 351 320 383 352 */
855 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
856 /* 415 384 447 416 479 448 511 480 */
857 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
859 /* ownDmaChannels */
860 /* 31 0 63 32 */
861 {0x00000000u, 0x00000000u},
863 /* ownQdmaChannels */
864 /* 31 0 */
865 {0x00000000u},
867 /* ownTccs */
868 /* 31 0 63 32 */
869 {0x00000000u, 0x00000000u},
871 /* resvdPaRAMSets */
872 /* 31 0 63 32 95 64 127 96 */
873 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
874 /* 159 128 191 160 223 192 255 224 */
875 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
876 /* 287 256 319 288 351 320 383 352 */
877 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
878 /* 415 384 447 416 479 448 511 480 */
879 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
881 /* resvdDmaChannels */
882 /* 31 0 63 32 */
883 {0x00000000u, 0x00000000u},
885 /* resvdQdmaChannels */
886 /* 31 0 */
887 {0x00000000u},
889 /* resvdTccs */
890 /* 31 0 63 32 */
891 {0x00000000u, 0x00000000u},
892 },
894 /* Resources owned/reserved by region 6 */
895 {
896 /* ownPaRAMSets */
897 /* 31 0 63 32 95 64 127 96 */
898 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
899 /* 159 128 191 160 223 192 255 224 */
900 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
901 /* 287 256 319 288 351 320 383 352 */
902 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
903 /* 415 384 447 416 479 448 511 480 */
904 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
906 /* ownDmaChannels */
907 /* 31 0 63 32 */
908 {0x00000000u, 0x00000000u},
910 /* ownQdmaChannels */
911 /* 31 0 */
912 {0x00000000u},
914 /* ownTccs */
915 /* 31 0 63 32 */
916 {0x00000000u, 0x00000000u},
918 /* resvdPaRAMSets */
919 /* 31 0 63 32 95 64 127 96 */
920 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
921 /* 159 128 191 160 223 192 255 224 */
922 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
923 /* 287 256 319 288 351 320 383 352 */
924 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
925 /* 415 384 447 416 479 448 511 480 */
926 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
928 /* resvdDmaChannels */
929 /* 31 0 63 32 */
930 {0x00000000u, 0x00000000u},
932 /* resvdQdmaChannels */
933 /* 31 0 */
934 {0x00000000u},
936 /* resvdTccs */
937 /* 31 0 63 32 */
938 {0x00000000u, 0x00000000u},
939 },
941 /* Resources owned/reserved by region 7 */
942 {
943 /* ownPaRAMSets */
944 /* 31 0 63 32 95 64 127 96 */
945 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
946 /* 159 128 191 160 223 192 255 224 */
947 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
948 /* 287 256 319 288 351 320 383 352 */
949 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
950 /* 415 384 447 416 479 448 511 480 */
951 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
953 /* ownDmaChannels */
954 /* 31 0 63 32 */
955 {0x00000000u, 0x00000000u},
957 /* ownQdmaChannels */
958 /* 31 0 */
959 {0x00000000u},
961 /* ownTccs */
962 /* 31 0 63 32 */
963 {0x00000000u, 0x00000000u},
965 /* resvdPaRAMSets */
966 /* 31 0 63 32 95 64 127 96 */
967 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
968 /* 159 128 191 160 223 192 255 224 */
969 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
970 /* 287 256 319 288 351 320 383 352 */
971 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
972 /* 415 384 447 416 479 448 511 480 */
973 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
975 /* resvdDmaChannels */
976 /* 31 0 63 32 */
977 {0x00000000u, 0x00000000u},
979 /* resvdQdmaChannels */
980 /* 31 0 */
981 {0x00000000u},
983 /* resvdTccs */
984 /* 31 0 63 32 */
985 {0x00000000u, 0x00000000u},
986 },
987 },
988 /* EDMA3 INSTANCE# 1 */
989 {
990 /* Resources owned/reserved by region 0 */
991 {
992 /* ownPaRAMSets */
993 /* 31 0 63 32 95 64 127 96 */
994 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
995 /* 159 128 191 160 223 192 255 224 */
996 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
997 /* 287 256 319 288 351 320 383 352 */
998 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
999 /* 415 384 447 416 479 448 511 480 */
1000 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1002 /* ownDmaChannels */
1003 /* 31 0 63 32 */
1004 {0x00000000u, 0x00000000u},
1006 /* ownQdmaChannels */
1007 /* 31 0 */
1008 {0x00000000u},
1010 /* ownTccs */
1011 /* 31 0 63 32 */
1012 {0x00000000u, 0x00000000u},
1014 /* resvdPaRAMSets */
1015 /* 31 0 63 32 95 64 127 96 */
1016 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1017 /* 159 128 191 160 223 192 255 224 */
1018 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1019 /* 287 256 319 288 351 320 383 352 */
1020 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1021 /* 415 384 447 416 479 448 511 480 */
1022 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1024 /* resvdDmaChannels */
1025 /* 31 0 63 32 */
1026 {0x00000000u, 0x00000000u},
1028 /* resvdQdmaChannels */
1029 /* 31 0 */
1030 {0x00000000u},
1032 /* resvdTccs */
1033 /* 31 0 63 32 */
1034 {0x00000000u, 0x00000000u},
1035 },
1036 /* Resources owned by Region 1 */
1037 {
1038 /* ownPaRAMSets */
1039 /* 31 0 63 32 95 64 127 96 */
1040 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1041 /* 159 128 191 160 223 192 255 224 */
1042 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1043 /* 287 256 319 288 351 320 383 352 */
1044 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1045 /* 415 384 447 416 479 448 511 480 */
1046 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1048 /* ownDmaChannels */
1049 /* 31 0 63 32 */
1050 {0xFFFFFFFFu, 0x00000000u},
1052 /* ownQdmaChannels */
1053 /* 31 0 */
1054 {0x000000FFu},
1056 /* ownTccs */
1057 /* 31 0 63 32 */
1058 {
1059 0xFFFFFFFFu,
1060 0x00000000u
1061 },
1063 /* Resources reserved by Region 1 */
1064 /* resvdPaRAMSets */
1065 /* 31 0 63 32 95 64 127 96 */
1066 {
1067 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1068 /* 159 128 191 160 223 192 255 224 */
1069 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1070 /* 287 256 319 288 351 320 383 352 */
1071 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1072 /* 415 384 447 416 479 448 511 480 */
1073 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1074 },
1076 /* resvdDmaChannels */
1077 /* 31 0 */
1078 {
1079 0x3F07FFFFu,
1080 /* 63..32 */
1081 0x00000000u
1082 },
1084 /* resvdQdmaChannels */
1085 /* 31 0 */
1086 {
1087 0x00000000u
1088 },
1090 /* resvdTccs */
1091 /* 31 0 */
1092 {
1093 0x3F07FFFFu,
1094 /* 63..32 */
1095 0x00000000u
1096 },
1097 },
1098 /* Resources owned/reserved by region 2 */
1099 {
1100 /* ownPaRAMSets */
1101 /* 31 0 63 32 95 64 127 96 */
1102 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1103 /* 159 128 191 160 223 192 255 224 */
1104 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1105 /* 287 256 319 288 351 320 383 352 */
1106 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1107 /* 415 384 447 416 479 448 511 480 */
1108 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1110 /* ownDmaChannels */
1111 /* 31 0 63 32 */
1112 {0x00000000u, 0x00000000u},
1114 /* ownQdmaChannels */
1115 /* 31 0 */
1116 {0x00000000u},
1118 /* ownTccs */
1119 /* 31 0 63 32 */
1120 {0x00000000u, 0x00000000u},
1122 /* resvdPaRAMSets */
1123 /* 31 0 63 32 95 64 127 96 */
1124 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1125 /* 159 128 191 160 223 192 255 224 */
1126 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1127 /* 287 256 319 288 351 320 383 352 */
1128 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1129 /* 415 384 447 416 479 448 511 480 */
1130 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1132 /* resvdDmaChannels */
1133 /* 31 0 63 32 */
1134 {0x00000000u, 0x00000000u},
1136 /* resvdQdmaChannels */
1137 /* 31 0 */
1138 {0x00000000u},
1140 /* resvdTccs */
1141 /* 31 0 63 32 */
1142 {0x00000000u, 0x00000000u},
1143 },
1145 /* Resources owned/reserved by region 3 */
1146 {
1147 /* ownPaRAMSets */
1148 /* 31 0 63 32 95 64 127 96 */
1149 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1150 /* 159 128 191 160 223 192 255 224 */
1151 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1152 /* 287 256 319 288 351 320 383 352 */
1153 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1154 /* 415 384 447 416 479 448 511 480 */
1155 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1157 /* ownDmaChannels */
1158 /* 31 0 63 32 */
1159 {0x00000000u, 0x00000000u},
1161 /* ownQdmaChannels */
1162 /* 31 0 */
1163 {0x00000000u},
1165 /* ownTccs */
1166 /* 31 0 63 32 */
1167 {0x00000000u, 0x00000000u},
1169 /* resvdPaRAMSets */
1170 /* 31 0 63 32 95 64 127 96 */
1171 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1172 /* 159 128 191 160 223 192 255 224 */
1173 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1174 /* 287 256 319 288 351 320 383 352 */
1175 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1176 /* 415 384 447 416 479 448 511 480 */
1177 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1179 /* resvdDmaChannels */
1180 /* 31 0 63 32 */
1181 {0x00000000u, 0x00000000u},
1183 /* resvdQdmaChannels */
1184 /* 31 0 */
1185 {0x00000000u},
1187 /* resvdTccs */
1188 /* 31 0 63 32 */
1189 {0x00000000u, 0x00000000u},
1190 },
1192 /* Resources owned/reserved by region 4 */
1193 {
1194 /* ownPaRAMSets */
1195 /* 31 0 63 32 95 64 127 96 */
1196 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1197 /* 159 128 191 160 223 192 255 224 */
1198 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1199 /* 287 256 319 288 351 320 383 352 */
1200 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1201 /* 415 384 447 416 479 448 511 480 */
1202 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1204 /* ownDmaChannels */
1205 /* 31 0 63 32 */
1206 {0x00000000u, 0x00000000u},
1208 /* ownQdmaChannels */
1209 /* 31 0 */
1210 {0x00000000u},
1212 /* ownTccs */
1213 /* 31 0 63 32 */
1214 {0x00000000u, 0x00000000u},
1216 /* resvdPaRAMSets */
1217 /* 31 0 63 32 95 64 127 96 */
1218 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1219 /* 159 128 191 160 223 192 255 224 */
1220 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1221 /* 287 256 319 288 351 320 383 352 */
1222 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1223 /* 415 384 447 416 479 448 511 480 */
1224 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1226 /* resvdDmaChannels */
1227 /* 31 0 63 32 */
1228 {0x00000000u, 0x00000000u},
1230 /* resvdQdmaChannels */
1231 /* 31 0 */
1232 {0x00000000u},
1234 /* resvdTccs */
1235 /* 31 0 63 32 */
1236 {0x00000000u, 0x00000000u},
1237 },
1239 /* Resources owned/reserved by region 5 */
1240 {
1241 /* ownPaRAMSets */
1242 /* 31 0 63 32 95 64 127 96 */
1243 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1244 /* 159 128 191 160 223 192 255 224 */
1245 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1246 /* 287 256 319 288 351 320 383 352 */
1247 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1248 /* 415 384 447 416 479 448 511 480 */
1249 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1251 /* ownDmaChannels */
1252 /* 31 0 63 32 */
1253 {0x00000000u, 0x00000000u},
1255 /* ownQdmaChannels */
1256 /* 31 0 */
1257 {0x00000000u},
1259 /* ownTccs */
1260 /* 31 0 63 32 */
1261 {0x00000000u, 0x00000000u},
1263 /* resvdPaRAMSets */
1264 /* 31 0 63 32 95 64 127 96 */
1265 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1266 /* 159 128 191 160 223 192 255 224 */
1267 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1268 /* 287 256 319 288 351 320 383 352 */
1269 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1270 /* 415 384 447 416 479 448 511 480 */
1271 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1273 /* resvdDmaChannels */
1274 /* 31 0 63 32 */
1275 {0x00000000u, 0x00000000u},
1277 /* resvdQdmaChannels */
1278 /* 31 0 */
1279 {0x00000000u},
1281 /* resvdTccs */
1282 /* 31 0 63 32 */
1283 {0x00000000u, 0x00000000u},
1284 },
1286 /* Resources owned/reserved by region 6 */
1287 {
1288 /* ownPaRAMSets */
1289 /* 31 0 63 32 95 64 127 96 */
1290 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1291 /* 159 128 191 160 223 192 255 224 */
1292 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1293 /* 287 256 319 288 351 320 383 352 */
1294 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1295 /* 415 384 447 416 479 448 511 480 */
1296 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1298 /* ownDmaChannels */
1299 /* 31 0 63 32 */
1300 {0x00000000u, 0x00000000u},
1302 /* ownQdmaChannels */
1303 /* 31 0 */
1304 {0x00000000u},
1306 /* ownTccs */
1307 /* 31 0 63 32 */
1308 {0x00000000u, 0x00000000u},
1310 /* resvdPaRAMSets */
1311 /* 31 0 63 32 95 64 127 96 */
1312 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1313 /* 159 128 191 160 223 192 255 224 */
1314 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1315 /* 287 256 319 288 351 320 383 352 */
1316 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1317 /* 415 384 447 416 479 448 511 480 */
1318 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1320 /* resvdDmaChannels */
1321 /* 31 0 63 32 */
1322 {0x00000000u, 0x00000000u},
1324 /* resvdQdmaChannels */
1325 /* 31 0 */
1326 {0x00000000u},
1328 /* resvdTccs */
1329 /* 31 0 63 32 */
1330 {0x00000000u, 0x00000000u},
1331 },
1333 /* Resources owned/reserved by region 7 */
1334 {
1335 /* ownPaRAMSets */
1336 /* 31 0 63 32 95 64 127 96 */
1337 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1338 /* 159 128 191 160 223 192 255 224 */
1339 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1340 /* 287 256 319 288 351 320 383 352 */
1341 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1342 /* 415 384 447 416 479 448 511 480 */
1343 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1345 /* ownDmaChannels */
1346 /* 31 0 63 32 */
1347 {0x00000000u, 0x00000000u},
1349 /* ownQdmaChannels */
1350 /* 31 0 */
1351 {0x00000000u},
1353 /* ownTccs */
1354 /* 31 0 63 32 */
1355 {0x00000000u, 0x00000000u},
1357 /* resvdPaRAMSets */
1358 /* 31 0 63 32 95 64 127 96 */
1359 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1360 /* 159 128 191 160 223 192 255 224 */
1361 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1362 /* 287 256 319 288 351 320 383 352 */
1363 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1364 /* 415 384 447 416 479 448 511 480 */
1365 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1367 /* resvdDmaChannels */
1368 /* 31 0 63 32 */
1369 {0x00000000u, 0x00000000u},
1371 /* resvdQdmaChannels */
1372 /* 31 0 */
1373 {0x00000000u},
1375 /* resvdTccs */
1376 /* 31 0 63 32 */
1377 {0x00000000u, 0x00000000u},
1378 }
1379 }
1380 };
1382 /* End of File */