fixed build warning
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_c6a811x_arm_int_reg.c
1 /*
2  * sample_c6a811x_int_reg.c
3  *
4  * Platform specific interrupt registration and un-registration routines.
5  *
6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  *
9  *  Redistribution and use in source and binary forms, with or without
10  *  modification, are permitted provided that the following conditions
11  *  are met:
12  *
13  *    Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  *
16  *    Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the
19  *    distribution.
20  *
21  *    Neither the name of Texas Instruments Incorporated nor the names of
22  *    its contributors may be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/hal/Hwi.h>
41 #include <xdc/runtime/Error.h>
42 #include <xdc/runtime/System.h>
44 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
46 /**
47   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
48   * (Not all TC error ISRs need to be registered, register only for the
49   * available Transfer Controllers).
50   */
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
52                                                 {
53                                                 &lisrEdma3TC0ErrHandler0,
54                                                 &lisrEdma3TC1ErrHandler0,
55                                                 &lisrEdma3TC2ErrHandler0,
56                                                 &lisrEdma3TC3ErrHandler0,
57                                                 &lisrEdma3TC4ErrHandler0,
58                                                 &lisrEdma3TC5ErrHandler0,
59                                                 &lisrEdma3TC6ErrHandler0,
60                                                 &lisrEdma3TC7ErrHandler0,
61                                                 };
63 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
64 extern unsigned int ccErrorInt[];
65 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
66 extern unsigned int numEdma3Tc[];
68 /**
69  * Variables which will be used internally for referring the hardware interrupt
70  * for various EDMA3 interrupts.
71  */
72 extern unsigned int hwIntXferComp[];
73 extern unsigned int hwIntCcErr[];
74 extern unsigned int hwIntTcErr[];
76 extern unsigned int dsp_num;
77 /* This variable has to be used as an extern */
78 //unsigned int gpp_num = 4;
80 Hwi_Handle hwiCCXferCompInt;
81 Hwi_Handle hwiCCErrInt;
82 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
84 /* External Instance Specific Configuration Structure */
85 extern EDMA3_RM_GblXbarToChanConfigParams 
86                                                                 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
88 typedef struct  {
89     volatile Uint32 DSP_INTMUX[21];
90     volatile Uint32 DUCATI_INTMUX[15];
91     volatile Uint32 TPCC_EVTMUX[16];
92     volatile Uint32 TIMER_EVTCAPT;
93     volatile Uint32 GPIO_MUX;
94 } CSL_IntmuxRegs;
96 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
100 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
101 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
105 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
109 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
110 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
111 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
114 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
115 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
116 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
119 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)
120 #define EDMA3_NUM_TCC                     (64u)
122 /*
123  * Forward decleration
124  */
125 EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum,
126                  unsigned int *chanNum,
127                  const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig);
128 EDMA3_RM_Result sampleConfigScr (unsigned int eventNum,
129                                   unsigned int chanNum);
131 void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
133 /**  To Register the ISRs with the underlying OS, if required. */
134 void registerEdma3Interrupts (unsigned int edma3Id)
135     {
136     static UInt32 cookie = 0;
137 #ifdef BUILD_CENTAURUS_A8
138     unsigned int numTc = 0;
139 #endif
140     Hwi_Params hwiParams; 
141     Error_Block      eb;
143     /* Initialize the Error Block                                             */
144     Error_init(&eb);
145         
146     /* Disabling the global interrupts */
147     cookie = Hwi_disable();
149     /* Initialize the HWI parameters with user specified values */
150     Hwi_Params_init(&hwiParams);
151     
152     /* argument for the ISR */
153     hwiParams.arg = edma3Id;
154         /* set the priority ID     */
155         //hwiParams.priority = hwIntXferComp[edma3Id];
156     
157     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
158                             ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
159                             (const Hwi_Params *) (&hwiParams),
160                             &eb);
161     if (TRUE == Error_check(&eb))
162     {
163         System_printf("HWI Create Failed\n",Error_getCode(&eb));
164     }
165 #ifdef BUILD_CENTAURUS_A8
166     /* Initialize the HWI parameters with user specified values */
167     Hwi_Params_init(&hwiParams);
168     /* argument for the ISR */
169     hwiParams.arg = edma3Id;
170         /* set the priority ID     */
171         hwiParams.priority = hwIntCcErr[edma3Id];
172         
173         hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
174                 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
175                 (const Hwi_Params *) (&hwiParams),
176                 &eb);
178     if (TRUE == Error_check(&eb))
179     {
180         System_printf("HWI Create Failed\n",Error_getCode(&eb));
181     }
183     while (numTc < numEdma3Tc[edma3Id])
184             {
185         /* Initialize the HWI parameters with user specified values */
186         Hwi_Params_init(&hwiParams);
187         /* argument for the ISR */
188         hwiParams.arg = edma3Id;
189         /* set the priority ID     */
190         hwiParams.priority = hwIntTcErr[edma3Id];
191         
192         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
193                     ((Hwi_FuncPtr)ptrEdma3TcIsrHandler[numTc]),
194                     (const Hwi_Params *) (&hwiParams),
195                     &eb);
196         if (TRUE == Error_check(&eb))
197         {
198             System_printf("HWI Create Failed\n",Error_getCode(&eb));
199         }
200         numTc++;
201         }
202    /**
203     * Enabling the HWI_ID.
204     * EDMA3 interrupts (transfer completion, CC error etc.)
205     * correspond to different ECM events (SoC specific). These ECM events come
206     * under ECM block XXX (handling those specific ECM events). Normally, block
207     * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
208     * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
209     * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
210     * mapped HWI_INT YYY, one should use the corresponding bitmask in the
211     * API C64_enableIER(), in which the YYY bit is SET.
212     */
213     Hwi_enableInterrupt(ccErrorInt[edma3Id]);
214 #if 0
215     Hwi_enableInterrupt(13);
216 #endif
217     Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
218     numTc = 0;
219     while (numTc < numEdma3Tc[edma3Id])
220             {
221         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
222         numTc++;
223         }
224 #endif
225     /* Restore interrupts */
226     Hwi_restore(cookie);
227     }
229 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
230 void unregisterEdma3Interrupts (unsigned int edma3Id)
231     {
232         static UInt32 cookie = 0;
233     unsigned int numTc = 0;
235     /* Disabling the global interrupts */
236     cookie = Hwi_disable();
238     Hwi_delete(&hwiCCXferCompInt);
239     Hwi_delete(&hwiCCErrInt);
240     while (numTc < numEdma3Tc[edma3Id])
241             {
242         Hwi_delete(&hwiTCErrInt[numTc]);
243         numTc++;
244         }
245     /* Restore interrupts */
246     Hwi_restore(cookie);
247     }
249 /**
250  * \brief   sampleMapXbarEvtToChan
251  *
252  * This function reads from the sample configuration structure which specifies 
253  * cross bar events mapped to DMA channel.
254  *
255  * \return  EDMA3_RM_SOK if success, else error code
256  */
257 EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum,
258                  unsigned int *chanNum,
259                  const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig)
260         {
261     EDMA3_RM_Result edma3Result = EDMA3_RM_E_INVALID_PARAM;
262     unsigned int xbarEvtNum = 0;
263     int          edmaChanNum = 0;
265         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
266                 (chanNum != NULL) &&
267                 (edmaGblXbarConfig != NULL))
268                 {
269                 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
270                 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
271                 if (edmaChanNum != -1)
272                         {
273                         *chanNum = edmaChanNum;
274                         edma3Result = EDMA3_RM_SOK;
275                         }
276                 }
277         return (edma3Result);
278         }
281 /**
282  * \brief   sampleConfigScr
283  *
284  * This function configures control config registers for the cross bar events 
285  * mapped to the EDMA channel.
286  *
287  * \return  EDMA3_RM_SOK if success, else error code
288  */
289 EDMA3_RM_Result sampleConfigScr (unsigned int eventNum,
290                                   unsigned int chanNum)
291         {
292     EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;
293     unsigned int scrChanOffset = 0;
294     unsigned int scrRegOffset  = 0;
295     unsigned int xBarEvtNum    = 0;
296     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
299         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
300                 (chanNum < EDMA3_NUM_TCC))
301                 {
302                 scrRegOffset = chanNum / 4;
303                 scrChanOffset = chanNum - (scrRegOffset * 4);
304                 xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
305                 
306                 switch(scrChanOffset)
307                         {
308                         case 0:
309                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
310                                         (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
311                                 break;
312                         case 1:
313                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
314                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
315                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
316                                 break;
317                         case 2:
318                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
319                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
320                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
321                                 break;
322                         case 3:
323                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
324                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
325                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
326                                 break;
327                         default:
328                                 edma3Result = EDMA3_RM_E_INVALID_PARAM;
329                                 break;
330                         }
331                 }
332         else
333                 {
334                 edma3Result = EDMA3_RM_E_INVALID_PARAM;
335                 }
336         return edma3Result;
337         }
339 EDMA3_RM_Result sampleInitXbarEvt(EDMA3_RM_Handle hEdma, 
340                                    unsigned int edma3Id)
341     {
342     EDMA3_RM_Result retVal = EDMA3_RM_SOK;
343     const EDMA3_RM_GblXbarToChanConfigParams *sampleXbarToChanConfig =
344                                 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
345     if (hEdma != NULL)
346         {
347         retVal = EDMA3_RM_initXbarEventMap(hEdma, 
348                                             sampleXbarToChanConfig,
349                                             (EDMA3_RM_mapXbarEvtToChan)&sampleMapXbarEvtToChan,
350                                             (EDMA3_RM_xbarConfigScr)&sampleConfigScr);
351         }
352     
353     return retVal;
354     }
356 void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
357     {
358 #ifdef EDMA3_RM_DEBUG
359     /*  Added to fix warning */
360     printf("memory Protection error");
361 #endif
362     }