Misra C Fixes for dra72x
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_dra72x_arm_int_reg.c
1 /*
2  * sample_dra72x_int_reg.c
3  *
4  * Platform specific interrupt registration and un-registration routines.
5  *
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  *
9  *  Redistribution and use in source and binary forms, with or without
10  *  modification, are permitted provided that the following conditions
11  *  are met:
12  *
13  *    Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  *
16  *    Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the
19  *    distribution.
20  *
21  *    Neither the name of Texas Instruments Incorporated nor the names of
22  *    its contributors may be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/hal/Hwi.h>
41 #include <xdc/runtime/Error.h>
42 #include <xdc/runtime/System.h>
44 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
46 /**
47   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
48   * (Not all TC error ISRs need to be registered, register only for the
49   * available Transfer Controllers).
50   */
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
52                                                 {
53                                                 &lisrEdma3TC0ErrHandler0,
54                                                 &lisrEdma3TC1ErrHandler0,
55                                                 &lisrEdma3TC2ErrHandler0,
56                                                 &lisrEdma3TC3ErrHandler0,
57                                                 &lisrEdma3TC4ErrHandler0,
58                                                 &lisrEdma3TC5ErrHandler0,
59                                                 &lisrEdma3TC6ErrHandler0,
60                                                 &lisrEdma3TC7ErrHandler0,
61                                                 };
63 extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
64 extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
65 extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
66 extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
68 /**
69  * Variables which will be used internally for referring the hardware interrupt
70  * for various EDMA3 interrupts.
71  */
72 extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
73 extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
74 extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
76 extern uint32_t dsp_num;
77 /* This variable has to be used as an extern */
78 uint32_t gpp_num = 0;
80 Hwi_Handle hwiCCXferCompInt;
81 Hwi_Handle hwiCCErrInt;
82 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
84 /* External Instance Specific Configuration Structure */
85 extern EDMA3_DRV_GblXbarToChanConfigParams 
86                                                                 sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
88 typedef struct  {
89     volatile Uint32 TPCC_EVTMUX[32];
90 } CSL_IntmuxRegs;
92 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
94 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
95 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
96 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
98 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
100 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
103 #define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127U)
104 #define EDMA3_NUM_TCC                     (64U)
106 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
107 /*
108  * Forward decleration
109  */
110 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
111                  uint32_t *chanNum,
112                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
113 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
114                                   uint32_t chanNum);
116 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
118 /**  To Register the ISRs with the underlying OS, if required. */
119 void registerEdma3Interrupts (uint32_t edma3Id);
121 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
122 void unregisterEdma3Interrupts (uint32_t edma3Id);
124 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
125                                    uint32_t edma3Id);
126                                    
127 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
129 /**  To Register the ISRs with the underlying OS, if required. */
130 void registerEdma3Interrupts (uint32_t edma3Id)
131     {
132     static UInt32 cookie = 0;
133     uint32_t numTc = 0;
134     Hwi_Params hwiParams;
135     Error_Block      eb;
137     /* Initialize the Error Block                                             */
138     Error_init(&eb);
140     /* Disabling the global interrupts */
141     cookie = Hwi_disable();
143     /* Initialize the HWI parameters with user specified values */
144     Hwi_Params_init(&hwiParams);
146     /* argument for the ISR */
147     hwiParams.arg = edma3Id;
148         /* set the priority ID     */
149         hwiParams.priority = hwIntXferComp[edma3Id];
151     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],
152                                         ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
153                                         (const Hwi_Params *) (&hwiParams),
154                                         &eb);
155     if ((bool)TRUE == Error_check(&eb))
156     {
157         System_printf("HWI Create Failed\n",Error_getCode(&eb));
158     }
160     /* Initialize the HWI parameters with user specified values */
161     Hwi_Params_init(&hwiParams);
162     /* argument for the ISR */
163     hwiParams.arg = edma3Id;
164         /* set the priority ID     */
165         hwiParams.priority = hwIntCcErr[edma3Id];
167         hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
168                 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
169                 (const Hwi_Params *) (&hwiParams),
170                 &eb);
172     if ((bool)TRUE == Error_check(&eb))
173     {
174         System_printf("HWI Create Failed\n",Error_getCode(&eb));
175     }
177     while (numTc < numEdma3Tc[edma3Id])
178             {
179         /* Initialize the HWI parameters with user specified values */
180         Hwi_Params_init(&hwiParams);
181         /* argument for the ISR */
182         hwiParams.arg = edma3Id;
183         /* set the priority ID     */
184         hwiParams.priority = hwIntTcErr[edma3Id];
186         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
187                     (Hwi_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
188                     (const Hwi_Params *) (&hwiParams),
189                     &eb);
190         if ((bool)TRUE == Error_check(&eb))
191         {
192             System_printf("HWI Create Failed\n",Error_getCode(&eb));
193         }
194         numTc++;
195         }
196    /**
197     * Enabling the HWI_ID.
198     * EDMA3 interrupts (transfer completion, CC error etc.)
199     * correspond to different ECM events (SoC specific). These ECM events come
200     * under ECM block XXX (handling those specific ECM events). Normally, block
201     * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
202     * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
203     * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
204     * mapped HWI_INT YYY, one should use the corresponding bitmask in the
205     * API C64_enableIER(), in which the YYY bit is SET.
206     */
207     Hwi_enableInterrupt(ccErrorInt[edma3Id]);
208 #if 0
209     Hwi_enableInterrupt(13);
210 #endif
211     Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]);
212     numTc = 0;
213     while (numTc < numEdma3Tc[edma3Id])
214             {
215         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
216         numTc++;
217         }
219     /* Restore interrupts */
220     Hwi_restore(cookie);
221     }
223 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
224 void unregisterEdma3Interrupts (uint32_t edma3Id)
225     {
226         static UInt32 cookiee = 0;
227     uint32_t numTc = 0;
229     /* Disabling the global interrupts */
230     cookiee = Hwi_disable();
232     Hwi_delete(&hwiCCXferCompInt);
233     Hwi_delete(&hwiCCErrInt);
234     while (numTc < numEdma3Tc[edma3Id])
235             {
236         Hwi_delete(&hwiTCErrInt[numTc]);
237         numTc++;
238         }
239     /* Restore interrupts */
240     Hwi_restore(cookiee);
241     }
243 /**
244  * \brief   sampleMapXbarEvtToChan
245  *
246  * This function reads from the sample configuration structure which specifies
247  * cross bar events mapped to DMA channel.
248  *
249  * \return  EDMA3_DRV_SOK if success, else error code
250  */
251 EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
252                  uint32_t *chanNum,
253                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
254         {
255     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
256     uint32_t xbarEvtNum = 0;
257     int32_t          edmaChanNum = 0;
259         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
260                 (chanNum != NULL) &&
261                 (edmaGblXbarConfig != NULL))
262                 {
263                 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
264                 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
265                 if (edmaChanNum != -1)
266                         {
267                         *chanNum = edmaChanNum;
268                         edma3Result = EDMA3_DRV_SOK;
269                         }
270                 }
271         return (edma3Result);
272         }
275 /**
276  * \brief   sampleConfigScr
277  *
278  * This function configures control config registers for the cross bar events
279  * mapped to the EDMA channel.
280  *
281  * \return  EDMA3_DRV_SOK if success, else error code
282  */
283 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
284                                   uint32_t chanNum)
285         {
286     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
287     uint32_t scrChanOffset = 0;
288     uint32_t scrRegOffset  = 0;
289     uint32_t xBarEvtNum    = 0;
290     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
293         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
294                 (chanNum < EDMA3_NUM_TCC))
295                 {
296                 scrRegOffset = chanNum / 2U;
297                 scrChanOffset = chanNum - (scrRegOffset * 2U);
298                 xBarEvtNum = eventNum + 1U;
299                 
300                 switch(scrChanOffset)
301                         {
302                         case 0:
303                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
304                                         (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
305                                 break;
306                         case 1U:
307                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
308                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
309                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
310                                 break;
311                         default:
312                                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
313                                 break;
314                         }
315                 }
316         else
317                 {
318                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;
319                 }
320         return edma3Result;
321         }
323 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
324                                    uint32_t edma3Id)
325     {
326     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
327     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
328                                 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
329     uint32_t sampleMapXbarEvtToChanTemp = (uint32_t)&sampleMapXbarEvtToChan;
330     uint32_t sampleConfigScrTemp = (uint32_t)&sampleConfigScr;
331     if (hEdma != NULL)
332         {
333         retVal = EDMA3_DRV_initXbarEventMap(hEdma,
334                                                                         sampleXbarToChanConfig,
335                                                                         (EDMA3_DRV_mapXbarEvtToChan)sampleMapXbarEvtToChanTemp,
336                                                                         (EDMA3_DRV_xbarConfigScr)sampleConfigScrTemp);
337         }
339     return retVal;
340     }
342 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
343     {
344 #ifdef EDMA3_RM_DEBUG
345     /*  Added to fix Misra C error */
346     printf("memory Protection error");
347 #endif
348     }