[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_dra72x_cfg.c
1 /*
2 * sample_omapl138_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 /* Statically allocate the region numbers with cores. */
53 int myCoreNum;
54 #define PID0_ADDRESS 0xE00FFFE0
55 #define CORE_ID_C0 0x0
56 #define CORE_ID_C1 0x1
57 unsigned short determineProcId()
58 {
59 unsigned short regionNo = numEdma3Instances;
60 #ifdef BUILD_TDA2XX_DSP
61 extern __cregister volatile unsigned int DNUM;
62 #endif
63 myCoreNum = numDsps;
64 #ifdef BUILD_TDA2XX_MPU
66 asm (" push {r0-r2} \n\t"
67 " MRC p15, 0, r0, c0, c0, 5\n\t"
68 " LDR r1, =myCoreNum\n\t"
69 " STR r0, [r1]\n\t"
70 " pop {r0-r2}\n\t");
71 if((myCoreNum & 0x03) == 1)
72 regionNo = 1;
73 else
74 regionNo = 0;
75 #elif defined(BUILD_TDA2XX_IPU)
76 myCoreNum = (*(unsigned int *)(PID0_ADDRESS));
77 if(Core_getIpuId() == 1){
78 if(myCoreNum == CORE_ID_C0)
79 regionNo = 4;
80 else if (myCoreNum == CORE_ID_C1)
81 regionNo = 5;
82 }
83 if(Core_getIpuId() == 2){
84 if(myCoreNum == CORE_ID_C0)
85 regionNo = 6;
86 else if (myCoreNum == CORE_ID_C1)
87 regionNo = 7;
88 }
89 #elif defined BUILD_TDA2XX_DSP
90 myCoreNum = DNUM;
91 if(myCoreNum == 0)
92 regionNo = 2;
93 else
94 regionNo = 3;
95 #endif
96 return regionNo;
97 }
99 signed char* getGlobalAddr(signed char* addr)
100 {
101 return (addr); /* The address is already a global address */
102 }
103 unsigned short isGblConfigRequired(unsigned int dspNum)
104 {
105 (void) dspNum;
107 return 1;
108 }
110 /* Semaphore handles */
111 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
113 /** Number of PaRAM Sets available */
114 #define EDMA3_NUM_PARAMSET (512u)
116 /** Number of TCCS available */
117 #define EDMA3_NUM_TCC (64u)
119 /** Number of DMA Channels available */
120 #define EDMA3_NUM_DMA_CHANNELS (64u)
122 /** Number of QDMA Channels available */
123 #define EDMA3_NUM_QDMA_CHANNELS (8u)
125 /** Number of Event Queues available */
126 #define EDMA3_0_NUM_EVTQUE (4u)
128 /** Number of Transfer Controllers available */
129 #define EDMA3_0_NUM_TC (4u)
131 /** Number of Regions */
132 #define EDMA3_0_NUM_REGIONS (2u)
135 /** Interrupt no. for Transfer Completion */
136 #define EDMA3_0_CC_XFER_COMPLETION_INT (34u)
137 /** Interrupt no. for CC Error */
138 #define EDMA3_0_CC_ERROR_INT (35u)
139 /** Interrupt no. for TCs Error */
140 #define EDMA3_0_TC0_ERROR_INT (36u)
141 #define EDMA3_0_TC1_ERROR_INT (37u)
142 #define EDMA3_0_TC2_ERROR_INT (0u)
143 #define EDMA3_0_TC3_ERROR_INT (0u)
144 #define EDMA3_0_TC4_ERROR_INT (0u)
145 #define EDMA3_0_TC5_ERROR_INT (0u)
146 #define EDMA3_0_TC6_ERROR_INT (0u)
147 #define EDMA3_0_TC7_ERROR_INT (0u)
149 /**
150 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
151 * ECM events (SoC specific). These ECM events come
152 * under ECM block XXX (handling those specific ECM events). Normally, block
153 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
154 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
155 * is mapped to a specific HWI_INT YYY in the tcf file.
156 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
157 * to transfer completion interrupt.
158 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
159 * to CC error interrupts.
160 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
161 * to TC error interrupts.
162 */
163 /* EDMA 0 */
165 #define EDMA3_0_HWI_INT_XFER_COMP (7u)
166 #define EDMA3_0_HWI_INT_CC_ERR (7u)
167 #define EDMA3_0_HWI_INT_TC0_ERR (7u)
168 #define EDMA3_0_HWI_INT_TC1_ERR (7u)
169 #define EDMA3_0_HWI_INT_TC2_ERR (7u)
170 #define EDMA3_0_HWI_INT_TC3_ERR (7u)
173 /**
174 * \brief Mapping of DMA channels 0-31 to Hardware Events from
175 * various peripherals, which use EDMA for data transfer.
176 * All channels need not be mapped, some can be free also.
177 * 1: Mapped
178 * 0: Not mapped
179 *
180 * This mapping will be used to allocate DMA channels when user passes
181 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
182 * copy). The same mapping is used to allocate the TCC when user passes
183 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
184 *
185 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
186 */
187 /* 31 0 */
188 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x3FC0C06Eu) /* TBD */
191 /**
192 * \brief Mapping of DMA channels 32-63 to Hardware Events from
193 * various peripherals, which use EDMA for data transfer.
194 * All channels need not be mapped, some can be free also.
195 * 1: Mapped
196 * 0: Not mapped
197 *
198 * This mapping will be used to allocate DMA channels when user passes
199 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
200 * copy). The same mapping is used to allocate the TCC when user passes
201 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
202 *
203 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
204 */
205 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xF3FFFFFCu) /* TBD */
208 /* Variable which will be used internally for referring number of Event Queues*/
209 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
210 EDMA3_0_NUM_EVTQUE,
211 };
213 /* Variable which will be used internally for referring number of TCs. */
214 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {
215 EDMA3_0_NUM_TC,
216 };
218 /**
219 * Variable which will be used internally for referring transfer completion
220 * interrupt.
221 */
222 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
223 {
224 {
225 0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
226 },
227 };
229 /**
230 * Variable which will be used internally for referring channel controller's
231 * error interrupt.
232 */
233 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
234 EDMA3_0_CC_ERROR_INT,
235 };
237 /**
238 * Variable which will be used internally for referring transfer controllers'
239 * error interrupts.
240 */
241 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
242 {
243 {
244 EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
245 EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
246 EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
247 EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
248 }
249 };
251 /**
252 * Variables which will be used internally for referring the hardware interrupt
253 * for various EDMA3 interrupts.
254 */
255 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
256 EDMA3_0_HWI_INT_XFER_COMP
257 };
259 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
260 EDMA3_0_HWI_INT_CC_ERR
261 };
263 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
264 {
265 EDMA3_0_HWI_INT_TC0_ERR,
266 EDMA3_0_HWI_INT_TC1_ERR,
267 EDMA3_0_HWI_INT_TC2_ERR,
268 EDMA3_0_HWI_INT_TC3_ERR
269 }
270 };
272 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))
273 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))
274 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))
275 /* Driver Object Initialization Configuration */
276 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
277 {
278 {
279 /* EDMA3 INSTANCE# 0 */
280 /** Total number of DMA Channels supported by the EDMA3 Controller */
281 EDMA3_NUM_DMA_CHANNELS,
282 /** Total number of QDMA Channels supported by the EDMA3 Controller */
283 EDMA3_NUM_QDMA_CHANNELS,
284 /** Total number of TCCs supported by the EDMA3 Controller */
285 EDMA3_NUM_TCC,
286 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
287 EDMA3_NUM_PARAMSET,
288 /** Total number of Event Queues in the EDMA3 Controller */
289 EDMA3_0_NUM_EVTQUE,
290 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
291 EDMA3_0_NUM_TC,
292 /** Number of Regions on this EDMA3 controller */
293 EDMA3_0_NUM_REGIONS,
295 /**
296 * \brief Channel mapping existence
297 * A value of 0 (No channel mapping) implies that there is fixed association
298 * for a channel number to a parameter entry number or, in other words,
299 * PaRAM entry n corresponds to channel n.
300 */
301 1u,
303 /** Existence of memory protection feature */
304 0u,
306 /** Global Register Region of CC Registers */
307 EDMA3_CC_BASE_ADDR,
308 /** Transfer Controller (TC) Registers */
309 {
310 EDMA3_TC0_BASE_ADDR,
311 EDMA3_TC1_BASE_ADDR,
312 (void *)NULL,
313 (void *)NULL,
314 (void *)NULL,
315 (void *)NULL,
316 (void *)NULL,
317 (void *)NULL
318 },
319 /** Interrupt no. for Transfer Completion */
320 EDMA3_0_CC_XFER_COMPLETION_INT,
321 /** Interrupt no. for CC Error */
322 EDMA3_0_CC_ERROR_INT,
323 /** Interrupt no. for TCs Error */
324 {
325 EDMA3_0_TC0_ERROR_INT,
326 EDMA3_0_TC1_ERROR_INT,
327 EDMA3_0_TC2_ERROR_INT,
328 EDMA3_0_TC3_ERROR_INT,
329 EDMA3_0_TC4_ERROR_INT,
330 EDMA3_0_TC5_ERROR_INT,
331 EDMA3_0_TC6_ERROR_INT,
332 EDMA3_0_TC7_ERROR_INT
333 },
335 /**
336 * \brief EDMA3 TC priority setting
337 *
338 * User can program the priority of the Event Queues
339 * at a system-wide level. This means that the user can set the
340 * priority of an IO initiated by either of the TCs (Transfer Controllers)
341 * relative to IO initiated by the other bus masters on the
342 * device (ARM, DSP, USB, etc)
343 */
344 {
345 0u,
346 1u,
347 2u,
348 3u,
349 0u,
350 0u,
351 0u,
352 0u
353 },
354 /**
355 * \brief To Configure the Threshold level of number of events
356 * that can be queued up in the Event queues. EDMA3CC error register
357 * (CCERR) will indicate whether or not at any instant of time the
358 * number of events queued up in any of the event queues exceeds
359 * or equals the threshold/watermark value that is set
360 * in the queue watermark threshold register (QWMTHRA).
361 */
362 {
363 16u,
364 16u,
365 16u,
366 16u,
367 0u,
368 0u,
369 0u,
370 0u
371 },
373 /**
374 * \brief To Configure the Default Burst Size (DBS) of TCs.
375 * An optimally-sized command is defined by the transfer controller
376 * default burst size (DBS). Different TCs can have different
377 * DBS values. It is defined in Bytes.
378 */
379 {
380 16u,
381 16u,
382 0u,
383 0u,
384 0u,
385 0u,
386 0u,
387 0u
388 },
390 /**
391 * \brief Mapping from each DMA channel to a Parameter RAM set,
392 * if it exists, otherwise of no use.
393 */
394 {
395 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
396 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
397 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
398 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
399 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
400 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
401 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
402 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
403 },
405 /**
406 * \brief Mapping from each DMA channel to a TCC. This specific
407 * TCC code will be returned when the transfer is completed
408 * on the mapped channel.
409 */
410 {
411 0u, 1u, 2u, 3u,
412 4u, 5u, 6u, 7u,
413 8u, 9u, 10u, 11u,
414 12u, 13u, 14u, 15u,
415 16u, 17u, 18u, 19u,
416 20u, 21u, 22u, 23u,
417 24u, 25u, 26u, 27u,
418 28u, 29u, 30u, 31u,
419 32u, 33u, 34u, 35u,
420 36u, 37u, 38u, 39u,
421 40u, 41u, 42u, 43u,
422 44u, 45u, 46u, 47u,
423 48u, 49u, 50u, 51u,
424 52u, 53u, 54u, 55u,
425 56u, 57u, 58u, 59u,
426 60u, 61u, 62u, 63u
427 },
429 /**
430 * \brief Mapping of DMA channels to Hardware Events from
431 * various peripherals, which use EDMA for data transfer.
432 * All channels need not be mapped, some can be free also.
433 */
434 {
435 EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
436 EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
437 }
438 },
440 };
443 /* Driver Instance Initialization Configuration */
444 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
445 {
446 /* EDMA3 INSTANCE# 0 */
447 {
448 /* Resources owned/reserved by region 0 (Associated to any MPU core)*/
449 {
450 /* ownPaRAMSets */
451 /* 31 0 63 32 95 64 127 96 */
452 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
453 /* 159 128 191 160 223 192 255 224 */
454 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
455 /* 287 256 319 288 351 320 383 352 */
456 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
457 /* 415 384 447 416 479 448 511 480 */
458 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
460 /* ownDmaChannels */
461 /* 31 0 63 32 */
462 {0xFFFFFFFFu, 0xFFFFFFFFu},
464 /* ownQdmaChannels */
465 /* 31 0 */
466 {0x000000FFu},
468 /* ownTccs */
469 /* 31 0 63 32 */
470 {0xFFFFFFFFu, 0xFFFFFFFFu},
472 /* resvdPaRAMSets */
473 /* 31 0 63 32 95 64 127 96 */
474 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
475 /* 159 128 191 160 223 192 255 224 */
476 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
477 /* 287 256 319 288 351 320 383 352 */
478 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
479 /* 415 384 447 416 479 448 511 480 */
480 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
482 /* resvdDmaChannels */
483 /* 31 0 63 32 */
484 {0x00u, 0x00u},
486 /* resvdQdmaChannels */
487 /* 31 0 */
488 {0x00u},
490 /* resvdTccs */
491 /* 31 0 63 32 */
492 {0x00u, 0x00u},
493 },
495 /* Resources owned/reserved by region 1 (Associated to any DSP core) */
496 {
497 /* ownPaRAMSets */
498 /* 31 0 63 32 95 64 127 96 */
499 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
500 /* 159 128 191 160 223 192 255 224 */
501 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
502 /* 287 256 319 288 351 320 383 352 */
503 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
504 /* 415 384 447 416 479 448 511 480 */
505 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
507 /* ownDmaChannels */
508 /* 31 0 63 32 */
509 {0xFFFFFFFFu, 0xFFFFFFFFu},
511 /* ownQdmaChannels */
512 /* 31 0 */
513 {0x000000FFu},
515 /* ownTccs */
516 /* 31 0 63 32 */
517 {0xFFFFFFFFu, 0xFFFFFFFFu},
519 /* resvdPaRAMSets */
520 /* 31 0 63 32 95 64 127 96 */
521 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
522 /* 159 128 191 160 223 192 255 224 */
523 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
524 /* 287 256 319 288 351 320 383 352 */
525 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
526 /* 415 384 447 416 479 448 511 480 */
527 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
529 /* resvdDmaChannels */
530 /* 31 0 63 32 */
531 {0x00u, 0x00u},
533 /* resvdQdmaChannels */
534 /* 31 0 */
535 {0x00u},
537 /* resvdTccs */
538 /* 31 0 63 32 */
539 {0x00u, 0x00u},
540 },
542 /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/
543 {
544 /* ownPaRAMSets */
545 /* 31 0 63 32 95 64 127 96 */
546 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
547 /* 159 128 191 160 223 192 255 224 */
548 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
549 /* 287 256 319 288 351 320 383 352 */
550 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
551 /* 415 384 447 416 479 448 511 480 */
552 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
554 /* ownDmaChannels */
555 /* 31 0 63 32 */
556 {0xFFFFFFFFu, 0xFFFFFFFFu},
558 /* ownQdmaChannels */
559 /* 31 0 */
560 {0x000000FFu},
562 /* ownTccs */
563 /* 31 0 63 32 */
564 {0xFFFFFFFFu, 0xFFFFFFFFu},
566 /* resvdPaRAMSets */
567 /* 31 0 63 32 95 64 127 96 */
568 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
569 /* 159 128 191 160 223 192 255 224 */
570 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
571 /* 287 256 319 288 351 320 383 352 */
572 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
573 /* 415 384 447 416 479 448 511 480 */
574 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
576 /* resvdDmaChannels */
577 /* 31 0 63 32 */
578 {0x00u, 0x00u},
580 /* resvdQdmaChannels */
581 /* 31 0 */
582 {0x00u},
584 /* resvdTccs */
585 /* 31 0 63 32 */
586 {0x00u, 0x00u},
587 },
589 /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/
590 {
591 /* ownPaRAMSets */
592 /* 31 0 63 32 95 64 127 96 */
593 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
594 /* 159 128 191 160 223 192 255 224 */
595 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
596 /* 287 256 319 288 351 320 383 352 */
597 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
598 /* 415 384 447 416 479 448 511 480 */
599 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
601 /* ownDmaChannels */
602 /* 31 0 63 32 */
603 {0xFFFFFFFFu, 0xFFFFFFFFu},
605 /* ownQdmaChannels */
606 /* 31 0 */
607 {0x000000FFu},
609 /* ownTccs */
610 /* 31 0 63 32 */
611 {0xFFFFFFFFu, 0xFFFFFFFFu},
613 /* resvdPaRAMSets */
614 /* 31 0 63 32 95 64 127 96 */
615 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
616 /* 159 128 191 160 223 192 255 224 */
617 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
618 /* 287 256 319 288 351 320 383 352 */
619 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
620 /* 415 384 447 416 479 448 511 480 */
621 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
623 /* resvdDmaChannels */
624 /* 31 0 63 32 */
625 {0x00u, 0x00u},
627 /* resvdQdmaChannels */
628 /* 31 0 */
629 {0x00u},
631 /* resvdTccs */
632 /* 31 0 63 32 */
633 {0x00u, 0x00u},
634 },
636 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
637 {
638 /* ownPaRAMSets */
639 /* 31 0 63 32 95 64 127 96 */
640 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
641 /* 159 128 191 160 223 192 255 224 */
642 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
643 /* 287 256 319 288 351 320 383 352 */
644 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
645 /* 415 384 447 416 479 448 511 480 */
646 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
648 /* ownDmaChannels */
649 /* 31 0 63 32 */
650 {0x00000000u, 0x00000000u},
652 /* ownQdmaChannels */
653 /* 31 0 */
654 {0x00000000u},
656 /* ownTccs */
657 /* 31 0 63 32 */
658 {0x00000000u, 0x00000000u},
660 /* resvdPaRAMSets */
661 /* 31 0 63 32 95 64 127 96 */
662 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
663 /* 159 128 191 160 223 192 255 224 */
664 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
665 /* 287 256 319 288 351 320 383 352 */
666 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
667 /* 415 384 447 416 479 448 511 480 */
668 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
670 /* resvdDmaChannels */
671 /* 31 0 63 32 */
672 {0x00000000u, 0x00000000u},
674 /* resvdQdmaChannels */
675 /* 31 0 */
676 {0x00000000u},
678 /* resvdTccs */
679 /* 31 0 63 32 */
680 {0x00000000u, 0x00000000u},
681 },
683 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
684 {
685 /* ownPaRAMSets */
686 /* 31 0 63 32 95 64 127 96 */
687 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
688 /* 159 128 191 160 223 192 255 224 */
689 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
690 /* 287 256 319 288 351 320 383 352 */
691 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
692 /* 415 384 447 416 479 448 511 480 */
693 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
695 /* ownDmaChannels */
696 /* 31 0 63 32 */
697 {0x00000000u, 0x00000000u},
699 /* ownQdmaChannels */
700 /* 31 0 */
701 {0x00000000u},
703 /* ownTccs */
704 /* 31 0 63 32 */
705 {0x00000000u, 0x00000000u},
707 /* resvdPaRAMSets */
708 /* 31 0 63 32 95 64 127 96 */
709 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
710 /* 159 128 191 160 223 192 255 224 */
711 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
712 /* 287 256 319 288 351 320 383 352 */
713 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
714 /* 415 384 447 416 479 448 511 480 */
715 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
717 /* resvdDmaChannels */
718 /* 31 0 63 32 */
719 {0x00000000u, 0x00000000u},
721 /* resvdQdmaChannels */
722 /* 31 0 */
723 {0x00000000u},
725 /* resvdTccs */
726 /* 31 0 63 32 */
727 {0x00000000u, 0x00000000u},
728 },
730 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
731 {
732 /* ownPaRAMSets */
733 /* 31 0 63 32 95 64 127 96 */
734 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
735 /* 159 128 191 160 223 192 255 224 */
736 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
737 /* 287 256 319 288 351 320 383 352 */
738 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
739 /* 415 384 447 416 479 448 511 480 */
740 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
742 /* ownDmaChannels */
743 /* 31 0 63 32 */
744 {0x00000000u, 0x00000000u},
746 /* ownQdmaChannels */
747 /* 31 0 */
748 {0x00000000u},
750 /* ownTccs */
751 /* 31 0 63 32 */
752 {0x00000000u, 0x00000000u},
754 /* resvdPaRAMSets */
755 /* 31 0 63 32 95 64 127 96 */
756 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
757 /* 159 128 191 160 223 192 255 224 */
758 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
759 /* 287 256 319 288 351 320 383 352 */
760 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
761 /* 415 384 447 416 479 448 511 480 */
762 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
764 /* resvdDmaChannels */
765 /* 31 0 63 32 */
766 {0x00000000u, 0x00000000u},
768 /* resvdQdmaChannels */
769 /* 31 0 */
770 {0x00000000u},
772 /* resvdTccs */
773 /* 31 0 63 32 */
774 {0x00000000u, 0x00000000u},
775 },
777 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
778 {
779 /* ownPaRAMSets */
780 /* 31 0 63 32 95 64 127 96 */
781 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
782 /* 159 128 191 160 223 192 255 224 */
783 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
784 /* 287 256 319 288 351 320 383 352 */
785 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
786 /* 415 384 447 416 479 448 511 480 */
787 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
789 /* ownDmaChannels */
790 /* 31 0 63 32 */
791 {0x00000000u, 0x00000000u},
793 /* ownQdmaChannels */
794 /* 31 0 */
795 {0x00000000u},
797 /* ownTccs */
798 /* 31 0 63 32 */
799 {0x00000000u, 0x00000000u},
801 /* resvdPaRAMSets */
802 /* 31 0 63 32 95 64 127 96 */
803 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
804 /* 159 128 191 160 223 192 255 224 */
805 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
806 /* 287 256 319 288 351 320 383 352 */
807 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
808 /* 415 384 447 416 479 448 511 480 */
809 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
811 /* resvdDmaChannels */
812 /* 31 0 63 32 */
813 {0x00000000u, 0x00000000u},
815 /* resvdQdmaChannels */
816 /* 31 0 */
817 {0x00000000u},
819 /* resvdTccs */
820 /* 31 0 63 32 */
821 {0x00000000u, 0x00000000u},
822 },
823 },
824 };
826 /* Driver Instance Cross bar event to channel map Initialization Configuration */
827 EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
828 {
829 /* EDMA3 INSTANCE# 0 */
830 {
831 /* Event to channel map for region 0 */
832 {
833 {-1, -1, -1, -1, -1, -1, -1, -1,
834 -1, -1, -1, -1, -1, -1, -1, -1,
835 -1, -1, -1, -1, -1, -1, -1, -1,
836 -1, -1, -1, -1, -1, -1, -1}
837 },
838 /* Event to channel map for region 1 */
839 {
840 {-1, -1, -1, -1, -1, -1, -1, -1,
841 -1, -1, -1, -1, -1, -1, -1, -1,
842 -1, -1, -1, -1, -1, -1, -1, -1,
843 -1, 26, 27, -1, -1, -1, -1}
844 },
845 /* Event to channel map for region 2 */
846 {
847 {-1, -1, -1, -1, -1, -1, -1, -1,
848 -1, -1, -1, -1, -1, -1, -1, -1,
849 -1, -1, -1, -1, -1, -1, -1, -1,
850 -1, -1, -1, -1, -1, -1, -1}
851 },
852 /* Event to channel map for region 3 */
853 {
854 {-1, -1, -1, -1, -1, -1, -1, -1,
855 -1, -1, -1, -1, -1, -1, -1, -1,
856 -1, -1, -1, -1, -1, -1, -1, -1,
857 -1, -1, -1, -1, -1, -1, -1}
858 },
859 /* Event to channel map for region 4 */
860 {
861 {-1, -1, -1, -1, -1, -1, -1, -1,
862 -1, -1, -1, -1, -1, -1, -1, -1,
863 -1, -1, -1, -1, -1, -1, -1, -1,
864 -1, -1, -1, -1, -1, -1, -1}
865 },
866 /* Event to channel map for region 5 */
867 {
868 {-1, -1, -1, -1, -1, -1, -1, -1,
869 -1, -1, -1, -1, -1, -1, -1, -1,
870 -1, -1, -1, -1, -1, -1, -1, -1,
871 -1, -1, -1, -1, -1, -1, -1}
872 },
873 /* Event to channel map for region 6 */
874 {
875 {-1, -1, -1, -1, -1, -1, -1, -1,
876 -1, -1, -1, -1, -1, -1, -1, -1,
877 -1, -1, -1, -1, -1, -1, -1, -1,
878 -1, -1, -1, -1, -1, -1, -1}
879 },
880 /* Event to channel map for region 7 */
881 {
882 {-1, -1, -1, -1, -1, -1, -1, -1,
883 -1, -1, -1, -1, -1, -1, -1, -1,
884 -1, -1, -1, -1, -1, -1, -1, -1,
885 -1, -1, -1, -1, -1, -1, -1}
886 },
887 }
888 };
890 /* End of File */