OMAPL137 Integration: Config files for OMAPL137EVM
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_omapl137_arm_cfg.c
1 /*
2  * sample_omapl137_cfg.c
3  *
4  * Platform specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES         1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                    1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54     return 0;
55 }
57 signed char*  getGlobalAddr(signed char* addr)
58 {
59      return (addr); /* The address is already a global address */
60 }
62 unsigned short isGblConfigRequired(unsigned int dspNum)
63 {
64     (void) dspNum;
65     return 0;
66 }
68 /* Semaphore handles */
69 EDMA3_OS_Sem_Handle SemHandle[NUM_EDMA3_INSTANCES] = {NULL};
71 /** Number of PaRAM Sets available */
72 #define EDMA3_NUM_PARAMSET                              (128u)
73 /** Number of TCCS available */
74 #define EDMA3_NUM_TCC                                   (32u)
76 /** Number of Event Queues available                                          */
77 #define EDMA3_0_NUM_EVTQUE                              (2u)
79 /** Number of Transfer Controllers available                                  */
80 #define EDMA3_0_NUM_TC                                  (2u)
82 /** Interrupt no. for Transfer Completion                                     */
83 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (11u)
85 /** Interrupt no. for CC Error                                                */
86 #define EDMA3_0_CC_ERROR_INT                            (12u)
88 /** Interrupt no. for TCs Error                                               */
89 #define EDMA3_0_TC0_ERROR_INT                           (13u)
90 #define EDMA3_0_TC1_ERROR_INT                           (32u)
91 #define EDMA3_0_TC2_ERROR_INT                           (0u)
92 #define EDMA3_0_TC3_ERROR_INT                           (0u)
93 #define EDMA3_0_TC4_ERROR_INT                           (0u)
94 #define EDMA3_0_TC5_ERROR_INT                           (0u)
95 #define EDMA3_0_TC6_ERROR_INT                           (0u)
96 #define EDMA3_0_TC7_ERROR_INT                           (0u)
99 /**
100  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
101  * ECM events (SoC specific). These ECM events come
102  * under ECM block XXX (handling those specific ECM events). Normally, block
103  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
104  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
105  * is mapped to a specific HWI_INT YYY in the tcf file.
106  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
107  * to transfer completion interrupt.
108  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
109  * to CC error interrupts.
110  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
111  * to TC error interrupts.
112  */
113 /* EDMA 0 */
114 #define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
115 #define EDMA3_0_HWI_INT_CC_ERR                              (7u)
116 #define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
117 #define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
119 /**
120  * \brief Mapping of DMA channels 0-31 to Hardware Events from
121  * various peripherals, which use EDMA for data transfer.
122  * All channels need not be mapped, some can be free also.
123  * 1: Mapped
124  * 0: Not mapped
125  *
126  * This mapping will be used to allocate DMA channels when user passes
127  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
128  * copy). The same mapping is used to allocate the TCC when user passes
129  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
130  *
131  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
132  */
133                                                       /* 31     0 */
134 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFF3FF3FFu)
136 /**
137  * \brief Mapping of DMA channels 32-63 to Hardware Events from
138  * various peripherals, which use EDMA for data transfer.
139  * All channels need not be mapped, some can be free also.
140  * 1: Mapped
141  * 0: Not mapped
142  *
143  * This mapping will be used to allocate DMA channels when user passes
144  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
145  * copy). The same mapping is used to allocate the TCC when user passes
146  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
147  *
148  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
149  */
150 /* DMA channels 32-63 DOES NOT exist in omapl138. */
151 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
153 /* Variable which will be used internally for referring number of Event Queues*/
154 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
155                                                         EDMA3_0_NUM_EVTQUE
156                                                     };
158 /* Variable which will be used internally for referring number of TCs.        */
159 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
160                                                     EDMA3_0_NUM_TC
161                                                 };
163 /**
164  * Variable which will be used internally for referring transfer completion
165  * interrupt.
166  */
167 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
168                 {
169                     EDMA3_0_CC_XFER_COMPLETION_INT, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
170                 },
171             };
173 /**
174  * Variable which will be used internally for referring channel controller's
175  * error interrupt.
176  */
177 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
178                                                     EDMA3_0_CC_ERROR_INT
179                                                };
181 /**
182  * Variable which will be used internally for referring transfer controllers'
183  * error interrupts.
184  */
185 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
186                                {
187                                    EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
188                                    EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
189                                    EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
190                                    EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
191                                }
192                             };
194 /**
195  * Variables which will be used internally for referring the hardware interrupt
196  * for various EDMA3 interrupts.
197  */
198 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
199                                                     EDMA3_0_HWI_INT_XFER_COMP
200                                                   };
202 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
203                                                    EDMA3_0_HWI_INT_CC_ERR
204                                                };
206 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
207                                                      {
208                                                         EDMA3_0_HWI_INT_TC0_ERR,
209                                                         EDMA3_0_HWI_INT_TC1_ERR,
210                                                      }
211                                                };
213 /* Driver Object Initialization Configuration                                 */
214 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
216     {
217         /* EDMA3 INSTANCE# 0 */
218         /** Total number of DMA Channels supported by the EDMA3 Controller    */
219         32u,
220         /** Total number of QDMA Channels supported by the EDMA3 Controller   */
221         8u,
222         /** Total number of TCCs supported by the EDMA3 Controller            */
223         32u,
224         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
225         128u,
226         /** Total number of Event Queues in the EDMA3 Controller              */
227         2u,
228         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
229         2u,
230         /** Number of Regions on this EDMA3 controller                        */
231         4u,
233         /**
234          * \brief Channel mapping existence
235          * A value of 0 (No channel mapping) implies that there is fixed association
236          * for a channel number to a parameter entry number or, in other words,
237          * PaRAM entry n corresponds to channel n.
238          */
239         0u,
241         /** Existence of memory protection feature */
242         0u,
244         /** Global Register Region of CC Registers */
245         (void *)0x01C00000u,
246         /** Transfer Controller (TC) Registers */
247         {
248             (void *)0x01C08000u,
249             (void *)0x01C08400u,
250             (void *)NULL,
251             (void *)NULL,
252             (void *)NULL,
253             (void *)NULL,
254             (void *)NULL,
255             (void *)NULL
256         },
257         /** Interrupt no. for Transfer Completion */
258         EDMA3_0_CC_XFER_COMPLETION_INT,
259         /** Interrupt no. for CC Error */
260         EDMA3_0_CC_ERROR_INT,
261         /** Interrupt no. for TCs Error */
262         {
263             EDMA3_0_TC0_ERROR_INT,
264             EDMA3_0_TC1_ERROR_INT,
265             EDMA3_0_TC2_ERROR_INT,
266             EDMA3_0_TC3_ERROR_INT,
267             EDMA3_0_TC4_ERROR_INT,
268             EDMA3_0_TC5_ERROR_INT,
269             EDMA3_0_TC6_ERROR_INT,
270             EDMA3_0_TC7_ERROR_INT
271         },
273         /**
274          * \brief EDMA3 TC priority setting
275          *
276          * User can program the priority of the Event Queues
277          * at a system-wide level.  This means that the user can set the
278          * priority of an IO initiated by either of the TCs (Transfer Controllers)
279          * relative to IO initiated by the other bus masters on the
280          * device (ARM, DSP, USB, etc)
281          */
282         {
283             0u,
284             1u,
285             0u,
286             0u,
287             0u,
288             0u,
289             0u,
290             0u
291         },
292         /**
293          * \brief To Configure the Threshold level of number of events
294          * that can be queued up in the Event queues. EDMA3CC error register
295          * (CCERR) will indicate whether or not at any instant of time the
296          * number of events queued up in any of the event queues exceeds
297          * or equals the threshold/watermark value that is set
298          * in the queue watermark threshold register (QWMTHRA).
299          */
300         {
301             16u,
302             16u,
303             0u,
304             0u,
305             0u,
306             0u,
307             0u,
308             0u
309         },
311         /**
312          * \brief To Configure the Default Burst Size (DBS) of TCs.
313          * An optimally-sized command is defined by the transfer controller
314          * default burst size (DBS). Different TCs can have different
315          * DBS values. It is defined in Bytes.
316          */
317             {
318             16u,
319             16u,
320             0u,
321             0u,
322             0u,
323             0u,
324             0u,
325             0u
326             },
328         /**
329          * \brief Mapping from each DMA channel to a Parameter RAM set,
330          * if it exists, otherwise of no use.
331          */
332             {
333             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
334             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
335             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
336             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
337             /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
338             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
339             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
340             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
341             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
342             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
343             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
344             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
345             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
346             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
347             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
348             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
349             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
350             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
351             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
352             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
353             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
354             },
356          /**
357           * \brief Mapping from each DMA channel to a TCC. This specific
358           * TCC code will be returned when the transfer is completed
359           * on the mapped channel.
360           */
361             {
362             0u, 1u, 2u, 3u,
363             4u, 5u, 6u, 7u,
364             8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
365             12u, 13u, 14u, 15u,
366             16u, 17u, 18u, 19u,
367             20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
368             24u, 25u, 26u, 27u,
369             28u, 29u, 30u, 31u,
370             /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
371             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
372             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
373             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
374             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
375             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
376             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
377             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
378             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
379             },
381         /**
382          * \brief Mapping of DMA channels to Hardware Events from
383          * various peripherals, which use EDMA for data transfer.
384          * All channels need not be mapped, some can be free also.
385          */
386             {
387             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
388             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
389             }
390         },
391 };
394 /* Driver Instance Initialization Configuration */
395 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
397     /* EDMA3 INSTANCE# 0 */
398     {
399         /* Resources owned/reserved by region 0 */
400         {
401             /* ownPaRAMSets */
402             /* 31     0     63    32     95    64     127   96 */
403             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
404             /* 159  128     191  160     223  192     255  224 */
405              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
406             /* 287  256     319  288     351  320     383  352 */
407              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
408             /* 415  384     447  416     479  448     511  480 */
409              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
411             /* ownDmaChannels */
412             /* 31     0     63    32 */
413             {0xFFFFFFFFu, 0x00000000u},
415             /* ownQdmaChannels */
416             /* 31     0 */
417             {0x000000FFu},
419             /* ownTccs */
420             /* 31     0     63    32 */
421             {0xFFFFFFFFu, 0x00000000u},
423             /* Resources reserved by Region 1 */
424             /* resvdPaRAMSets */
425             /* 31     0     63    32     95    64     127   96 */
426             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
427             /* 159  128     191  160     223  192     255  224 */
428              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
429             /* 287  256     319  288     351  320     383  352 */
430              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
431             /* 415  384     447  416     479  448     511  480 */
432              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
434             /* resvdDmaChannels */
435             /* 31       0 */
436             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
437             /* 63..32 */
438             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
440             /* resvdQdmaChannels */
441             /* 31     0 */
442             {0x00000000u},
444             /* resvdTccs */
445             /* 31       0 */
446             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
447             /* 63..32 */
448             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
449         },
450         /* Resources owned/reserved by region 1 */
451         {
452             /* ownPaRAMSets */
453             /* 31     0     63    32     95    64     127   96 */
454             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
455             /* 159  128     191  160     223  192     255  224 */
456              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
457             /* 287  256     319  288     351  320     383  352 */
458              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
459             /* 415  384     447  416     479  448     511  480 */
460              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
462             /* ownDmaChannels */
463             /* 31     0     63    32 */
464             {0xFFFFFFFFu, 0x00000000u},
466             /* ownQdmaChannels */
467             /* 31     0 */
468             {0x000000FFu},
470             /* ownTccs */
471             /* 31     0     63    32 */
472             {0xFFFFFFFFu, 0x00000000u},
474             /* Resources reserved by Region 1 */
475             /* resvdPaRAMSets */
476             /* 31     0     63    32     95    64     127   96 */
477             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
478             /* 159  128     191  160     223  192     255  224 */
479              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
480             /* 287  256     319  288     351  320     383  352 */
481              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
482             /* 415  384     447  416     479  448     511  480 */
483              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
485             /* resvdDmaChannels */
486             /* 31       0 */
487             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
488             /* 63..32 */
489             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
491             /* resvdQdmaChannels */
492             /* 31     0 */
493             {0x00000000u},
495             /* resvdTccs */
496             /* 31       0 */
497             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
498             /* 63..32 */
499             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
500         },
501         /* Resources owned/reserved by region 2 */
502         {
503             /* ownPaRAMSets */
504             /* 31     0     63    32     95    64     127   96 */
505             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
506             /* 159  128     191  160     223  192     255  224 */
507              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
508             /* 287  256     319  288     351  320     383  352 */
509              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
510             /* 415  384     447  416     479  448     511  480 */
511              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
513             /* ownDmaChannels */
514             /* 31     0     63    32 */
515             {0x00000000u, 0x00000000u},
517             /* ownQdmaChannels */
518             /* 31     0 */
519             {0x00000000u},
521             /* ownTccs */
522             /* 31     0     63    32 */
523             {0x00000000u, 0x00000000u},
525             /* resvdPaRAMSets */
526             /* 31     0     63    32     95    64     127   96 */
527             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
528             /* 159  128     191  160     223  192     255  224 */
529              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
530             /* 287  256     319  288     351  320     383  352 */
531              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
532             /* 415  384     447  416     479  448     511  480 */
533              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
535             /* resvdDmaChannels */
536             /* 31     0     63    32 */
537             {0x00000000u, 0x00000000u},
539             /* resvdQdmaChannels */
540             /* 31     0 */
541             {0x00000000u},
543             /* resvdTccs */
544             /* 31     0     63    32 */
545             {0x00000000u, 0x00000000u},
546         },
548         /* Resources owned/reserved by region 3 */
549         {
550             /* ownPaRAMSets */
551             /* 31     0     63    32     95    64     127   96 */
552             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
553             /* 159  128     191  160     223  192     255  224 */
554              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
555             /* 287  256     319  288     351  320     383  352 */
556              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
557             /* 415  384     447  416     479  448     511  480 */
558              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
560             /* ownDmaChannels */
561             /* 31     0     63    32 */
562             {0x00000000u, 0x00000000u},
564             /* ownQdmaChannels */
565             /* 31     0 */
566             {0x00000000u},
568             /* ownTccs */
569             /* 31     0     63    32 */
570             {0x00000000u, 0x00000000u},
572             /* resvdPaRAMSets */
573             /* 31     0     63    32     95    64     127   96 */
574             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
575             /* 159  128     191  160     223  192     255  224 */
576              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
577             /* 287  256     319  288     351  320     383  352 */
578              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
579             /* 415  384     447  416     479  448     511  480 */
580              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
582             /* resvdDmaChannels */
583             /* 31     0     63    32 */
584             {0x00000000u, 0x00000000u},
586             /* resvdQdmaChannels */
587             /* 31     0 */
588             {0x00000000u},
590             /* resvdTccs */
591             /* 31     0     63    32 */
592             {0x00000000u, 0x00000000u},
593         },
595         /* Resources owned/reserved by region 4 */
596         {
597             /* ownPaRAMSets */
598             /* 31     0     63    32     95    64     127   96 */
599             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
600             /* 159  128     191  160     223  192     255  224 */
601              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
602             /* 287  256     319  288     351  320     383  352 */
603              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
604             /* 415  384     447  416     479  448     511  480 */
605              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
607             /* ownDmaChannels */
608             /* 31     0     63    32 */
609             {0x00000000u, 0x00000000u},
611             /* ownQdmaChannels */
612             /* 31     0 */
613             {0x00000000u},
615             /* ownTccs */
616             /* 31     0     63    32 */
617             {0x00000000u, 0x00000000u},
619             /* resvdPaRAMSets */
620             /* 31     0     63    32     95    64     127   96 */
621             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
622             /* 159  128     191  160     223  192     255  224 */
623              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
624             /* 287  256     319  288     351  320     383  352 */
625              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
626             /* 415  384     447  416     479  448     511  480 */
627              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
629             /* resvdDmaChannels */
630             /* 31     0     63    32 */
631             {0x00000000u, 0x00000000u},
633             /* resvdQdmaChannels */
634             /* 31     0 */
635             {0x00000000u},
637             /* resvdTccs */
638             /* 31     0     63    32 */
639             {0x00000000u, 0x00000000u},
640         },
642         /* Resources owned/reserved by region 5 */
643         {
644             /* ownPaRAMSets */
645             /* 31     0     63    32     95    64     127   96 */
646             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
647             /* 159  128     191  160     223  192     255  224 */
648              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
649             /* 287  256     319  288     351  320     383  352 */
650              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
651             /* 415  384     447  416     479  448     511  480 */
652              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
654             /* ownDmaChannels */
655             /* 31     0     63    32 */
656             {0x00000000u, 0x00000000u},
658             /* ownQdmaChannels */
659             /* 31     0 */
660             {0x00000000u},
662             /* ownTccs */
663             /* 31     0     63    32 */
664             {0x00000000u, 0x00000000u},
666             /* resvdPaRAMSets */
667             /* 31     0     63    32     95    64     127   96 */
668             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
669             /* 159  128     191  160     223  192     255  224 */
670              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
671             /* 287  256     319  288     351  320     383  352 */
672              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
673             /* 415  384     447  416     479  448     511  480 */
674              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
676             /* resvdDmaChannels */
677             /* 31     0     63    32 */
678             {0x00000000u, 0x00000000u},
680             /* resvdQdmaChannels */
681             /* 31     0 */
682             {0x00000000u},
684             /* resvdTccs */
685             /* 31     0     63    32 */
686             {0x00000000u, 0x00000000u},
687         },
689         /* Resources owned/reserved by region 6 */
690         {
691             /* ownPaRAMSets */
692             /* 31     0     63    32     95    64     127   96 */
693             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
694             /* 159  128     191  160     223  192     255  224 */
695              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
696             /* 287  256     319  288     351  320     383  352 */
697              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
698             /* 415  384     447  416     479  448     511  480 */
699              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
701             /* ownDmaChannels */
702             /* 31     0     63    32 */
703             {0x00000000u, 0x00000000u},
705             /* ownQdmaChannels */
706             /* 31     0 */
707             {0x00000000u},
709             /* ownTccs */
710             /* 31     0     63    32 */
711             {0x00000000u, 0x00000000u},
713             /* resvdPaRAMSets */
714             /* 31     0     63    32     95    64     127   96 */
715             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
716             /* 159  128     191  160     223  192     255  224 */
717              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
718             /* 287  256     319  288     351  320     383  352 */
719              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
720             /* 415  384     447  416     479  448     511  480 */
721              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
723             /* resvdDmaChannels */
724             /* 31     0     63    32 */
725             {0x00000000u, 0x00000000u},
727             /* resvdQdmaChannels */
728             /* 31     0 */
729             {0x00000000u},
731             /* resvdTccs */
732             /* 31     0     63    32 */
733             {0x00000000u, 0x00000000u},
734         },
736         /* Resources owned/reserved by region 7 */
737         {
738             /* ownPaRAMSets */
739             /* 31     0     63    32     95    64     127   96 */
740             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
741             /* 159  128     191  160     223  192     255  224 */
742              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
743             /* 287  256     319  288     351  320     383  352 */
744              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
745             /* 415  384     447  416     479  448     511  480 */
746              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
748             /* ownDmaChannels */
749             /* 31     0     63    32 */
750             {0x00000000u, 0x00000000u},
752             /* ownQdmaChannels */
753             /* 31     0 */
754             {0x00000000u},
756             /* ownTccs */
757             /* 31     0     63    32 */
758             {0x00000000u, 0x00000000u},
760             /* resvdPaRAMSets */
761             /* 31     0     63    32     95    64     127   96 */
762             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
763             /* 159  128     191  160     223  192     255  224 */
764              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
765             /* 287  256     319  288     351  320     383  352 */
766              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
767             /* 415  384     447  416     479  448     511  480 */
768              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
770             /* resvdDmaChannels */
771             /* 31     0     63    32 */
772             {0x00000000u, 0x00000000u},
774             /* resvdQdmaChannels */
775             /* 31     0 */
776             {0x00000000u},
778             /* resvdTccs */
779             /* 31     0     63    32 */
780             {0x00000000u, 0x00000000u},
781         },
782     }
783 };
785 /* End of File */