OMAPL137 Integration: Config files for OMAPL137EVM
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_omapl137_cfg.c
1 /*
2  * sample_omapl137_cfg.c
3  *
4  * Platform specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2009 - 2017 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES         1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                    1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54     return 1;
55 }
57 signed char*  getGlobalAddr(signed char* addr)
58 {
59      return (addr); /* The address is already a global address */
60 }
61 unsigned short isGblConfigRequired(unsigned int dspNum)
62 {
63     (void) dspNum;
65     return 1;
66 }
68 /* Semaphore handles */
69 EDMA3_OS_Sem_Handle SemHandle[NUM_EDMA3_INSTANCES] = {NULL};
71 /** Number of PaRAM Sets available */
72 #define EDMA3_NUM_PARAMSET                              (128u)
73 /** Number of TCCS available */
74 #define EDMA3_NUM_TCC                                   (32u)
76 /** Number of Event Queues available                                          */
77 #define EDMA3_0_NUM_EVTQUE                              (2u)
79 /** Number of Transfer Controllers available                                  */
80 #define EDMA3_0_NUM_TC                                  (2u)
82 #ifdef __TMS470__  /* values for ARM */
84 #else /* values for DSP */
85 /** Interrupt no. for Transfer Completion                                     */
86 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (8u)
88 /** Interrupt no. for CC Error                                                */
89 #define EDMA3_0_CC_ERROR_INT                            (56u)
91 /** Interrupt no. for TCs Error                                               */
92 #define EDMA3_0_TC0_ERROR_INT                           (57u)
93 #define EDMA3_0_TC1_ERROR_INT                           (58u)
94 #define EDMA3_0_TC2_ERROR_INT                           (0u)
95 #define EDMA3_0_TC3_ERROR_INT                           (0u)
96 #define EDMA3_0_TC4_ERROR_INT                           (0u)
97 #define EDMA3_0_TC5_ERROR_INT                           (0u)
98 #define EDMA3_0_TC6_ERROR_INT                           (0u)
99 #define EDMA3_0_TC7_ERROR_INT                           (0u)
101 /**
102  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
103  * ECM events (SoC specific). These ECM events come
104  * under ECM block XXX (handling those specific ECM events). Normally, block
105  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
106  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
107  * is mapped to a specific HWI_INT YYY in the tcf file.
108  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
109  * to transfer completion interrupt.
110  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
111  * to CC error interrupts.
112  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
113  * to TC error interrupts.
114  */
115 /* EDMA 0 */
116 #define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
117 #define EDMA3_0_HWI_INT_CC_ERR                              (8u)
118 #define EDMA3_0_HWI_INT_TC0_ERR                             (8u)
119 #define EDMA3_0_HWI_INT_TC1_ERR                             (8u)
121 #endif  /* __TMS470__ */
123 /**
124  * \brief Mapping of DMA channels 0-31 to Hardware Events from
125  * various peripherals, which use EDMA for data transfer.
126  * All channels need not be mapped, some can be free also.
127  * 1: Mapped
128  * 0: Not mapped
129  *
130  * This mapping will be used to allocate DMA channels when user passes
131  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
132  * copy). The same mapping is used to allocate the TCC when user passes
133  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
134  *
135  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
136  */
137                                                       /* 31     0 */
138 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFF3FF3FFu)
140 /**
141  * \brief Mapping of DMA channels 32-63 to Hardware Events from
142  * various peripherals, which use EDMA for data transfer.
143  * All channels need not be mapped, some can be free also.
144  * 1: Mapped
145  * 0: Not mapped
146  *
147  * This mapping will be used to allocate DMA channels when user passes
148  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
149  * copy). The same mapping is used to allocate the TCC when user passes
150  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
151  *
152  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
153  */
154 /* DMA channels 32-63 DOES NOT exist in omapl138. */
155 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
157 /* Variable which will be used internally for referring number of Event Queues*/
158 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
159                                                         EDMA3_0_NUM_EVTQUE
160                                                     };
162 /* Variable which will be used internally for referring number of TCs.        */
163 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
164                                                     EDMA3_0_NUM_TC
165                                                 };
167 /**
168  * Variable which will be used internally for referring transfer completion
169  * interrupt.
170  */
171 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
172                 {
173                     0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
174                 },
175             };
177 /**
178  * Variable which will be used internally for referring channel controller's
179  * error interrupt.
180  */
181 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
182                                                     EDMA3_0_CC_ERROR_INT
183                                                };
185 /**
186  * Variable which will be used internally for referring transfer controllers'
187  * error interrupts.
188  */
189 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
190                                {
191                                    EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
192                                    EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
193                                    EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
194                                    EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
195                                }
196                             };
198 /**
199  * Variables which will be used internally for referring the hardware interrupt
200  * for various EDMA3 interrupts.
201  */
202 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
203                                                     EDMA3_0_HWI_INT_XFER_COMP
204                                                   };
206 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
207                                                    EDMA3_0_HWI_INT_CC_ERR
208                                                };
210 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
211                                                      {
212                                                         EDMA3_0_HWI_INT_TC0_ERR,
213                                                         EDMA3_0_HWI_INT_TC1_ERR,
214                                                      }
215                                                };
217 /* Driver Object Initialization Configuration                                 */
218 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
220     {
221         /* EDMA3 INSTANCE# 0 */
222         /** Total number of DMA Channels supported by the EDMA3 Controller    */
223         32u,
224         /** Total number of QDMA Channels supported by the EDMA3 Controller   */
225         8u,
226         /** Total number of TCCs supported by the EDMA3 Controller            */
227         32u,
228         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
229         128u,
230         /** Total number of Event Queues in the EDMA3 Controller              */
231         2u,
232         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
233         2u,
234         /** Number of Regions on this EDMA3 controller                        */
235         4u,
237         /**
238          * \brief Channel mapping existence
239          * A value of 0 (No channel mapping) implies that there is fixed association
240          * for a channel number to a parameter entry number or, in other words,
241          * PaRAM entry n corresponds to channel n.
242          */
243         0u,
245         /** Existence of memory protection feature */
246         0u,
248         /** Global Register Region of CC Registers */
249         (void *)0x01C00000u,
250         /** Transfer Controller (TC) Registers */
251         {
252             (void *)0x01C08000u,
253             (void *)0x01C08400u,
254             (void *)NULL,
255             (void *)NULL,
256             (void *)NULL,
257             (void *)NULL,
258             (void *)NULL,
259             (void *)NULL
260         },
261         /** Interrupt no. for Transfer Completion */
262         EDMA3_0_CC_XFER_COMPLETION_INT,
263         /** Interrupt no. for CC Error */
264         EDMA3_0_CC_ERROR_INT,
265         /** Interrupt no. for TCs Error */
266         {
267             EDMA3_0_TC0_ERROR_INT,
268             EDMA3_0_TC1_ERROR_INT,
269             EDMA3_0_TC2_ERROR_INT,
270             EDMA3_0_TC3_ERROR_INT,
271             EDMA3_0_TC4_ERROR_INT,
272             EDMA3_0_TC5_ERROR_INT,
273             EDMA3_0_TC6_ERROR_INT,
274             EDMA3_0_TC7_ERROR_INT
275         },
277         /**
278          * \brief EDMA3 TC priority setting
279          *
280          * User can program the priority of the Event Queues
281          * at a system-wide level.  This means that the user can set the
282          * priority of an IO initiated by either of the TCs (Transfer Controllers)
283          * relative to IO initiated by the other bus masters on the
284          * device (ARM, DSP, USB, etc)
285          */
286         {
287             0u,
288             1u,
289             0u,
290             0u,
291             0u,
292             0u,
293             0u,
294             0u
295         },
296         /**
297          * \brief To Configure the Threshold level of number of events
298          * that can be queued up in the Event queues. EDMA3CC error register
299          * (CCERR) will indicate whether or not at any instant of time the
300          * number of events queued up in any of the event queues exceeds
301          * or equals the threshold/watermark value that is set
302          * in the queue watermark threshold register (QWMTHRA).
303          */
304         {
305             16u,
306             16u,
307             0u,
308             0u,
309             0u,
310             0u,
311             0u,
312             0u
313         },
315         /**
316          * \brief To Configure the Default Burst Size (DBS) of TCs.
317          * An optimally-sized command is defined by the transfer controller
318          * default burst size (DBS). Different TCs can have different
319          * DBS values. It is defined in Bytes.
320          */
321             {
322             16u,
323             16u,
324             0u,
325             0u,
326             0u,
327             0u,
328             0u,
329             0u
330             },
332         /**
333          * \brief Mapping from each DMA channel to a Parameter RAM set,
334          * if it exists, otherwise of no use.
335          */
336             {
337             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
338             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
339             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
340             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
341             /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
342             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
343             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
344             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
345             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
346             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
347             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
348             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
349             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
350             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
351             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
352             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
353             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
354             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
355             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
356             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
357             EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
358             },
360          /**
361           * \brief Mapping from each DMA channel to a TCC. This specific
362           * TCC code will be returned when the transfer is completed
363           * on the mapped channel.
364           */
365             {
366             0u, 1u, 2u, 3u,
367             4u, 5u, 6u, 7u,
368             8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
369             12u, 13u, 14u, 15u,
370             16u, 17u, 18u, 19u,
371             20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
372             24u, 25u, 26u, 27u,
373             28u, 29u, 30u, 31u,
374             /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
375             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
376             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
377             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
378             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
379             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
380             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
381             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
382             EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
383             },
385         /**
386          * \brief Mapping of DMA channels to Hardware Events from
387          * various peripherals, which use EDMA for data transfer.
388          * All channels need not be mapped, some can be free also.
389          */
390             {
391             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
392             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
393             }
394     },
395 };
398 /* Driver Instance Initialization Configuration */
399 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
401     /* EDMA3 INSTANCE# 0 */
402     {
403         /* Resources owned/reserved by region 0 */
404         {
405             /* ownPaRAMSets */
406             /* 31     0     63    32     95    64     127   96 */
407             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
408             /* 159  128     191  160     223  192     255  224 */
409              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
410             /* 287  256     319  288     351  320     383  352 */
411              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
412             /* 415  384     447  416     479  448     511  480 */
413              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
415             /* ownDmaChannels */
416             /* 31     0     63    32 */
417             {0x00000000u, 0x00000000u},
419             /* ownQdmaChannels */
420             /* 31     0 */
421             {0x00000000u},
423             /* ownTccs */
424             /* 31     0     63    32 */
425             {0x00000000u, 0x00000000u},
427             /* resvdPaRAMSets */
428             /* 31     0     63    32     95    64     127   96 */
429             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
430             /* 159  128     191  160     223  192     255  224 */
431              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
432             /* 287  256     319  288     351  320     383  352 */
433              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
434             /* 415  384     447  416     479  448     511  480 */
435              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
437             /* resvdDmaChannels */
438             /* 31     0     63    32 */
439             {0x00000000u, 0x00000000u},
441             /* resvdQdmaChannels */
442             /* 31     0 */
443             {0x00000000u},
445             /* resvdTccs */
446             /* 31     0     63    32 */
447             {0x00000000u, 0x00000000u},
448         },
449         /* Resources owned/reserved by region 1 */
450         {
451             /* ownPaRAMSets */
452             /* 31     0     63    32     95    64     127   96 */
453             {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
454             /* 159  128     191  160     223  192     255  224 */
455              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
456             /* 287  256     319  288     351  320     383  352 */
457              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
458             /* 415  384     447  416     479  448     511  480 */
459              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
461             /* ownDmaChannels */
462             /* 31     0     63    32 */
463             {0xFFFFFFFFu, 0x00000000u},
465             /* ownQdmaChannels */
466             /* 31     0 */
467             {0x000000FFu},
469             /* ownTccs */
470             /* 31     0     63    32 */
471             {0xFFFFFFFFu, 0x00000000u},
473             /* Resources reserved by Region 1 */
474             /* resvdPaRAMSets */
475             /* 31     0     63    32     95    64     127   96 */
476             {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
477             /* 159  128     191  160     223  192     255  224 */
478              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
479             /* 287  256     319  288     351  320     383  352 */
480              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
481             /* 415  384     447  416     479  448     511  480 */
482              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
484             /* resvdDmaChannels */
485             /* 31       0 */
486             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
487             /* 63..32 */
488             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
490             /* resvdQdmaChannels */
491             /* 31     0 */
492             {0x00000000u},
494             /* resvdTccs */
495             /* 31       0 */
496             {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
497             /* 63..32 */
498             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
499         },
500         /* Resources owned/reserved by region 2 */
501         {
502             /* ownPaRAMSets */
503             /* 31     0     63    32     95    64     127   96 */
504             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
505             /* 159  128     191  160     223  192     255  224 */
506              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
507             /* 287  256     319  288     351  320     383  352 */
508              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
509             /* 415  384     447  416     479  448     511  480 */
510              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
512             /* ownDmaChannels */
513             /* 31     0     63    32 */
514             {0x00000000u, 0x00000000u},
516             /* ownQdmaChannels */
517             /* 31     0 */
518             {0x00000000u},
520             /* ownTccs */
521             /* 31     0     63    32 */
522             {0x00000000u, 0x00000000u},
524             /* resvdPaRAMSets */
525             /* 31     0     63    32     95    64     127   96 */
526             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
527             /* 159  128     191  160     223  192     255  224 */
528              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
529             /* 287  256     319  288     351  320     383  352 */
530              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
531             /* 415  384     447  416     479  448     511  480 */
532              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
534             /* resvdDmaChannels */
535             /* 31     0     63    32 */
536             {0x00000000u, 0x00000000u},
538             /* resvdQdmaChannels */
539             /* 31     0 */
540             {0x00000000u},
542             /* resvdTccs */
543             /* 31     0     63    32 */
544             {0x00000000u, 0x00000000u},
545         },
547         /* Resources owned/reserved by region 3 */
548         {
549             /* ownPaRAMSets */
550             /* 31     0     63    32     95    64     127   96 */
551             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
552             /* 159  128     191  160     223  192     255  224 */
553              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
554             /* 287  256     319  288     351  320     383  352 */
555              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
556             /* 415  384     447  416     479  448     511  480 */
557              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
559             /* ownDmaChannels */
560             /* 31     0     63    32 */
561             {0x00000000u, 0x00000000u},
563             /* ownQdmaChannels */
564             /* 31     0 */
565             {0x00000000u},
567             /* ownTccs */
568             /* 31     0     63    32 */
569             {0x00000000u, 0x00000000u},
571             /* resvdPaRAMSets */
572             /* 31     0     63    32     95    64     127   96 */
573             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
574             /* 159  128     191  160     223  192     255  224 */
575              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
576             /* 287  256     319  288     351  320     383  352 */
577              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
578             /* 415  384     447  416     479  448     511  480 */
579              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
581             /* resvdDmaChannels */
582             /* 31     0     63    32 */
583             {0x00000000u, 0x00000000u},
585             /* resvdQdmaChannels */
586             /* 31     0 */
587             {0x00000000u},
589             /* resvdTccs */
590             /* 31     0     63    32 */
591             {0x00000000u, 0x00000000u},
592         },
594         /* Resources owned/reserved by region 4 */
595         {
596             /* ownPaRAMSets */
597             /* 31     0     63    32     95    64     127   96 */
598             {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
599             /* 159  128     191  160     223  192     255  224 */
600              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
601             /* 287  256     319  288     351  320     383  352 */
602              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
603             /* 415  384     447  416     479  448     511  480 */
604              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
606             /* ownDmaChannels */
607             /* 31     0     63    32 */
608             {0x00000000u, 0x00000000u},
610             /* ownQdmaChannels */
611             /* 31     0 */
612             {0x00000000u},
614             /* ownTccs */
615             /* 31     0     63    32 */
616             {0x00000000u, 0x00000000u},
618             /* resvdPaRAMSets */
619             /* 31     0     63    32     95    64     127   96 */
620             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
621             /* 159  128     191  160     223  192     255  224 */
622              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
623             /* 287  256     319  288     351  320     383  352 */
624              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
625             /* 415  384     447  416     479  448     511  480 */
626              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
628             /* resvdDmaChannels */
629             /* 31     0     63    32 */
630             {0x00000000u, 0x00000000u},
632             /* resvdQdmaChannels */
633             /* 31     0 */
634             {0x00000000u},
636             /* resvdTccs */
637             /* 31     0     63    32 */
638             {0x00000000u, 0x00000000u},
639         },
641         /* Resources owned/reserved by region 5 */
642         {
643             /* ownPaRAMSets */
644             /* 31     0     63    32     95    64     127   96 */
645             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
646             /* 159  128     191  160     223  192     255  224 */
647              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
648             /* 287  256     319  288     351  320     383  352 */
649              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
650             /* 415  384     447  416     479  448     511  480 */
651              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
653             /* ownDmaChannels */
654             /* 31     0     63    32 */
655             {0x00000000u, 0x00000000u},
657             /* ownQdmaChannels */
658             /* 31     0 */
659             {0x00000000u},
661             /* ownTccs */
662             /* 31     0     63    32 */
663             {0x00000000u, 0x00000000u},
665             /* resvdPaRAMSets */
666             /* 31     0     63    32     95    64     127   96 */
667             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
668             /* 159  128     191  160     223  192     255  224 */
669              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
670             /* 287  256     319  288     351  320     383  352 */
671              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
672             /* 415  384     447  416     479  448     511  480 */
673              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
675             /* resvdDmaChannels */
676             /* 31     0     63    32 */
677             {0x00000000u, 0x00000000u},
679             /* resvdQdmaChannels */
680             /* 31     0 */
681             {0x00000000u},
683             /* resvdTccs */
684             /* 31     0     63    32 */
685             {0x00000000u, 0x00000000u},
686         },
688         /* Resources owned/reserved by region 6 */
689         {
690             /* ownPaRAMSets */
691             /* 31     0     63    32     95    64     127   96 */
692             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
693             /* 159  128     191  160     223  192     255  224 */
694              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
695             /* 287  256     319  288     351  320     383  352 */
696              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
697             /* 415  384     447  416     479  448     511  480 */
698              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
700             /* ownDmaChannels */
701             /* 31     0     63    32 */
702             {0x00000000u, 0x00000000u},
704             /* ownQdmaChannels */
705             /* 31     0 */
706             {0x00000000u},
708             /* ownTccs */
709             /* 31     0     63    32 */
710             {0x00000000u, 0x00000000u},
712             /* resvdPaRAMSets */
713             /* 31     0     63    32     95    64     127   96 */
714             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
715             /* 159  128     191  160     223  192     255  224 */
716              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
717             /* 287  256     319  288     351  320     383  352 */
718              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
719             /* 415  384     447  416     479  448     511  480 */
720              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
722             /* resvdDmaChannels */
723             /* 31     0     63    32 */
724             {0x00000000u, 0x00000000u},
726             /* resvdQdmaChannels */
727             /* 31     0 */
728             {0x00000000u},
730             /* resvdTccs */
731             /* 31     0     63    32 */
732             {0x00000000u, 0x00000000u},
733         },
735         /* Resources owned/reserved by region 7 */
736         {
737             /* ownPaRAMSets */
738             /* 31     0     63    32     95    64     127   96 */
739             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
740             /* 159  128     191  160     223  192     255  224 */
741              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
742             /* 287  256     319  288     351  320     383  352 */
743              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
744             /* 415  384     447  416     479  448     511  480 */
745              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
747             /* ownDmaChannels */
748             /* 31     0     63    32 */
749             {0x00000000u, 0x00000000u},
751             /* ownQdmaChannels */
752             /* 31     0 */
753             {0x00000000u},
755             /* ownTccs */
756             /* 31     0     63    32 */
757             {0x00000000u, 0x00000000u},
759             /* resvdPaRAMSets */
760             /* 31     0     63    32     95    64     127   96 */
761             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
762             /* 159  128     191  160     223  192     255  224 */
763              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
764             /* 287  256     319  288     351  320     383  352 */
765              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
766             /* 415  384     447  416     479  448     511  480 */
767              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
769             /* resvdDmaChannels */
770             /* 31     0     63    32 */
771             {0x00000000u, 0x00000000u},
773             /* resvdQdmaChannels */
774             /* 31     0 */
775             {0x00000000u},
777             /* resvdTccs */
778             /* 31     0     63    32 */
779             {0x00000000u, 0x00000000u},
780         },
781     }
782 };
784 /* End of File */