33df24990da0c9537f657d94bd9b71cc58c93d63
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_omapl138_cfg.c
1 /*
2 * sample_omapl138_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 2u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 1u
49 const unsigned int numDsps = NUM_DSPS;
51 /* Determine the processor id by reading DNUM register. */
52 unsigned short determineProcId()
53 {
54 #if 0
55 volatile unsigned int *addr;
56 unsigned int core_no;
58 /* Identify the core number */
59 addr = (unsigned int *)(CGEM_REG_START+0x40000);
60 core_no = ((*addr) & 0x000F0000)>>16;
62 return core_no;
63 #endif
64 return 1;
65 }
67 unsigned short isGblConfigRequired(unsigned int dspNum)
68 {
69 (void) dspNum;
71 return 1;
72 }
74 /* Semaphore handles */
75 EDMA3_OS_Sem_Handle rmSemHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL};
77 /** Number of PaRAM Sets available */
78 #define EDMA3_NUM_PARAMSET (128u)
79 /** Number of TCCS available */
80 #define EDMA3_NUM_TCC (32u)
82 /** Number of Event Queues available */
83 #define EDMA3_0_NUM_EVTQUE (2u)
84 #define EDMA3_1_NUM_EVTQUE (1u)
86 /** Number of Transfer Controllers available */
87 #define EDMA3_0_NUM_TC (2u)
88 #define EDMA3_1_NUM_TC (1u)
90 #ifdef __TMS470__ /* values for ARM */
92 #else /* values for DSP */
93 /** Interrupt no. for Transfer Completion */
94 #define EDMA3_0_CC_XFER_COMPLETION_INT (8u)
95 #define EDMA3_1_CC_XFER_COMPLETION_INT (91u)
97 /** Interrupt no. for CC Error */
98 #define EDMA3_0_CC_ERROR_INT (56u)
99 #define EDMA3_1_CC_ERROR_INT (92u)
101 /** Interrupt no. for TCs Error */
102 #define EDMA3_0_TC0_ERROR_INT (57u)
103 #define EDMA3_0_TC1_ERROR_INT (58u)
104 #define EDMA3_0_TC2_ERROR_INT (0u)
105 #define EDMA3_0_TC3_ERROR_INT (0u)
106 #define EDMA3_0_TC4_ERROR_INT (0u)
107 #define EDMA3_0_TC5_ERROR_INT (0u)
108 #define EDMA3_0_TC6_ERROR_INT (0u)
109 #define EDMA3_0_TC7_ERROR_INT (0u)
111 #define EDMA3_1_TC0_ERROR_INT (93u)
112 #define EDMA3_1_TC1_ERROR_INT (0u)
113 #define EDMA3_1_TC2_ERROR_INT (0u)
114 #define EDMA3_1_TC3_ERROR_INT (0u)
115 #define EDMA3_1_TC4_ERROR_INT (0u)
116 #define EDMA3_1_TC5_ERROR_INT (0u)
117 #define EDMA3_1_TC6_ERROR_INT (0u)
118 #define EDMA3_1_TC7_ERROR_INT (0u)
120 /**
121 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
122 * ECM events (SoC specific). These ECM events come
123 * under ECM block XXX (handling those specific ECM events). Normally, block
124 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
125 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
126 * is mapped to a specific HWI_INT YYY in the tcf file.
127 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
128 * to transfer completion interrupt.
129 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
130 * to CC error interrupts.
131 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
132 * to TC error interrupts.
133 */
134 /* EDMA 0 */
135 #define EDMA3_0_HWI_INT_XFER_COMP (7u)
136 #define EDMA3_0_HWI_INT_CC_ERR (8u)
137 #define EDMA3_0_HWI_INT_TC0_ERR (8u)
138 #define EDMA3_0_HWI_INT_TC1_ERR (8u)
140 /* EDMA 1 */
141 #define EDMA3_1_HWI_INT_XFER_COMP (9u)
142 #define EDMA3_1_HWI_INT_CC_ERR (9u)
143 #define EDMA3_1_HWI_INT_TC0_ERR (9u)
145 #endif /* __TMS470__ */
147 /**
148 * \brief Mapping of DMA channels 0-31 to Hardware Events from
149 * various peripherals, which use EDMA for data transfer.
150 * All channels need not be mapped, some can be free also.
151 * 1: Mapped
152 * 0: Not mapped
153 *
154 * This mapping will be used to allocate DMA channels when user passes
155 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
156 * copy). The same mapping is used to allocate the TCC when user passes
157 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
158 *
159 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
160 */
161 /* 31 0 */
162 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFF3FF3FFu)
163 #define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x3F07FFFFu)
165 /**
166 * \brief Mapping of DMA channels 32-63 to Hardware Events from
167 * various peripherals, which use EDMA for data transfer.
168 * All channels need not be mapped, some can be free also.
169 * 1: Mapped
170 * 0: Not mapped
171 *
172 * This mapping will be used to allocate DMA channels when user passes
173 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
174 * copy). The same mapping is used to allocate the TCC when user passes
175 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
176 *
177 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
178 */
179 /* DMA channels 32-63 DOES NOT exist in omapl138. */
180 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u)
181 #define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u)
183 /* Variable which will be used internally for referring number of Event Queues*/
184 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
185 EDMA3_0_NUM_EVTQUE,
186 EDMA3_1_NUM_EVTQUE
187 };
189 /* Variable which will be used internally for referring number of TCs. */
190 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {
191 EDMA3_0_NUM_TC,
192 EDMA3_1_NUM_TC
193 };
195 /**
196 * Variable which will be used internally for referring transfer completion
197 * interrupt.
198 */
199 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
200 {
201 0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
202 },
203 {
204 0u, EDMA3_1_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
205 },
206 };
208 /**
209 * Variable which will be used internally for referring channel controller's
210 * error interrupt.
211 */
212 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
213 EDMA3_0_CC_ERROR_INT,
214 EDMA3_1_CC_ERROR_INT
215 };
217 /**
218 * Variable which will be used internally for referring transfer controllers'
219 * error interrupts.
220 */
221 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
222 {
223 EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
224 EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
225 EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
226 EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
227 },
228 {
229 EDMA3_1_TC0_ERROR_INT, EDMA3_1_TC1_ERROR_INT,
230 EDMA3_1_TC2_ERROR_INT, EDMA3_1_TC3_ERROR_INT,
231 EDMA3_1_TC4_ERROR_INT, EDMA3_1_TC5_ERROR_INT,
232 EDMA3_1_TC6_ERROR_INT, EDMA3_1_TC7_ERROR_INT,
233 }
234 };
236 /**
237 * Variables which will be used internally for referring the hardware interrupt
238 * for various EDMA3 interrupts.
239 */
240 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
241 EDMA3_0_HWI_INT_XFER_COMP,
242 EDMA3_1_HWI_INT_XFER_COMP
243 };
245 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
246 EDMA3_0_HWI_INT_CC_ERR,
247 EDMA3_1_HWI_INT_CC_ERR
248 };
250 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
251 {
252 EDMA3_0_HWI_INT_TC0_ERR,
253 EDMA3_0_HWI_INT_TC1_ERR,
254 },
255 {
256 EDMA3_1_HWI_INT_TC0_ERR,
257 }
258 };
260 /* Driver Object Initialization Configuration */
261 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
262 {
263 {
264 /* EDMA3 INSTANCE# 0 */
265 /** Total number of DMA Channels supported by the EDMA3 Controller */
266 32u,
267 /** Total number of QDMA Channels supported by the EDMA3 Controller */
268 8u,
269 /** Total number of TCCs supported by the EDMA3 Controller */
270 32u,
271 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
272 128u,
273 /** Total number of Event Queues in the EDMA3 Controller */
274 2u,
275 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
276 2u,
277 /** Number of Regions on this EDMA3 controller */
278 4u,
280 /**
281 * \brief Channel mapping existence
282 * A value of 0 (No channel mapping) implies that there is fixed association
283 * for a channel number to a parameter entry number or, in other words,
284 * PaRAM entry n corresponds to channel n.
285 */
286 0u,
288 /** Existence of memory protection feature */
289 0u,
291 /** Global Register Region of CC Registers */
292 (void *)0x01C00000u,
293 /** Transfer Controller (TC) Registers */
294 {
295 (void *)0x01C08000u,
296 (void *)0x01C08400u,
297 (void *)NULL,
298 (void *)NULL,
299 (void *)NULL,
300 (void *)NULL,
301 (void *)NULL,
302 (void *)NULL
303 },
304 /** Interrupt no. for Transfer Completion */
305 EDMA3_0_CC_XFER_COMPLETION_INT,
306 /** Interrupt no. for CC Error */
307 EDMA3_0_CC_ERROR_INT,
308 /** Interrupt no. for TCs Error */
309 {
310 EDMA3_0_TC0_ERROR_INT,
311 EDMA3_0_TC1_ERROR_INT,
312 EDMA3_0_TC2_ERROR_INT,
313 EDMA3_0_TC3_ERROR_INT,
314 EDMA3_0_TC4_ERROR_INT,
315 EDMA3_0_TC5_ERROR_INT,
316 EDMA3_0_TC6_ERROR_INT,
317 EDMA3_0_TC7_ERROR_INT
318 },
320 /**
321 * \brief EDMA3 TC priority setting
322 *
323 * User can program the priority of the Event Queues
324 * at a system-wide level. This means that the user can set the
325 * priority of an IO initiated by either of the TCs (Transfer Controllers)
326 * relative to IO initiated by the other bus masters on the
327 * device (ARM, DSP, USB, etc)
328 */
329 {
330 0u,
331 1u,
332 0u,
333 0u,
334 0u,
335 0u,
336 0u,
337 0u
338 },
339 /**
340 * \brief To Configure the Threshold level of number of events
341 * that can be queued up in the Event queues. EDMA3CC error register
342 * (CCERR) will indicate whether or not at any instant of time the
343 * number of events queued up in any of the event queues exceeds
344 * or equals the threshold/watermark value that is set
345 * in the queue watermark threshold register (QWMTHRA).
346 */
347 {
348 16u,
349 16u,
350 0u,
351 0u,
352 0u,
353 0u,
354 0u,
355 0u
356 },
358 /**
359 * \brief To Configure the Default Burst Size (DBS) of TCs.
360 * An optimally-sized command is defined by the transfer controller
361 * default burst size (DBS). Different TCs can have different
362 * DBS values. It is defined in Bytes.
363 */
364 {
365 16u,
366 16u,
367 0u,
368 0u,
369 0u,
370 0u,
371 0u,
372 0u
373 },
375 /**
376 * \brief Mapping from each DMA channel to a Parameter RAM set,
377 * if it exists, otherwise of no use.
378 */
379 {
380 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
381 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
382 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
383 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
384 /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
385 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
386 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
387 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
388 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
389 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
390 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
391 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
392 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
393 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
394 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
395 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
396 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
397 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
398 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
399 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
400 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
401 },
403 /**
404 * \brief Mapping from each DMA channel to a TCC. This specific
405 * TCC code will be returned when the transfer is completed
406 * on the mapped channel.
407 */
408 {
409 0u, 1u, 2u, 3u,
410 4u, 5u, 6u, 7u,
411 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
412 12u, 13u, 14u, 15u,
413 16u, 17u, 18u, 19u,
414 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
415 24u, 25u, 26u, 27u,
416 28u, 29u, 30u, 31u,
417 /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
418 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
419 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
420 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
421 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
422 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
423 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
424 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
425 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
426 },
428 /**
429 * \brief Mapping of DMA channels to Hardware Events from
430 * various peripherals, which use EDMA for data transfer.
431 * All channels need not be mapped, some can be free also.
432 */
433 {
434 EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
435 EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
436 }
437 },
439 {
440 /* EDMA3 INSTANCE# 1 */
441 /** Total number of DMA Channels supported by the EDMA3 Controller */
442 32u,
443 /** Total number of QDMA Channels supported by the EDMA3 Controller */
444 8u,
445 /** Total number of TCCs supported by the EDMA3 Controller */
446 32u,
447 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
448 128u,
449 /** Total number of Event Queues in the EDMA3 Controller */
450 1u,
451 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
452 1u,
453 /** Number of Regions on this EDMA3 controller */
454 4u,
456 /**
457 * \brief Channel mapping existence
458 * A value of 0 (No channel mapping) implies that there is fixed association
459 * for a channel number to a parameter entry number or, in other words,
460 * PaRAM entry n corresponds to channel n.
461 */
462 0u,
464 /** Existence of memory protection feature */
465 0u,
467 /** Global Register Region of CC Registers */
468 (void *)0x01E30000u,
469 /** Transfer Controller (TC) Registers */
470 {
471 (void *)0x01E38000u,
472 (void *)NULL,
473 (void *)NULL,
474 (void *)NULL,
475 (void *)NULL,
476 (void *)NULL,
477 (void *)NULL,
478 (void *)NULL
479 },
480 /** Interrupt no. for Transfer Completion */
481 EDMA3_1_CC_XFER_COMPLETION_INT,
482 /** Interrupt no. for CC Error */
483 EDMA3_1_CC_ERROR_INT,
484 /** Interrupt no. for TCs Error */
485 {
486 EDMA3_1_TC0_ERROR_INT,
487 EDMA3_1_TC1_ERROR_INT,
488 EDMA3_1_TC2_ERROR_INT,
489 EDMA3_1_TC3_ERROR_INT,
490 EDMA3_1_TC4_ERROR_INT,
491 EDMA3_1_TC5_ERROR_INT,
492 EDMA3_1_TC6_ERROR_INT,
493 EDMA3_1_TC7_ERROR_INT,
494 },
496 /**
497 * \brief EDMA3 TC priority setting
498 *
499 * User can program the priority of the Event Queues
500 * at a system-wide level. This means that the user can set the
501 * priority of an IO initiated by either of the TCs (Transfer Controllers)
502 * relative to IO initiated by the other bus masters on the
503 * device (ARM, DSP, USB, etc)
504 */
505 {
506 0u,
507 0u,
508 0u,
509 0u,
510 0u,
511 0u,
512 0u,
513 0u
514 },
515 /**
516 * \brief To Configure the Threshold level of number of events
517 * that can be queued up in the Event queues. EDMA3CC error register
518 * (CCERR) will indicate whether or not at any instant of time the
519 * number of events queued up in any of the event queues exceeds
520 * or equals the threshold/watermark value that is set
521 * in the queue watermark threshold register (QWMTHRA).
522 */
523 {
524 16u,
525 0u,
526 0u,
527 0u,
528 0u,
529 0u,
530 0u,
531 0u
532 },
534 /**
535 * \brief To Configure the Default Burst Size (DBS) of TCs.
536 * An optimally-sized command is defined by the transfer controller
537 * default burst size (DBS). Different TCs can have different
538 * DBS values. It is defined in Bytes.
539 */
540 {
541 16u,
542 0u,
543 0u,
544 0u,
545 0u,
546 0u,
547 0u,
548 0u
549 },
551 /**
552 * \brief Mapping from each DMA channel to a Parameter RAM set,
553 * if it exists, otherwise of no use.
554 */
555 {
556 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
557 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
558 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
559 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
560 /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
561 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
562 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
563 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
564 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
565 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
566 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
567 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
568 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
569 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
570 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
571 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
572 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
573 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
574 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
575 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
576 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
577 },
579 /**
580 * \brief Mapping from each DMA channel to a TCC. This specific
581 * TCC code will be returned when the transfer is completed
582 * on the mapped channel.
583 */
584 {
585 0u, 1u, 2u, 3u,
586 4u, 5u, 6u, 7u,
587 8u, 9u, 10u, 11u,
588 12u, 13u, 14u, 15u,
589 16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP,
590 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
591 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
592 24u, 25u, 26u, 27u,
593 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
594 /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
595 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
596 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
597 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
598 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
599 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
600 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
601 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
602 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
603 },
605 /**
606 * \brief Mapping of DMA channels to Hardware Events from
607 * various peripherals, which use EDMA for data transfer.
608 * All channels need not be mapped, some can be free also.
609 */
610 {
611 EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
612 EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
613 }
614 },
615 };
618 /* Driver Instance Initialization Configuration */
619 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
620 {
621 /* EDMA3 INSTANCE# 0 */
622 {
623 /* Resources owned/reserved by region 0 */
624 {
625 /* ownPaRAMSets */
626 /* 31 0 63 32 95 64 127 96 */
627 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
628 /* 159 128 191 160 223 192 255 224 */
629 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
630 /* 287 256 319 288 351 320 383 352 */
631 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
632 /* 415 384 447 416 479 448 511 480 */
633 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
635 /* ownDmaChannels */
636 /* 31 0 63 32 */
637 {0x00000000u, 0x00000000u},
639 /* ownQdmaChannels */
640 /* 31 0 */
641 {0x00000000u},
643 /* ownTccs */
644 /* 31 0 63 32 */
645 {0x00000000u, 0x00000000u},
647 /* resvdPaRAMSets */
648 /* 31 0 63 32 95 64 127 96 */
649 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
650 /* 159 128 191 160 223 192 255 224 */
651 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
652 /* 287 256 319 288 351 320 383 352 */
653 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
654 /* 415 384 447 416 479 448 511 480 */
655 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
657 /* resvdDmaChannels */
658 /* 31 0 63 32 */
659 {0x00000000u, 0x00000000u},
661 /* resvdQdmaChannels */
662 /* 31 0 */
663 {0x00000000u},
665 /* resvdTccs */
666 /* 31 0 63 32 */
667 {0x00000000u, 0x00000000u},
668 },
669 /* Resources owned/reserved by region 1 */
670 {
671 /* ownPaRAMSets */
672 /* 31 0 63 32 95 64 127 96 */
673 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
674 /* 159 128 191 160 223 192 255 224 */
675 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
676 /* 287 256 319 288 351 320 383 352 */
677 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
678 /* 415 384 447 416 479 448 511 480 */
679 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
681 /* ownDmaChannels */
682 /* 31 0 63 32 */
683 {0xFFFFFFFFu, 0x00000000u},
685 /* ownQdmaChannels */
686 /* 31 0 */
687 {0x000000FFu},
689 /* ownTccs */
690 /* 31 0 63 32 */
691 {0xFFFFFFFFu, 0x00000000u},
693 /* Resources reserved by Region 1 */
694 /* resvdPaRAMSets */
695 /* 31 0 63 32 95 64 127 96 */
696 {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
697 /* 159 128 191 160 223 192 255 224 */
698 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
699 /* 287 256 319 288 351 320 383 352 */
700 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
701 /* 415 384 447 416 479 448 511 480 */
702 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
704 /* resvdDmaChannels */
705 /* 31 0 */
706 {0xFF3FF3FFu,
707 /* 63..32 */
708 0x00000000u},
710 /* resvdQdmaChannels */
711 /* 31 0 */
712 {0x00000000u},
714 /* resvdTccs */
715 /* 31 0 */
716 {0xFF3FF3FFu,
717 /* 63..32 */
718 0x00000000u},
719 },
720 /* Resources owned/reserved by region 2 */
721 {
722 /* ownPaRAMSets */
723 /* 31 0 63 32 95 64 127 96 */
724 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
725 /* 159 128 191 160 223 192 255 224 */
726 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
727 /* 287 256 319 288 351 320 383 352 */
728 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
729 /* 415 384 447 416 479 448 511 480 */
730 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
732 /* ownDmaChannels */
733 /* 31 0 63 32 */
734 {0x00000000u, 0x00000000u},
736 /* ownQdmaChannels */
737 /* 31 0 */
738 {0x00000000u},
740 /* ownTccs */
741 /* 31 0 63 32 */
742 {0x00000000u, 0x00000000u},
744 /* resvdPaRAMSets */
745 /* 31 0 63 32 95 64 127 96 */
746 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
747 /* 159 128 191 160 223 192 255 224 */
748 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
749 /* 287 256 319 288 351 320 383 352 */
750 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
751 /* 415 384 447 416 479 448 511 480 */
752 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
754 /* resvdDmaChannels */
755 /* 31 0 63 32 */
756 {0x00000000u, 0x00000000u},
758 /* resvdQdmaChannels */
759 /* 31 0 */
760 {0x00000000u},
762 /* resvdTccs */
763 /* 31 0 63 32 */
764 {0x00000000u, 0x00000000u},
765 },
767 /* Resources owned/reserved by region 3 */
768 {
769 /* ownPaRAMSets */
770 /* 31 0 63 32 95 64 127 96 */
771 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
772 /* 159 128 191 160 223 192 255 224 */
773 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
774 /* 287 256 319 288 351 320 383 352 */
775 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
776 /* 415 384 447 416 479 448 511 480 */
777 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
779 /* ownDmaChannels */
780 /* 31 0 63 32 */
781 {0x00000000u, 0x00000000u},
783 /* ownQdmaChannels */
784 /* 31 0 */
785 {0x00000000u},
787 /* ownTccs */
788 /* 31 0 63 32 */
789 {0x00000000u, 0x00000000u},
791 /* resvdPaRAMSets */
792 /* 31 0 63 32 95 64 127 96 */
793 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
794 /* 159 128 191 160 223 192 255 224 */
795 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
796 /* 287 256 319 288 351 320 383 352 */
797 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
798 /* 415 384 447 416 479 448 511 480 */
799 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
801 /* resvdDmaChannels */
802 /* 31 0 63 32 */
803 {0x00000000u, 0x00000000u},
805 /* resvdQdmaChannels */
806 /* 31 0 */
807 {0x00000000u},
809 /* resvdTccs */
810 /* 31 0 63 32 */
811 {0x00000000u, 0x00000000u},
812 },
814 /* Resources owned/reserved by region 4 */
815 {
816 /* ownPaRAMSets */
817 /* 31 0 63 32 95 64 127 96 */
818 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
819 /* 159 128 191 160 223 192 255 224 */
820 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
821 /* 287 256 319 288 351 320 383 352 */
822 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
823 /* 415 384 447 416 479 448 511 480 */
824 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
826 /* ownDmaChannels */
827 /* 31 0 63 32 */
828 {0x00000000u, 0x00000000u},
830 /* ownQdmaChannels */
831 /* 31 0 */
832 {0x00000000u},
834 /* ownTccs */
835 /* 31 0 63 32 */
836 {0x00000000u, 0x00000000u},
838 /* resvdPaRAMSets */
839 /* 31 0 63 32 95 64 127 96 */
840 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
841 /* 159 128 191 160 223 192 255 224 */
842 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
843 /* 287 256 319 288 351 320 383 352 */
844 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
845 /* 415 384 447 416 479 448 511 480 */
846 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
848 /* resvdDmaChannels */
849 /* 31 0 63 32 */
850 {0x00000000u, 0x00000000u},
852 /* resvdQdmaChannels */
853 /* 31 0 */
854 {0x00000000u},
856 /* resvdTccs */
857 /* 31 0 63 32 */
858 {0x00000000u, 0x00000000u},
859 },
861 /* Resources owned/reserved by region 5 */
862 {
863 /* ownPaRAMSets */
864 /* 31 0 63 32 95 64 127 96 */
865 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
866 /* 159 128 191 160 223 192 255 224 */
867 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
868 /* 287 256 319 288 351 320 383 352 */
869 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
870 /* 415 384 447 416 479 448 511 480 */
871 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
873 /* ownDmaChannels */
874 /* 31 0 63 32 */
875 {0x00000000u, 0x00000000u},
877 /* ownQdmaChannels */
878 /* 31 0 */
879 {0x00000000u},
881 /* ownTccs */
882 /* 31 0 63 32 */
883 {0x00000000u, 0x00000000u},
885 /* resvdPaRAMSets */
886 /* 31 0 63 32 95 64 127 96 */
887 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
888 /* 159 128 191 160 223 192 255 224 */
889 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
890 /* 287 256 319 288 351 320 383 352 */
891 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
892 /* 415 384 447 416 479 448 511 480 */
893 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
895 /* resvdDmaChannels */
896 /* 31 0 63 32 */
897 {0x00000000u, 0x00000000u},
899 /* resvdQdmaChannels */
900 /* 31 0 */
901 {0x00000000u},
903 /* resvdTccs */
904 /* 31 0 63 32 */
905 {0x00000000u, 0x00000000u},
906 },
908 /* Resources owned/reserved by region 6 */
909 {
910 /* ownPaRAMSets */
911 /* 31 0 63 32 95 64 127 96 */
912 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
913 /* 159 128 191 160 223 192 255 224 */
914 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
915 /* 287 256 319 288 351 320 383 352 */
916 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
917 /* 415 384 447 416 479 448 511 480 */
918 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
920 /* ownDmaChannels */
921 /* 31 0 63 32 */
922 {0x00000000u, 0x00000000u},
924 /* ownQdmaChannels */
925 /* 31 0 */
926 {0x00000000u},
928 /* ownTccs */
929 /* 31 0 63 32 */
930 {0x00000000u, 0x00000000u},
932 /* resvdPaRAMSets */
933 /* 31 0 63 32 95 64 127 96 */
934 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
935 /* 159 128 191 160 223 192 255 224 */
936 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
937 /* 287 256 319 288 351 320 383 352 */
938 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
939 /* 415 384 447 416 479 448 511 480 */
940 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
942 /* resvdDmaChannels */
943 /* 31 0 63 32 */
944 {0x00000000u, 0x00000000u},
946 /* resvdQdmaChannels */
947 /* 31 0 */
948 {0x00000000u},
950 /* resvdTccs */
951 /* 31 0 63 32 */
952 {0x00000000u, 0x00000000u},
953 },
955 /* Resources owned/reserved by region 7 */
956 {
957 /* ownPaRAMSets */
958 /* 31 0 63 32 95 64 127 96 */
959 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
960 /* 159 128 191 160 223 192 255 224 */
961 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
962 /* 287 256 319 288 351 320 383 352 */
963 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
964 /* 415 384 447 416 479 448 511 480 */
965 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
967 /* ownDmaChannels */
968 /* 31 0 63 32 */
969 {0x00000000u, 0x00000000u},
971 /* ownQdmaChannels */
972 /* 31 0 */
973 {0x00000000u},
975 /* ownTccs */
976 /* 31 0 63 32 */
977 {0x00000000u, 0x00000000u},
979 /* resvdPaRAMSets */
980 /* 31 0 63 32 95 64 127 96 */
981 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
982 /* 159 128 191 160 223 192 255 224 */
983 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
984 /* 287 256 319 288 351 320 383 352 */
985 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
986 /* 415 384 447 416 479 448 511 480 */
987 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
989 /* resvdDmaChannels */
990 /* 31 0 63 32 */
991 {0x00000000u, 0x00000000u},
993 /* resvdQdmaChannels */
994 /* 31 0 */
995 {0x00000000u},
997 /* resvdTccs */
998 /* 31 0 63 32 */
999 {0x00000000u, 0x00000000u},
1000 },
1001 },
1002 /* EDMA3 INSTANCE# 1 */
1003 {
1004 /* Resources owned/reserved by region 0 */
1005 {
1006 /* ownPaRAMSets */
1007 /* 31 0 63 32 95 64 127 96 */
1008 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1009 /* 159 128 191 160 223 192 255 224 */
1010 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1011 /* 287 256 319 288 351 320 383 352 */
1012 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1013 /* 415 384 447 416 479 448 511 480 */
1014 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1016 /* ownDmaChannels */
1017 /* 31 0 63 32 */
1018 {0x00000000u, 0x00000000u},
1020 /* ownQdmaChannels */
1021 /* 31 0 */
1022 {0x00000000u},
1024 /* ownTccs */
1025 /* 31 0 63 32 */
1026 {0x00000000u, 0x00000000u},
1028 /* resvdPaRAMSets */
1029 /* 31 0 63 32 95 64 127 96 */
1030 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1031 /* 159 128 191 160 223 192 255 224 */
1032 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1033 /* 287 256 319 288 351 320 383 352 */
1034 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1035 /* 415 384 447 416 479 448 511 480 */
1036 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1038 /* resvdDmaChannels */
1039 /* 31 0 63 32 */
1040 {0x00000000u, 0x00000000u},
1042 /* resvdQdmaChannels */
1043 /* 31 0 */
1044 {0x00000000u},
1046 /* resvdTccs */
1047 /* 31 0 63 32 */
1048 {0x00000000u, 0x00000000u},
1049 },
1050 /* Resources owned by Region 1 */
1051 {
1052 /* ownPaRAMSets */
1053 /* 31 0 63 32 95 64 127 96 */
1054 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1055 /* 159 128 191 160 223 192 255 224 */
1056 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1057 /* 287 256 319 288 351 320 383 352 */
1058 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1059 /* 415 384 447 416 479 448 511 480 */
1060 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1062 /* ownDmaChannels */
1063 /* 31 0 63 32 */
1064 {0xFFFFFFFFu, 0x00000000u},
1066 /* ownQdmaChannels */
1067 /* 31 0 */
1068 {0x000000FFu},
1070 /* ownTccs */
1071 /* 31 0 63 32 */
1072 {
1073 0xFFFFFFFFu,
1074 0x00000000u
1075 },
1077 /* Resources reserved by Region 1 */
1078 /* resvdPaRAMSets */
1079 /* 31 0 63 32 95 64 127 96 */
1080 {
1081 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1082 /* 159 128 191 160 223 192 255 224 */
1083 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1084 /* 287 256 319 288 351 320 383 352 */
1085 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1086 /* 415 384 447 416 479 448 511 480 */
1087 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1088 },
1090 /* resvdDmaChannels */
1091 /* 31 0 */
1092 {
1093 0x3F07FFFFu,
1094 /* 63..32 */
1095 0x00000000u
1096 },
1098 /* resvdQdmaChannels */
1099 /* 31 0 */
1100 {
1101 0x00000000u
1102 },
1104 /* resvdTccs */
1105 /* 31 0 */
1106 {
1107 0x3F07FFFFu,
1108 /* 63..32 */
1109 0x00000000u
1110 },
1111 },
1112 /* Resources owned/reserved by region 2 */
1113 {
1114 /* ownPaRAMSets */
1115 /* 31 0 63 32 95 64 127 96 */
1116 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1117 /* 159 128 191 160 223 192 255 224 */
1118 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1119 /* 287 256 319 288 351 320 383 352 */
1120 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1121 /* 415 384 447 416 479 448 511 480 */
1122 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1124 /* ownDmaChannels */
1125 /* 31 0 63 32 */
1126 {0x00000000u, 0x00000000u},
1128 /* ownQdmaChannels */
1129 /* 31 0 */
1130 {0x00000000u},
1132 /* ownTccs */
1133 /* 31 0 63 32 */
1134 {0x00000000u, 0x00000000u},
1136 /* resvdPaRAMSets */
1137 /* 31 0 63 32 95 64 127 96 */
1138 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1139 /* 159 128 191 160 223 192 255 224 */
1140 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1141 /* 287 256 319 288 351 320 383 352 */
1142 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1143 /* 415 384 447 416 479 448 511 480 */
1144 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1146 /* resvdDmaChannels */
1147 /* 31 0 63 32 */
1148 {0x00000000u, 0x00000000u},
1150 /* resvdQdmaChannels */
1151 /* 31 0 */
1152 {0x00000000u},
1154 /* resvdTccs */
1155 /* 31 0 63 32 */
1156 {0x00000000u, 0x00000000u},
1157 },
1159 /* Resources owned/reserved by region 3 */
1160 {
1161 /* ownPaRAMSets */
1162 /* 31 0 63 32 95 64 127 96 */
1163 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1164 /* 159 128 191 160 223 192 255 224 */
1165 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1166 /* 287 256 319 288 351 320 383 352 */
1167 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1168 /* 415 384 447 416 479 448 511 480 */
1169 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1171 /* ownDmaChannels */
1172 /* 31 0 63 32 */
1173 {0x00000000u, 0x00000000u},
1175 /* ownQdmaChannels */
1176 /* 31 0 */
1177 {0x00000000u},
1179 /* ownTccs */
1180 /* 31 0 63 32 */
1181 {0x00000000u, 0x00000000u},
1183 /* resvdPaRAMSets */
1184 /* 31 0 63 32 95 64 127 96 */
1185 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1186 /* 159 128 191 160 223 192 255 224 */
1187 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1188 /* 287 256 319 288 351 320 383 352 */
1189 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1190 /* 415 384 447 416 479 448 511 480 */
1191 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1193 /* resvdDmaChannels */
1194 /* 31 0 63 32 */
1195 {0x00000000u, 0x00000000u},
1197 /* resvdQdmaChannels */
1198 /* 31 0 */
1199 {0x00000000u},
1201 /* resvdTccs */
1202 /* 31 0 63 32 */
1203 {0x00000000u, 0x00000000u},
1204 },
1206 /* Resources owned/reserved by region 4 */
1207 {
1208 /* ownPaRAMSets */
1209 /* 31 0 63 32 95 64 127 96 */
1210 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1211 /* 159 128 191 160 223 192 255 224 */
1212 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1213 /* 287 256 319 288 351 320 383 352 */
1214 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1215 /* 415 384 447 416 479 448 511 480 */
1216 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1218 /* ownDmaChannels */
1219 /* 31 0 63 32 */
1220 {0x00000000u, 0x00000000u},
1222 /* ownQdmaChannels */
1223 /* 31 0 */
1224 {0x00000000u},
1226 /* ownTccs */
1227 /* 31 0 63 32 */
1228 {0x00000000u, 0x00000000u},
1230 /* resvdPaRAMSets */
1231 /* 31 0 63 32 95 64 127 96 */
1232 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1233 /* 159 128 191 160 223 192 255 224 */
1234 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1235 /* 287 256 319 288 351 320 383 352 */
1236 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1237 /* 415 384 447 416 479 448 511 480 */
1238 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1240 /* resvdDmaChannels */
1241 /* 31 0 63 32 */
1242 {0x00000000u, 0x00000000u},
1244 /* resvdQdmaChannels */
1245 /* 31 0 */
1246 {0x00000000u},
1248 /* resvdTccs */
1249 /* 31 0 63 32 */
1250 {0x00000000u, 0x00000000u},
1251 },
1253 /* Resources owned/reserved by region 5 */
1254 {
1255 /* ownPaRAMSets */
1256 /* 31 0 63 32 95 64 127 96 */
1257 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1258 /* 159 128 191 160 223 192 255 224 */
1259 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1260 /* 287 256 319 288 351 320 383 352 */
1261 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1262 /* 415 384 447 416 479 448 511 480 */
1263 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1265 /* ownDmaChannels */
1266 /* 31 0 63 32 */
1267 {0x00000000u, 0x00000000u},
1269 /* ownQdmaChannels */
1270 /* 31 0 */
1271 {0x00000000u},
1273 /* ownTccs */
1274 /* 31 0 63 32 */
1275 {0x00000000u, 0x00000000u},
1277 /* resvdPaRAMSets */
1278 /* 31 0 63 32 95 64 127 96 */
1279 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1280 /* 159 128 191 160 223 192 255 224 */
1281 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1282 /* 287 256 319 288 351 320 383 352 */
1283 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1284 /* 415 384 447 416 479 448 511 480 */
1285 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1287 /* resvdDmaChannels */
1288 /* 31 0 63 32 */
1289 {0x00000000u, 0x00000000u},
1291 /* resvdQdmaChannels */
1292 /* 31 0 */
1293 {0x00000000u},
1295 /* resvdTccs */
1296 /* 31 0 63 32 */
1297 {0x00000000u, 0x00000000u},
1298 },
1300 /* Resources owned/reserved by region 6 */
1301 {
1302 /* ownPaRAMSets */
1303 /* 31 0 63 32 95 64 127 96 */
1304 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1305 /* 159 128 191 160 223 192 255 224 */
1306 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1307 /* 287 256 319 288 351 320 383 352 */
1308 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1309 /* 415 384 447 416 479 448 511 480 */
1310 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1312 /* ownDmaChannels */
1313 /* 31 0 63 32 */
1314 {0x00000000u, 0x00000000u},
1316 /* ownQdmaChannels */
1317 /* 31 0 */
1318 {0x00000000u},
1320 /* ownTccs */
1321 /* 31 0 63 32 */
1322 {0x00000000u, 0x00000000u},
1324 /* resvdPaRAMSets */
1325 /* 31 0 63 32 95 64 127 96 */
1326 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1327 /* 159 128 191 160 223 192 255 224 */
1328 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1329 /* 287 256 319 288 351 320 383 352 */
1330 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1331 /* 415 384 447 416 479 448 511 480 */
1332 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1334 /* resvdDmaChannels */
1335 /* 31 0 63 32 */
1336 {0x00000000u, 0x00000000u},
1338 /* resvdQdmaChannels */
1339 /* 31 0 */
1340 {0x00000000u},
1342 /* resvdTccs */
1343 /* 31 0 63 32 */
1344 {0x00000000u, 0x00000000u},
1345 },
1347 /* Resources owned/reserved by region 7 */
1348 {
1349 /* ownPaRAMSets */
1350 /* 31 0 63 32 95 64 127 96 */
1351 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1352 /* 159 128 191 160 223 192 255 224 */
1353 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1354 /* 287 256 319 288 351 320 383 352 */
1355 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1356 /* 415 384 447 416 479 448 511 480 */
1357 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1359 /* ownDmaChannels */
1360 /* 31 0 63 32 */
1361 {0x00000000u, 0x00000000u},
1363 /* ownQdmaChannels */
1364 /* 31 0 */
1365 {0x00000000u},
1367 /* ownTccs */
1368 /* 31 0 63 32 */
1369 {0x00000000u, 0x00000000u},
1371 /* resvdPaRAMSets */
1372 /* 31 0 63 32 95 64 127 96 */
1373 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1374 /* 159 128 191 160 223 192 255 224 */
1375 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1376 /* 287 256 319 288 351 320 383 352 */
1377 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1378 /* 415 384 447 416 479 448 511 480 */
1379 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1381 /* resvdDmaChannels */
1382 /* 31 0 63 32 */
1383 {0x00000000u, 0x00000000u},
1385 /* resvdQdmaChannels */
1386 /* 31 0 */
1387 {0x00000000u},
1389 /* resvdTccs */
1390 /* 31 0 63 32 */
1391 {0x00000000u, 0x00000000u},
1392 }
1393 }
1394 };
1396 /* End of File */