[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_omapl138_int_reg.c
1 /*
2 * sample_omapl138_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/family/c64p/EventCombiner.h>
41 #include <ti/sysbios/family/c64p/Hwi.h>
43 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
45 /**
46 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
47 * (Not all TC error ISRs need to be registered, register only for the
48 * available Transfer Controllers).
49 */
50 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
51 {
52 &lisrEdma3TC0ErrHandler0,
53 &lisrEdma3TC1ErrHandler0,
54 &lisrEdma3TC2ErrHandler0,
55 &lisrEdma3TC3ErrHandler0,
56 &lisrEdma3TC4ErrHandler0,
57 &lisrEdma3TC5ErrHandler0,
58 &lisrEdma3TC6ErrHandler0,
59 &lisrEdma3TC7ErrHandler0,
60 };
62 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
63 extern unsigned int ccErrorInt[];
64 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
65 extern unsigned int numEdma3Tc[];
67 /**
68 * Variables which will be used internally for referring the hardware interrupt
69 * for various EDMA3 interrupts.
70 */
71 extern unsigned int hwIntXferComp[];
72 extern unsigned int hwIntCcErr[];
73 extern unsigned int hwIntTcErr[];
75 extern unsigned int dsp_num;
77 /** To Register the ISRs with the underlying OS, if required. */
78 void registerEdma3Interrupts (unsigned int edma3Id)
79 {
80 static UInt32 cookie = 0;
81 unsigned int numTc = 0;
83 /* Disabling the global interrupts */
84 cookie = Hwi_disable();
86 /* Enable the Xfer Completion Event Interrupt */
87 EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
88 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
89 edma3Id, 1);
90 EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
92 /* Enable the CC Error Event Interrupt */
93 EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
94 (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
95 edma3Id, 1);
96 EventCombiner_enableEvent(ccErrorInt[edma3Id]);
98 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
99 while (numTc < numEdma3Tc[edma3Id])
100 {
101 EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
102 (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
103 edma3Id, 1);
104 EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
105 numTc++;
106 }
108 /**
109 * Enabling the HWI_ID.
110 * EDMA3 interrupts (transfer completion, CC error etc.)
111 * correspond to different ECM events (SoC specific). These ECM events come
112 * under ECM block XXX (handling those specific ECM events). Normally, block
113 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
114 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
115 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
116 * mapped HWI_INT YYY, one should use the corresponding bitmask in the
117 * API C64_enableIER(), in which the YYY bit is SET.
118 */
119 Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
120 Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
121 Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
123 /* Restore interrupts */
124 Hwi_restore(cookie);
125 }
127 /** To Unregister the ISRs with the underlying OS, if previously registered. */
128 void unregisterEdma3Interrupts (unsigned int edma3Id)
129 {
130 static UInt32 cookie = 0;
131 unsigned int numTc = 0;
133 /* Disabling the global interrupts */
134 cookie = Hwi_disable();
136 /* Disable the Xfer Completion Event Interrupt */
137 EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
139 /* Disable the CC Error Event Interrupt */
140 EventCombiner_disableEvent(ccErrorInt[edma3Id]);
142 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
143 while (numTc < numEdma3Tc[edma3Id])
144 {
145 EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
146 numTc++;
147 }
149 /* Restore interrupts */
150 Hwi_restore(cookie);
151 }