packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6486_cfg.c

   1 /*
   2  * sample_tci6486_cfg.c
   3  *
   4  * Platform specific EDMA3 hardware related information like number of transfer
   5  * controllers, various interrupt ids etc. It is used while interrupts
   6  * enabling / disabling. It needs to be ported for different SoCs.
   7  *
   8  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   9  *
  10  *
  11  *  Redistribution and use in source and binary forms, with or without
  12  *  modification, are permitted provided that the following conditions
  13  *  are met:
  14  *
  15  *    Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  *
  18  *    Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the
  21  *    distribution.
  22  *
  23  *    Neither the name of Texas Instruments Incorporated nor the names of
  24  *    its contributors may be used to endorse or promote products derived
  25  *    from this software without specific prior written permission.
  26  *
  27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39 */
  40
  41 #include <ti/sdo/edma3/rm/edma3_rm.h>
  42
  43 /* Number of EDMA3 controllers present in the system */
  44 #define NUM_EDMA3_INSTANCES                     1u
  45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
  46
  47 /* Number of DSPs present in the system */
  48 #define NUM_DSPS                                        6u
  49
  50 extern cregister volatile unsigned int DNUM;
  51
  52 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
  53 /* Determine the processor id by reading DNUM register. */
  54 unsigned short determineProcId()
  55         {
  56     /* Identify the core number */
  57         return (unsigned short)DNUM;
  58         }
  59
  60 signed char*  getGlobalAddr(signed char* addr)
  61 {
  62     if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
  63     {
  64         return (addr); /* The address is already a global address */
  65     }
  66
  67     return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
  68 }
  69
  70
  71 /** Whether global configuration required for EDMA3 or not.
  72  * This configuration should be done only once for the EDMA3 hardware by
  73  * any one of the masters (i.e. DSPs).
  74  * It can be changed depending on the use-case.
  75  */
  76 unsigned int gblCfgReqdArray [NUM_DSPS] = {
  77                                                                         0,      /* DSP#0 is Master, will do the global init */
  78                                                                         1,      /* DSP#1 is Slave, will not do the global init  */
  79                                                                         1,      /* DSP#2 is Slave, will not do the global init  */
  80                                                                         1,      /* DSP#3 is Slave, will not do the global init  */
  81                                                                         1,      /* DSP#4 is Slave, will not do the global init  */
  82                                                                         1,      /* DSP#5 is Slave, will not do the global init  */
  83                                                                         };
  84
  85 unsigned short isGblConfigRequired(unsigned int dspNum)
  86         {
  87         return gblCfgReqdArray[dspNum];
  88         }
  89
  90 /**
  91 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
  92 * ECM events (SoC specific). These ECM events come
  93 * under ECM block XXX (handling those specific ECM events). Normally, block
  94 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
  95 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
  96 * is mapped to a specific HWI_INT YYY in the tcf file.
  97 * For TCI6488, following mappings has been done:
  98 * ECM Block 0 (Events 04-31) --> HWI Interrupt 7
  99 * ECM Block 1 (Events 32-63) --> HWI Interrupt 8
 100 * ECM Block 2 (Events 64-95) --> HWI Interrupt 9
 101 * ECM Block 3 (Events 96-127) --> HWI Interrupt 10
 102 * These defines below specify which ECM event is mapped to which HWI interrupt.
 103 * Define EDMA3_HWI_INT_XFER_COMP[n] to specific HWI_INT, corresponding
 104 * to transfer completion interrupt, on that particular DSP core.
 105 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
 106 * to CC error interrupts.
 107 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
 108 * to TC error interrupts.
 109 */
 110 /* Transfer completion interrupt for DSP 0 lies in ECM block 0. */
 111 #define EDMA3_HWI_INT_XFER_COMP_0                                               (7u)
 112 /* Transfer completion interrupt for DSP 1 lies in ECM block 0. */
 113 #define EDMA3_HWI_INT_XFER_COMP_1                                               (7u)
 114 /* Transfer completion interrupt for DSP 2 lies in ECM block 0. */
 115 #define EDMA3_HWI_INT_XFER_COMP_2                                               (7u)
 116 /* Transfer completion interrupt for DSP 3 lies in ECM block 0. */
 117 #define EDMA3_HWI_INT_XFER_COMP_3                                               (7u)
 118 /* Transfer completion interrupt for DSP 4 lies in ECM block 0. */
 119 #define EDMA3_HWI_INT_XFER_COMP_4                                               (7u)
 120 /* Transfer completion interrupt for DSP 5 lies in ECM block 0. */
 121 #define EDMA3_HWI_INT_XFER_COMP_5                                               (7u)
 122
 123 /** CC Error Interrupt lies in ECM block 1.                     */
 124 #define EDMA3_HWI_INT_CC_ERR                                                    (8u)
 125
 126 /* TC0 Error interrupt in ECM block 1.                          */
 127 #define EDMA3_HWI_INT_TC_ERR_0                                                  (8u)
 128 /* TC1 Error interrupt in ECM block 1.                          */
 129 #define EDMA3_HWI_INT_TC_ERR_1                                                  (8u)
 130 /* TC0 Error interrupt in ECM block 1.                          */
 131 #define EDMA3_HWI_INT_TC_ERR_2                                                  (8u)
 132 /* TC1 Error interrupt in ECM block 1.                          */
 133 #define EDMA3_HWI_INT_TC_ERR_3                                                  (8u)
 134
 135 /* Semaphore handles */
 136 EDMA3_OS_Sem_Handle SemHandle[NUM_EDMA3_INSTANCES] = {NULL};
 137
 138
 139 /* Variable which will be used internally for referring number of Event Queues. */
 140 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {4u};
 141
 142 /* Variable which will be used internally for referring number of TCs. */
 143 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {4u};
 144
 145 /**
 146  * Variable which will be used internally for referring transfer completion
 147  * interrupt. Completion interrupts for all the shadow regions and all the
 148  * EDMA3 controllers are captured since it is a multi-DSP platform.
 149  */
 150 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
 151                                                                                                         {
 152                                                                                                         15u, 15u, 15u, 15u,
 153                                                                                                         15u, 15u, 67u, 68u,
 154                                                                                                         },
 155                                                                                                 };
 156
 157 /**
 158  * Variable which will be used internally for referring channel controller's
 159  * error interrupt.
 160  */
 161 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {57u};
 162
 163 /**
 164  * Variable which will be used internally for referring transfer controllers'
 165  * error interrupts.
 166  */
 167 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
 168                                                                                                         {
 169                                                                                                         59u, 60u, 61u, 62u,
 170                                                                                                         0u, 0u, 0u, 0u,
 171                                                                                                         },
 172                                                                                                 };
 173
 174 /**
 175  * Variables which will be used internally for referring the hardware interrupt
 176  * for various EDMA3 interrupts.
 177  */
 178 unsigned int hwIntXferComp[NUM_DSPS] = {
 179                                                                 EDMA3_HWI_INT_XFER_COMP_0,
 180                                                                 EDMA3_HWI_INT_XFER_COMP_1,
 181                                                                 EDMA3_HWI_INT_XFER_COMP_2,
 182                                                                 EDMA3_HWI_INT_XFER_COMP_3,
 183                                                                 EDMA3_HWI_INT_XFER_COMP_4,
 184                                                                 EDMA3_HWI_INT_XFER_COMP_5
 185                                                                 };
 186 unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
 187 unsigned int hwIntTcErr[EDMA3_MAX_REGIONS]  = {
 188                                                                 EDMA3_HWI_INT_TC_ERR_0,
 189                                                                 EDMA3_HWI_INT_TC_ERR_1,
 190                                                                 EDMA3_HWI_INT_TC_ERR_2,
 191                                                                 EDMA3_HWI_INT_TC_ERR_3,
 192                                                                 0u,
 193                                                                 0u,
 194                                                                 0u,
 195                                                                 0u
 196                                                                 };
 197
 198 /* Driver Object Initialization Configuration */
 199 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
 200         {
 201                 {
 202                 /** Total number of DMA Channels supported by the EDMA3 Controller */
 203                 64u,
 204                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
 205                 4u,
 206                 /** Total number of TCCs supported by the EDMA3 Controller */
 207                 64u,
 208                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
 209                 256u,
 210                 /** Total number of Event Queues in the EDMA3 Controller */
 211                 4u,
 212                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
 213                 4u,
 214                 /** Number of Regions on this EDMA3 controller */
 215                 8u,
 216
 217                 /**
 218                  * \brief Channel mapping existence
 219                  * A value of 0 (No channel mapping) implies that there is fixed association
 220                  * for a channel number to a parameter entry number or, in other words,
 221                  * PaRAM entry n corresponds to channel n.
 222                  */
 223                 1u,
 224
 225                 /** Existence of memory protection feature */
 226                 1u,
 227
 228                 /** Global Register Region of CC Registers */
 229                 (void *)0x02A00000u,
 230                 /** Transfer Controller (TC) Registers */
 231                 {
 232                 (void *)0x02A20000u,
 233                 (void *)0x02A28000u,
 234                 (void *)0x02A30000u,
 235                 (void *)0x02A38000u,
 236                 (void *)NULL,
 237                 (void *)NULL,
 238                 (void *)NULL,
 239                 (void *)NULL
 240                 },
 241                 /** Interrupt no. for Transfer Completion */
 242                 15u,
 243                 /** Interrupt no. for CC Error */
 244                 57u,
 245                 /** Interrupt no. for TCs Error */
 246                 {
 247                 59u,
 248                 60u,
 249                 61u,
 250                 62u,
 251                 0u,
 252                 0u,
 253                 0u,
 254                 0u,
 255                 },
 256
 257                 /**
 258                  * \brief EDMA3 TC priority setting
 259                  *
 260                  * User can program the priority of the Event Queues
 261                  * at a system-wide level.  This means that the user can set the
 262                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
 263                  * relative to IO initiated by the other bus masters on the
 264                  * device (ARM, DSP, USB, etc)
 265                  */
 266                 {
 267                 0u,
 268                 1u,
 269                 2u,
 270                 3u,
 271                 0u,
 272                 0u,
 273                 0u,
 274                 0u
 275                 },
 276                 /**
 277                  * \brief To Configure the Threshold level of number of events
 278                  * that can be queued up in the Event queues. EDMA3CC error register
 279                  * (CCERR) will indicate whether or not at any instant of time the
 280                  * number of events queued up in any of the event queues exceeds
 281                  * or equals the threshold/watermark value that is set
 282                  * in the queue watermark threshold register (QWMTHRA).
 283                  */
 284                 {
 285                 16u,
 286                 16u,
 287                 16u,
 288                 16u,
 289                 0u,
 290                 0u,
 291                 0u,
 292                 0u
 293                 },
 294
 295                 /**
 296                  * \brief To Configure the Default Burst Size (DBS) of TCs.
 297                  * An optimally-sized command is defined by the transfer controller
 298                  * default burst size (DBS). Different TCs can have different
 299                  * DBS values. It is defined in Bytes.
 300                  */
 301                 {
 302                 64u,
 303                 64u,
 304                 64u,
 305                 64u,
 306                 0u,
 307                 0u,
 308                 0u,
 309                 0u
 310                 },
 311
 312                 /**
 313                  * \brief Mapping from each DMA channel to a Parameter RAM set,
 314                  * if it exists, otherwise of no use.
 315                  */
 316                 {
 317         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 318         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 319         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 320         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 321         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 322         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 323         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 324         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 325         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 326         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 327         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 328         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 329         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 330         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 331         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 332         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 333         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 334         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 335         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 336         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 337         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 338         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 339         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 340         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 341         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 342         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 343         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 344         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 345         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 346         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 347         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 348         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
 349                 },
 350
 351                  /**
 352                   * \brief Mapping from each DMA channel to a TCC. This specific
 353                   * TCC code will be returned when the transfer is completed
 354                   * on the mapped channel.
 355                   */
 356                 {
 357         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 358         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 359         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 360         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 361         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 362         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 363         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 364         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 365         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 366         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 367         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 368         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 369         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 370         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 371         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 372         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
 373                 },
 374
 375                 /**
 376                  * \brief Mapping of DMA channels to Hardware Events from
 377                  * various peripherals, which use EDMA for data transfer.
 378                  * All channels need not be mapped, some can be free also.
 379                  */
 380                 {
 381                 0x00000000u,
 382                 0x00000000u
 383                 }
 384                 }
 385         };
 386
 387 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 388 {
 389         {
 390           {
 391                 /* Resources owned by Region 0 */
 392                  /* ownPaRAMSets */
 393                 /* 31     0     63    32     95    64     127   96 */
 394                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
 395                 /* 159  128     191  160     223  192     255  224 */
 396                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 397                 /* 287  256     319  288     351  320     383  352 */
 398                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 399                 /* 415  384     447  416     479  448     511  480 */
 400                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 401
 402                 /* ownDmaChannels */
 403                 /* 31     0     63    32 */
 404                 {0x0000FFFFu, 0x00000000u},
 405
 406                 /* ownQdmaChannels */
 407                 /* 31     0 */
 408                 {0x00000001u},
 409
 410                 /* ownTccs */
 411                 /* 31     0     63    32 */
 412                 {0x0000FFFFu, 0x00000000u},
 413
 414                 /* Resources reserved by Region 0 */
 415                 /* resvdPaRAMSets */
 416                 /* 31     0     63    32     95    64     127   96 */
 417                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 418                 /* 159  128     191  160     223  192     255  224 */
 419                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 420                 /* 287  256     319  288     351  320     383  352 */
 421                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 422                 /* 415  384     447  416     479  448     511  480 */
 423                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 424
 425                 /* resvdDmaChannels */
 426         /* 31     0    63     32 */
 427         {0x00000000u, 0x00000000u},
 428
 429                 /* resvdQdmaChannels */
 430                 /* 31     0 */
 431                 {0x00000000u},
 432
 433                 /* resvdTccs */
 434         /* 31     0    63     32 */
 435         {0x00000000u, 0x00000000u},
 436           },
 437
 438           {
 439                 /* Resources owned by Region 1 */
 440                 /* ownPaRAMSets */
 441                 /* 31     0     63    32     95    64     127   96 */
 442                 {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
 443                 /* 159  128     191  160     223  192     255  224 */
 444                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 445                 /* 287  256     319  288     351  320     383  352 */
 446                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 447                 /* 415  384     447  416     479  448     511  480 */
 448                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 449
 450                 /* ownDmaChannels */
 451                 /* 31     0     63    32 */
 452                 {0xFFFF0000u, 0x00000000u},
 453
 454                 /* ownQdmaChannels */
 455                 /* 31     0 */
 456                 {0x00000002u},
 457
 458                 /* ownTccs */
 459                 /* 31     0     63    32 */
 460                 {0xFFFF0000u, 0x00000000u},
 461
 462                 /* Resources reserved by Region 1 */
 463                 /* resvdPaRAMSets */
 464                 /* 31     0     63    32     95    64     127   96 */
 465                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 466                 /* 159  128     191  160     223  192     255  224 */
 467                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 468                 /* 287  256     319  288     351  320     383  352 */
 469                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 470                 /* 415  384     447  416     479  448     511  480 */
 471                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 472
 473                 /* resvdDmaChannels */
 474         /* 31     0    63     32 */
 475         {0x00000000u, 0x00000000u},
 476
 477                 /* resvdQdmaChannels */
 478                 /* 31     0 */
 479                 {0x00000000u},
 480
 481                 /* resvdTccs */
 482         /* 31     0    63     32 */
 483         {0x00000000u, 0x00000000u},
 484           },
 485
 486           {
 487                 /* Resources owned by Region 2 */
 488                  /* ownPaRAMSets */
 489                 /* 31     0     63    32     95    64     127   96 */
 490                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 491                 /* 159  128     191  160     223  192     255  224 */
 492                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
 493                 /* 287  256     319  288     351  320     383  352 */
 494                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 495                 /* 415  384     447  416     479  448     511  480 */
 496                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 497
 498                 /* ownDmaChannels */
 499                 /* 31     0     63    32 */
 500                 {0x00000000u, 0x000000FFu},
 501
 502                 /* ownQdmaChannels */
 503                 /* 31     0 */
 504                 {0x00000004u},
 505
 506                 /* ownTccs */
 507                 /* 31     0     63    32 */
 508                 {0x00000000u, 0x000000FFu},
 509
 510                 /* Resources reserved by Region 2 */
 511                 /* resvdPaRAMSets */
 512                 /* 31     0     63    32     95    64     127   96 */
 513                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 514                 /* 159  128     191  160     223  192     255  224 */
 515                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 516                 /* 287  256     319  288     351  320     383  352 */
 517                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 518                 /* 415  384     447  416     479  448     511  480 */
 519                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 520
 521                 /* resvdDmaChannels */
 522         /* 31     0    63     32 */
 523         {0x00000000u, 0x00000000u},
 524
 525                 /* resvdQdmaChannels */
 526                 /* 31     0 */
 527                 {0x00000000u},
 528
 529                 /* resvdTccs */
 530         /* 31     0    63     32 */
 531         {0x00000000u, 0x00000000u},
 532           },
 533
 534           {
 535                 /* Resources owned by Region 3 */
 536                  /* ownPaRAMSets */
 537                 /* 31     0     63    32     95    64     127   96 */
 538                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 539                 /* 159  128     191  160     223  192     255  224 */
 540                  0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 541                 /* 287  256     319  288     351  320     383  352 */
 542                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 543                 /* 415  384     447  416     479  448     511  480 */
 544                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 545
 546                 /* ownDmaChannels */
 547                 /* 31     0     63    32 */
 548                 {0x00000000u, 0x0000FF00u},
 549
 550                 /* ownQdmaChannels */
 551                 /* 31     0 */
 552                 {0x00000008u},
 553
 554                 /* ownTccs */
 555                 /* 31     0     63    32 */
 556                 {0x00000000u, 0x0000FF00u},
 557
 558                 /* Resources reserved by Region 3 */
 559                 /* resvdPaRAMSets */
 560                 /* 31     0     63    32     95    64     127   96 */
 561                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 562                 /* 159  128     191  160     223  192     255  224 */
 563                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 564                 /* 287  256     319  288     351  320     383  352 */
 565                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 566                 /* 415  384     447  416     479  448     511  480 */
 567                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 568
 569                 /* resvdDmaChannels */
 570                 /* 31     0     63    32 */
 571                 {0x00000000u, 0x00000000u},
 572
 573                 /* resvdQdmaChannels */
 574                 /* 31     0 */
 575                 {0x00000000u},
 576
 577                 /* resvdTccs */
 578                 /* 31     0     63    32 */
 579                 {0x00000000u, 0x00000000u},
 580           },
 581
 582           {
 583                 /* Resources owned by Region 4 */
 584                  /* ownPaRAMSets */
 585                 /* 31     0     63    32     95    64     127   96 */
 586                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 587                 /* 159  128     191  160     223  192     255  224 */
 588                  0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
 589                 /* 287  256     319  288     351  320     383  352 */
 590                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 591                 /* 415  384     447  416     479  448     511  480 */
 592                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 593
 594                 /* ownDmaChannels */
 595                 /* 31     0     63    32 */
 596                 {0x00000000u, 0x00FF0000u},
 597
 598                 /* ownQdmaChannels */
 599                 /* 31     0 */
 600                 {0x00000008u},
 601
 602                 /* ownTccs */
 603                 /* 31     0     63    32 */
 604                 {0x00000000u, 0x00FF0000u},
 605
 606                 /* Resources reserved by Region 4 */
 607                 /* resvdPaRAMSets */
 608                 /* 31     0     63    32     95    64     127   96 */
 609                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 610                 /* 159  128     191  160     223  192     255  224 */
 611                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 612                 /* 287  256     319  288     351  320     383  352 */
 613                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 614                 /* 415  384     447  416     479  448     511  480 */
 615                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 616
 617                 /* resvdDmaChannels */
 618                 /* 31     0     63    32 */
 619                 {0x00000000u, 0x00000000u},
 620
 621                 /* resvdQdmaChannels */
 622                 /* 31     0 */
 623                 {0x00000000u},
 624
 625                 /* resvdTccs */
 626                 /* 31     0     63    32 */
 627                 {0x00000000u, 0x00000000u},
 628           },
 629
 630           {
 631                 /* Resources owned by Region 5 */
 632                  /* ownPaRAMSets */
 633                 /* 31     0     63    32     95    64     127   96 */
 634                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 635                 /* 159  128     191  160     223  192     255  224 */
 636                  0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
 637                 /* 287  256     319  288     351  320     383  352 */
 638                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 639                 /* 415  384     447  416     479  448     511  480 */
 640                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 641
 642                 /* ownDmaChannels */
 643                 /* 31     0     63    32 */
 644                 {0x00000000u, 0xFF000000u},
 645
 646                 /* ownQdmaChannels */
 647                 /* 31     0 */
 648                 {0x00000008u},
 649
 650                 /* ownTccs */
 651                 /* 31     0     63    32 */
 652                 {0x00000000u, 0xFF000000u},
 653
 654                 /* Resources reserved by Region 5 */
 655                 /* resvdPaRAMSets */
 656                 /* 31     0     63    32     95    64     127   96 */
 657                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
 658                 /* 159  128     191  160     223  192     255  224 */
 659                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 660                 /* 287  256     319  288     351  320     383  352 */
 661                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 662                 /* 415  384     447  416     479  448     511  480 */
 663                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 664
 665                 /* resvdDmaChannels */
 666                 /* 31     0     63    32 */
 667                 {0x00000000u, 0x00000000u},
 668
 669                 /* resvdQdmaChannels */
 670                 /* 31     0 */
 671                 {0x00000000u},
 672
 673                 /* resvdTccs */
 674                 /* 31     0     63    32 */
 675                 {0x00000000u, 0x00000000u},
 676           },
 677
 678       {
 679         /* Resources owned by Region 6 */
 680          /* ownPaRAMSets */
 681         /* 31     0     63    32     95    64     127   96 */
 682         {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 683         /* 159  128     191  160     223  192     255  224 */
 684          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 685         /* 287  256     319  288     351  320     383  352 */
 686          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 687         /* 415  384     447  416     479  448     511  480 */
 688          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 689
 690         /* ownDmaChannels */
 691         /* 31     0     63    32 */
 692         {0x00000000u, 0x00000000u},
 693
 694         /* ownQdmaChannels */
 695         /* 31     0 */
 696         {0x00000000u},
 697
 698         /* ownTccs */
 699         /* 31     0     63    32 */
 700         {0x00000000u, 0x00000000u},
 701
 702         /* Resources reserved by Region 6 */
 703         /* resvdPaRAMSets */
 704         /* 31     0     63    32     95    64     127   96 */
 705         {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 706         /* 159  128     191  160     223  192     255  224 */
 707          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 708         /* 287  256     319  288     351  320     383  352 */
 709          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 710         /* 415  384     447  416     479  448     511  480 */
 711          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 712
 713         /* resvdDmaChannels */
 714         /* 31     0     63    32 */
 715         {0x00000000u, 0x00000000u},
 716
 717         /* resvdQdmaChannels */
 718         /* 31     0 */
 719         {0x00000000u},
 720
 721         /* resvdTccs */
 722         /* 31     0     63    32 */
 723         {0x00000000u, 0x00000000u},
 724       },
 725
 726       {
 727         /* Resources owned by Region 7 */
 728          /* ownPaRAMSets */
 729         /* 31     0     63    32     95    64     127   96 */
 730         {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 731         /* 159  128     191  160     223  192     255  224 */
 732          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 733         /* 287  256     319  288     351  320     383  352 */
 734          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 735         /* 415  384     447  416     479  448     511  480 */
 736          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 737
 738         /* ownDmaChannels */
 739         /* 31     0     63    32 */
 740         {0x00000000u, 0x00000000u},
 741
 742         /* ownQdmaChannels */
 743         /* 31     0 */
 744         {0x00000000u},
 745
 746         /* ownTccs */
 747         /* 31     0     63    32 */
 748         {0x00000000u, 0x00000000u},
 749
 750         /* Resources reserved by Region 7 */
 751         /* resvdPaRAMSets */
 752         /* 31     0     63    32     95    64     127   96 */
 753         {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 754         /* 159  128     191  160     223  192     255  224 */
 755          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 756         /* 287  256     319  288     351  320     383  352 */
 757          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 758         /* 415  384     447  416     479  448     511  480 */
 759          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 760
 761         /* resvdDmaChannels */
 762         /* 31     0     63    32 */
 763         {0x00000000u, 0x00000000u},
 764
 765         /* resvdQdmaChannels */
 766         /* 31     0 */
 767         {0x00000000u},
 768
 769         /* resvdTccs */
 770         /* 31     0     63    32 */
 771         {0x00000000u, 0x00000000u},
 772       }
 773         }
 774 };
 775
 776 /* End of File */